BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5841A UCN5842A

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5841A UCN5842A

Datasheet Thumbnail

Top Searches for this datasheet

5841 5842
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5841A UCN5842A
CLOCK SERIAL DATA LOGIC GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE
SHIFT REGISTER
Data Sheet 26185.14E
LATCHES
merging low-power CMOS logic bipolar output power drivers permit UCN5841/42A, UCN5841/42LW, A5841/42SLW integrated circuits used wide variety peripheral power driver applications. Each device eight-bit CMOS shift register CMOS control circuitry, eight CMOS data latches, eight bipolar current-sinking Darlington output drivers. Darlington outputs, with integral transient-suppression diodes, suitable with relays, solenoids, other inductive loads. Except packaging maximum driver output voltage ratings, UCN5841A, UCN5841LW, A5841SLW, UCN5842A, UCN5842LW, A5842SLW identical. package variations 5842 offer premium performance with minimum output-breakdown voltage rating sustaining). drivers operated with split supply where negative supply BiMOS devices have higher data-input rates than earlier BiMOS circuits. With logic supply, they will typically operate better than MHz. With supply, significantly higher speeds obtained. CMOS inputs compatible with standard CMOS NMOS logic levels. circuits require appropriate pull-up resistors. using serial data output, drivers cascaded interface applications requiring additional drive lines. Suffix devices furnished standard 18-pin plastic DIP; suffix `LW' indicates 18-lead surface-mountable wide-body SOIC package; A5841SLW A5842SLW provided 20lead wide-body SOIC package with improved thermal characteristics. UCN5841LW driver also available operation over extended temperature range -40°C. order, change prefix `UCN' `UCQ'.
Dwg. PP-026-1
Note that UCN584xA (dual in-line package) UCN584xLW (small-outline package) electrically identical share common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS 25°C Free-Air Temperature
Output Voltage, (5841) (5842) Output Voltage, VCE(sus) (5841) (5842) Logic Supply Voltage Range, with Reference Emitter Supply Voltage, Input Voltage Range, -0.3 Continuous Output Current, IOUT Package Power Dissipation, Graph Operating Temperature Range, -20°C +85°C Storage Temperature Range, -55°C +150°C
inductive load applications. Caution: CMOS devices have input static protection susceptible damage when exposed extremely high static electrical charges.
FEATURES
Data-Input Rate CMOS, NMOS, Compatible Inputs Internal Pull-Up/Pull-Down Resistors Low-Power CMOS Logic Latches, High-Voltage Current-Sink Outputs Output Transient-Protection Diodes Single Split Supply Operation SOIC Packaging Automotive Capable Always order complete part number, e.g., A5841SLW
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
(`A' Package Shown)
CLOCK SERIAL DATA LOGIC GROUND
LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE (ACTIVE LOW)
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BIPOLAR
POWER GROUND
Dwg. FP-013-2
ALLOWABLE PACKAGE POWER DISSIPATION WATTS
A5841SLW A5842SLW
POWER GROUND CLOCK SERIAL DATA GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE POWER GROUND CONNECT. CONNECT.
LATCHES
18-PIN DIP, 60°C/W 20-LEAD SOIC, 70°C/W 18-LEAD SOIC, 80°C/W
SHIFT REGISTER
AMBIENT TEMPERATURE
Dwg. PP-029-3
Dwg. GP-022-4
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 1985, 1999 Allegro MicroSystems, Inc.
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS +25°C, (unless otherwise specified).
Applicable Characteristic Output Leakage Current Symbol ICEX Devices 5841* Test Conditions VOUT VOUT +70°C 5842* VOUT VOUT +70°C Collector-Emitter Saturation Voltage VCE(SAT) IOUT IOUT IOUT Collector-Emitter Sustaining Voltage Input Voltage VCE(sus) 5841* 5842* VIN(0) VIN(1) Input Resistance Supply Current IDD(ON) Drivers Drivers Drivers IDD(OFF) Drivers OFF, Drivers OFF, Drivers OFF, Clamp Diode Leakage Current Clamp Diode Forward Voltage 5841* 5842* IOUT IOUT Min. 10.5 Limits Max. Unit
Complete part number includes prefix UCN) suffix SLW) follows: UCN5841A, UCN5841LW, A5841SLW, UCN5842A, UCN5842LW, A5842SLW.
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
CLOCK DATA STROBE
STROBE OUTPUT ENABLE
OUTPUT ENABLE
Dwg. A-12,627 Dwg. EP-010-3
TIMING CONDITIONS
+25°C, Logic Levels Ground)
Minimum Data Active Time Before Clock Pulse (Data Set-Up Time)
CLOCK SERIAL DATA
Minimum Data Active Time After Clock Pulse (Data Hold Time) Minimum Data Pulse Width Minimum Clock Pulse Width Minimum Time Between Clock Activation Strobe Minimum Strobe Pulse Width
Dwg. EP-010-4A
Typical Time Between Strobe Activation Output Transition
TYPICAL OUTPUT DRIVER
Serial Data present input transferred shift register logic logic transition CLOCK input pulse. succeeding CLOCK pulses, registers shift data information towards SERIAL DATA OUTPUT. SERIAL DATA must appear input prior rising edge CLOCK input waveform. Information present register transferred respective latch when STROBE high (serial-to-parallel conversion). latches will continue accept data long STROBE held high. Applications where latches bypassed (STROBE tied high) will require that ENABLE input high during serial data entry. When ENABLE input high, output buffers disabled (OFF) without affecting information stored latches shift register. With ENABLE input low, outputs controlled state latches.
Dwg. EP-021-8
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
TYPICAL APPLICATION
RELAY/SOLENOID DRIVER Using Split Supply
UCN5842A
Dwg. A-12,547
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input Serial Data Strobe Output Input
Logic Level High Logic Level Irrelevant
Latch Contents Output Enable
Output Contents
Present State
Previous State
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5841A UCN5842A
Dimensions Inches (controlling dimensions)
0.014 0.008
0.430 0.280 0.240
0.300
0.070 0.045
0.100 0.920 0.880
0.005
0.210
0.015
0.150 0.115 0.022 0.014
Dwg. MA-001-18A
Dimensions Millimeters (for reference only)
0.355 0.204
10.92 7.11 6.10
7.62
1.77 1.15
2.54 23.37 22.35
0.13
5.33
0.39
3.81 2.93 0.558 0.356
Dwg. MA-001-18A
NOTES: Exact body lead configuration vendor's option within limits shown. Lead spacing tolerance non-cumulative. Lead thickness measured seating plane below.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
UCN5841LW UCN5842LW
Dimensions Inches (for reference only)
0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
0.4625 0.4469
0.050
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-18A
Dimensions Millimeters (controlling dimensions)
0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
11.75 11.35
1.27
2.65 2.35 0.10 MIN. Exact body lead configuration vendor's option within limits shown. Lead spacing tolerance non-cumulative.
Dwg. MA-008-18A
NOTES:
5841 5842 8-BIT SERIAL-INPUT, LATCHED DRIVERS
A5841SLW A5842SLW
Dimensions Inches (for reference only)
0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
0.5118 0.4961
0.050
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-20
Dimensions Millimeters (controlling dimensions)
0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
13.00 12.60
1.27
2.65 2.35 0.10 MIN.
NOTES:
Exact body lead configuration vendor's option within limits shown. Lead spacing tolerance non-cumulative.
Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements design products. Dwg. MA-008-20 information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringements patents other rights third parties which result from use.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVERS UCN5841A UCN5842A

Top Searches for this datasheet

Other recent searches