10-Bit, MSPS Dual TxDAC+® Converter AD9763* DVDD DCOM AVDD ACOM C
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FEATURES 10-Bit Dual Transmit MSPS Update Rate Excellent SFDR IMD: Excellent Gain Offset Matching: 0.25% Fully Independent Gain Control Dual Port Interleaved Data On-Chip Reference Single Supply Operation Power Dissipation: Power-Down Mode: 48-Lead LQFP APPLICATIONS Communications Base Stations Digital Synthesis Quadrature Modulation PRODUCT DESCRIPTION
10-Bit, MSPS Dual TxDAC+® Converter AD9763*
DVDD DCOM AVDD ACOM CLK1 IOUTA1 IOUTB1 REFIO FSADJ1 FSADJ2 SLEEP IOUTA2 IOUTB2 PORT1 LATCH
WRT1 WRT2
REFERENCE DIGITAL INTERFACE
AD9763
BIAS GENERATOR LATCH
PORT2
MODE
CLK2
AD9763 dual port, high speed, two-channel, 10-bit CMOS DAC. integrates high quality 10-bit TxDAC+ cores, voltage reference digital interface circuitry into small 48-lead LQFP package. AD9763 offers exceptional performance while supporting update rates MSPS. AD9763 been optimized processing data communications applications. digital interface consists double-buffered latches well control logic. Separate write inputs allow data written ports independent another. Separate clocks control update rate DACs. mode control allows AD9763 interface separate data ports, single interleaved high speed data port. interleaving mode input data stream demuxed into original data then latched. data then converted DACs updated half input data rate. DACs utilize segmented current source architecture combined with proprietary switching technique reduce glitch energy maximize dynamic accuracy. Each provides differential current output thus supporting single-ended differential applications. Both DACs simultaneously updated provide nominal full-scale current full-scale currents between each matched within 0.25%.
AD9763 manufactured advanced cost CMOS process. operates from single supply consumes power.
PRODUCT HIGHLIGHTS
AD9763 member pin-compatible family dual TxDACs providing 10-, 14-bit resolution. Dual 10-Bit, MSPS DACs: pair high performance DACs optimized distortion performance provide flexible transmission information. Matching: Gain matching typically 0.25% full scale, offset matching better than 0.025%. Power: Complete CMOS Dual function operates from single supply. full-scale current reduced lower power operation, sleep mode provided power idle periods. On-Chip Voltage Reference: AD9763 includes 1.20 temperature-compensated bandgap voltage reference. Dual 10-Bit Inputs: AD9763 features flexible dualport interface allowing dual interleaved input data.
TxDAC+ registered trademark Analog Devices, Inc. *Patent pending.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
AD9763-SPECIFICATIONS
SPECIFICATIONS
Parameter RESOLUTION ACCURACY1 Integral Linearity Error (INL) Differential Linearity Error (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Gain Match Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD Digital Supply Current (IDVDD)4 Supply Current Sleep Mode (IAVDD) Power Dissipation4 IOUTFS Power Dissipation5 IOUTFS Power Supply Rejection Ratio6-AVDD Power Supply Rejection Ratio6-DVDD OPERATING RANGE
TMAX, AVDD DVDD IOUTFS unless otherwise noted.)
-0.5 -0.02 -1.0 1.14 1.20 1.26 0.15 +0.5 +0.02 20.0 1.25 Units Bits FSR/°C FSR/°C FSR/°C ppm/°C
0.25
1.25
12.0 +0.4 +0.025
-0.4 -0.025
FSR/V FSR/V
NOTES 1Measured OUTA driving virtual ground. 2Nominal full-scale current, OUTFS times IREF current. external buffer amplifier with input bias current <100 should used drive external load. 4Measured CLOCK MSPS fOUT MHz. 5Measured unbuffered voltage output with OUTFS LOAD IOUTA OUTB, CLOCK MSPS fOUT MHz. Power supply variation. Specifications subject change without notice.
REV.
DYNAMIC SPECIFICATIONS
put,
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% 90%)1 Output Fall Time (10% 90%)1 Output Noise (IOUTFS Output Noise (IOUTFS
AD9763
Units MSPS pV-s pA/Hz pA/Hz
TMAX, AVDD DVDD IOUTFS Differential Transformer Coupled OutDoubly Terminated, unless otherwise noted)
LINEARITY Spurious-Free Dynamic Range Nyquist fCLOCK MSPS; fOUT 1.00 dBFS Output +25°C dBFS Output dBFS Output dBFS Output fCLOCK MSPS; fOUT 1.00 fCLOCK MSPS; fOUT 2.51 fCLOCK MSPS; fOUT 5.02 fCLOCK MSPS; fOUT 14.02 fCLOCK MSPS; fOUT fCLOCK MSPS; fOUT fCLOCK MSPS; fOUT Spurious-Free Dynamic Range Within Window fCLOCK MSPS; fOUT 1.00 MHz; Span fCLOCK MSPS; fOUT 5.02 MHz; Span fCLOCK MSPS; fOUT 5.03 MHz; Span fCLOCK MSPS; fOUT 5.04 MHz; Span Total Harmonic Distortion fCLOCK MSPS; fOUT 1.00 +25°C fCLOCK MHz; fOUT 2.00 fCLOCK MHz; fOUT 2.00 fCLOCK MHz; fOUT 2.00 Multitone Power Ratio (Eight Tones Spacing) fCLOCK MSPS; fOUT 2.00 2.99 dBFS Output dBFS Output dBFS Output dBFS Output
NOTES 1Measured single-ended into load. Specifications subject change without notice.
REV.
AD9763-SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter DIGITAL INPUTS Logic Voltage DVDD Logic DVDD Logic Voltage DVDD Logic DVDD Logic Current Logic Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW)
TMAX, AVDD DVDD IOUTFS unless otherwise noted.)
Units
NOTES When DVDD Logic voltage Logic voltage DVDD increase depending CLOCK. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, OUTB COMP1 REFIO, FSADJ ACOM1 Junction Temperature Storage Temperature Lead Temperature sec)
With Respect ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM
-0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3
+6.5 +6.5 +0.3 +6.5 DVDD DVDD AVDD AVDD AVDD +0.3 +150 +150 +300
Units
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
ORDERING GUIDE
Model AD9763AST AD9763-EB
Temperature Range -40°C +85°C
Package Description
Package Option*
DATA
48-Lead LQFP ST-48 Evaluation Board
WRT1/IQWRT
CLK1/IQCLK
Thin Plastic Quad Flatpack.
THERMAL CHARACTERISTICS Thermal Resistance
IOUTA IOUTB
48-Lead LQFP 91°C/W
Figure Timing Diagram Dual Interleaved Modes
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9763 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9763
FUNCTION DESCRIPTIONS
1-10 11-14, 33-36 23-32
Name PORT1 DCOM1, DCOM2 DVDD1, DVDD2 WRT1/IQWRT CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL PORT2 SLEEP ACOM IOUTA2, IOUTB2 FSADJ2 ACOM1 REFIO FSADJ1 IOUTB1, OUTA1 AVDD MODE
Description Data Bits DB9-P1 DB0-P1. Connection. Digital Common. Digital Supply Voltage V-5.5 Input write signal PORT (IQWRT interleaving mode). Clock input DAC1 (IQCLK interleaving mode). Clock input DAC2 (IQRESET interleaving mode). Input write signal PORT (IQSEL interleaving mode). Data Bits DB9-P2 DB0-P2. Power-Down Control Input. Analog Common. "PORT differential current outputs. Full-scale current output adjust DAC2. Reference ground internal reference. Reference Input/Output. Full-scale current output adjust DAC1. "PORT differential current outputs. Analog Supply Voltage V-5.5 Mode select choose between dual interleaving operation.
CONFIGURATION
FSADJ1 FSADJ2 ACOM1 SLEEP IOUTA1 IOUTB1 IOUTB2 IOUTA2 REFIO ACOM MODE DB9-P1 (MSB) DB8-P1 DB7-P1 DB6-P1 DB5-P1 DB4-P1 DB3-P1 DB2-P1 DB1-P1 DB0-P1
AVDD
IDENTIFIER
DB0-P2 DB1-P2 DB2-P2 DB3-P2 DB4-P2 DB5-P2 DB6-P2 DB7-P2
AD9763
VIEW (Not Scale)
DVDD1
DCOM1
DCOM2
DVDD2
WRT1/IQWRT
WRT2/IQSEL
CLK1/IQCLK
REV.
CLK2/IQRESET
DB9-P2 (MSB)
DB8-P2
CONNECT
AD9763
DEFINITIONS SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity INL) Temperature Drift
Linearity error defined maximum deviation actual analog output from ideal output, determined straight line drawn from zero full scale.
Differential Nonlinearity DNL)
Temperature drift specified maximum change from ambient (+25°C) value value either TMIN MAX. offset gain drift, drift reported full-scale range (FSR) degree reference drift, drift reported degree
Power Supply Rejection
measure variation analog value, normalized full scale, associated with change digital input code.
Monotonicity
maximum change full-scale output supplies varied from nominal minimum maximum specified voltages.
Settling Time
converter monotonic output either increases remains constant digital input increases.
Offset Error
deviation output current from ideal zero called offset error. IOUTA, output expected when inputs IOUTB, output expected when inputs
Gain Error
time required output reach remain within specified error band about final value, measured from start output transition.
Glitch Impulse
Asymmetrical switching times give rise undesired output transients that quantified glitch impulse. specified area glitch pV-s.
Spurious-Free Dynamic Range
difference between actual ideal output span. actual span determined output when inputs minus output when inputs
Output Compliance Range
difference, between amplitude output signal peak spurious signal over specified bandwidth.
Total Harmonic Distortion
range allowable voltage output current-output DAC. Operation beyond maximum compliance limits cause either output stage saturation breakdown resulting nonlinear performance.
ratio first harmonic components value measured input signal. expressed percentage decibels (dB).
AVDD FSADJ1 RSET1 FSADJ2 RSET2 1.2V PMOS CURRENT SOURCE ARRAY REFIO
CLK1/IQCLK CONTROL LOGIC
CLK2/IQRESET
SLEEP ACOM IOUTA1
MINI CIRCUITS T1-1T
PMOS CURRENT SOURCE ARRAY
LATCH
SEGMENTED SWITCHES SWITCH IOUTB1 DAC1 IOUTA2 SEGMENTED SWITCHES SWITCH IOUTB2 DAC2 MODE DVDD
HP3589A SPECTRUM/ NETWORK ANALYZER
LATCH
AD9763
WRT1/ IQWRT
MULTIPLEXING LOGIC CHANNEL LATCH CHANNEL LATCH WRT2/ IQSEL
ACOM1
DCOM
DVDD DCOM *RETIMED CLOCK OUTPUT LECROY 9210 PULSE GENERATOR
DIGITAL DATA TEKTRONIX AWG-2021 w/OPTION *AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS FALLING EDGE DUTY CYCLE CLOCK
Figure Basic Characterization Test Setup AD9763, Testing Port Dual Port Mode
REV.
AD9763 Typical Characterization Curves
(AVDD DVDD +3.3 IOUTFS otherwise noted.) Doubly Terminated Load, Differential Output, SFDR Nyquist, unless
0dBFS
0dBFS
5MSPS
SFDR
SFDR
25MSPS
SFDR
-6dBFS
-6dBFS
-12dBFS
65MSPS 125MSPS fOUT
-12dBFS
0.00
0.50
1.00 1.50 fOUT
2.00
2.50
fOUT
Figure SFDR dBFS
Figure SFDR MSPS
Figure SFDR MSPS
0dBFS -6dBFS
0dBFS
IOUTFS 20mA fOUT IOUTFS
SFDR
SFDR
-12dBFS
-12dBFS
SFDR
-6dBFS
IOUTFS 10mA
fOUT
fOUT
Figure SFDR fOUT MSPS
Figure SFDR MSPS
Figure SFDR IOUTFS MSPS dBFS
910kHz/10MSPS
5MHz/25MSPS 1MHz/5MSPS
3.38/3.36MHz@25MSPS 0.965/1.035MHz@7MSPS 6.75/7.25MHz@65MSPS
2.27MHz/25MSPS SFDR
2MHz/10MSPS
SFDR
SFDR
13MHz/65MSPS 25MHz/125MSPS
5.91MHz/65MSPS 11.37MHz/125MSPS
16.9/18.1MHz@125MSPS
AOUT dBFS
AOUT dBFS
AOUT dBFS
Figure Single-Tone SFDR AOUT fOUT fCLOCK/11
Figure Single-Tone SFDR AOUT fOUT fCLOCK/5
Figure Dual-Tone SFDR AOUT fOUT fCLOCK/7
REV.
AD9763
0.25 0.20 0.15 IOUTFS 20mA SINAD IOUTFS 10mA LSBs 0.20 0.10 0.05 -0.05 -0.10 -0.15 IOUTFS -0.20 -0.25 CODE 1000 -0.05 -0.01 CODE 1000 LSBs 0.15 0.10 0.05 0.30 0.25
fCLOCK MSPS
Figure SINAD fCLOCK IOUTFS fOUT dBFS
Figure Typical
Figure Typical
fOUT 1MHz
1.26 1.24
fOUT 10MHz
SFDR
VREF Volts
fOUT 25MHz
1.22 1.20 1.18
fOUT 40MHz
1.16
fOUT 60MHz
TEMPERATURE
1.14 TEMPERATURE
FREQUENCY
Figure SFDR Temperature MSPS, dBFS
Figure Reference Voltage Drift Temperature
Figure Single-Tone SFDR fCLK MSPS
FREQUENCY FREQUENCY
Figure Dual-Tone SFDR fCLK MSPS
Figure Four-Tone SFDR fCLK MSPS
REV.
AD9763
AVDD RSET1 IREF1 FSADJ1 REFIO CLK1/IQCLK CONTROL LOGIC CLK2/IQRESET SLEEP ACOM IOUTA1 SEGMENTED SWITCHES SWITCH IOUTB1 DAC1 IOUTA2 SEGMENTED SWITCHES SWITCH IOUTB2 DAC2 MODE DVDD DCOM VOUT VOUT RL2B RL2A VDIFF VOUT VOUT VOUT VOUT RL1B RL1A
PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY
LATCH
RSET2 IREF
FSADJ2
LATCH
1.2V
AD9763
WRT1/ IQWRT
MULTIPLEXING LOGIC CHANNEL LATCH CHANNEL LATCH WRT2/ IQSEL
ACOM1
DIGITAL DATA INPUTS
Figure Simplified Block Diagram
FUNCTIONAL DESCRIPTION REFERENCE OPERATION
Figure shows simplified block diagram AD9763. AD9763 consists DACs, each with independent digital control logic full-scale output current control. Each contains PMOS current source array capable providing full-scale current (IOUTFS). array divided into equal currents that make five most significant bits (MSBs). next four bits, middle bits, consist equal current sources whose value 1/16th current source. remaining binary weighted fraction middle current sources. Implementing middle lower bits with current sources, instead R-2R ladder, enhances dynamic performance multitone amplitude signals helps maintain DAC's high output impedance (i.e., >100 these current sources switched other output nodes (i.e., IOUTA IOUTB) PMOS differential current switches. switches based architecture that drastically improves distortion performance. This switch architecture reduces various timing errors provides matching complementary drive signals inputs differential current switches. analog digital sections AD9763 have separate power supply inputs (i.e., AVDD DVDD) that operate independently over range. digital section, which capable operating MSPS clock rate, consists edge-triggered latches segment decoding logic circuitry. analog section includes PMOS current sources, associated differential switches, 1.20 bandgap voltage reference reference control amplifier. full-scale output current each regulated separate reference control amplifiers from external resistor, RSET, connected Full Scale Adjust (FSADJ) pin. external resistor, combination with both reference control amplifier voltage reference VREFIO, sets reference current REF, which replicated segmented current sources with proper scaling factor. full-scale current, IOUTFS, IREF.
AD9763 contains internal 1.20 bandgap reference. This easily overridden external reference with effect performance. REFIO serves either input output, depending whether internal external reference used. internal reference, simply decouple REFIO ACOM with capacitor. internal reference voltage will present REFIO. voltage REFIO used elsewhere circuit, external buffer amplifier with input bias current less than should used. example internal reference shown Figure
OPTIONAL EXTERNAL REFERENCE BUFFER
ACOM1 +1.2V
AD9763
REFERENCE SECTION
AVDD
ADDITIONAL EXTERNAL LOAD
REFIO FSADJ
CURRENT SOURCE ARRAY
IREF
Figure Internal Reference Configuration
external reference applied REFIO shown Figure external reference provide either fixed reference voltage enhance accuracy drift performance varying reference voltage gain control. Note that compensation capacitor required since internal reference overridden, relatively high input impedance REFIO minimizes loading external reference.
ACOM1 AVDD +1.2V EXTERNAL REFERENCE REFIO FSADJ
AD9763
REFERENCE SECTION
AVDD
CURRENT SOURCE ARRAY
IREF
Figure External Reference Configuration
REV.
AD9763
REFERENCE CONTROL AMPLIFIER
Both DACs AD9763 contain control amplifier that used regulate full-scale output current, IOUTFS. control amplifier configured converter shown Figure that current output, IREF, determined ratio VREFIO external resistor, RSET, stated Equation IREF copied segmented current sources with proper scale factor IOUTFS stated Equation control amplifier allows wide (10:1) adjustment span IOUTFS from setting IREF between 62.5 wide adjustment range IOUTFS provides several benefits. first relates directly power dissipation AD9763, which proportional IOUTFS (refer Power Dissipation section). second relates adjustment, which useful system gain control purposes. small signal bandwidth reference control amplifier approximately used frequency, small signal multiplying applications.
TRANSFER FUNCTION
These last equations highlight some advantages operating AD9763 differentially. First, differential operation will help cancel common-mode error sources associated with IOUTA OUTB such noise, distortion offsets. Second, differential code-dependent current subsequent voltage, VDIFF twice value single-ended voltage output (i.e., VOUTA VOUTB), thus providing twice signal power load. Note, gain drift temperature performance single-ended (VOUTA VOUTB) differential output (VDIFF) AD9763 enhanced selecting temperature tracking resistors RLOAD their ratiometric relationship shown Equation
ANALOG OUTPUTS
Both DACs AD9763 provide complementary current outputs, IOUTA IOUTB. IOUTA will provide near full-scale current output, IOUTFS, when bits high (i.e., CODE 1023) while IOUTB, complementary output, provides current. current output appearing IOUTA IOUTB function both input code IOUTFS expressed IOUTA (DAC CODE /1024) IOUTFS IOUTB (1023 CODE)/1024) IOUTFS
complementary current outputs each DAC, IOUTA IOUTB, configured single-ended differential operation. IOUTA IOUTB converted into complementary single-ended voltage outputs, VOUTA VOUTB, load resistor, RLOAD, described Transfer Function section Equations through differential voltage, VDIFF existing between VOUTA VOUTB also converted single-ended voltage transformer differential amplifier configuration. performance AD9763 optimum specified using differential transformer coupled output which voltage swing IOUTA IOUTB limited single-ended unipolar output desirable, IOUTA should selected. distortion noise performance AD9763 enhanced when configured differential operation. common-mode error sources both IOUTA OUTB significantly reduced common-mode rejection transformer differential amplifier. These common-mode error sources include even-order distortion products noise. enhancement distortion performance becomes more significant frequency content reconstructed waveform increases. This first order cancellation various dynamic common-mode distortion mechanisms, digital feedthrough noise. Performing differential-to-single-ended conversion transformer also provides ability deliver twice reconstructed signal power load (i.e., assuming source termination). Since output currents IOUTA IOUTB complementary, they become additive when processed differentially. properly selected transformer will allow AD9763 provide required power voltage levels different loads. output impedance IOUTA IOUTB determined equivalent parallel combination PMOS switches associated with current sources typically parallel with also slightly dependent output voltage (i.e., VOUTA VOUTB) nature PMOS device. result, maintaining IOUTA and/or IOUTB virtual ground configuration will result optimum linearity. Note INL/DNL specifications AD9763 measured with IOUTA maintained virtual ground amp. IOUTA IOUTB also have negative positive voltage compliance range that must adhered order achieve optimum performance. negative output compliance range -1.0 breakdown limits CMOS process. REV.
where CODE 1023 (i.e., Decimal Representation). previously mentioned, IOUTFS function reference current IREF, which nominally reference voltage, VREFIO external resistor RSET. expressed IOUTFS IREF where IREF VREFIO /RSET current outputs will typically drive resistive load directly transformer. coupling required, IOUTA IOUTB should directly connected matching resistive loads, RLOAD, that tied analog common, ACOM. Note, RLOAD represent equivalent load resistance seen IOUTA IOUTB would case doubly terminated cable. single-ended voltage output appearing IOUTA IOUTB nodes simply: VOUTA IOUTA LOAD VOUTB IOUTB RLOAD
Note full-scale value VOUTA VOUTB should exceed specified output compliance range maintain specified distortion linearity performance. VDIFF (IOUTA IOUTB) RLOAD Substituting values IOUTA IOUTB IREF; VDIFF expressed VDIFF CODE 1023)/1024} LOAD/R SET) VREFIO
-10-
AD9763
Operation beyond this maximum limit result breakdown output stage affect reliability AD9763. positive output compliance range slightly dependent full-scale output current, IOUTFS. degrades slightly from nominal 1.25 IOUTFS 1.00 IOUTFS optimum distortion performance single-ended differential output achieved when maximum full-scale signal IOUTA IOUTB does exceed Applications requiring AD9763's output (i.e., VOUTA and/or VOUTB) extend output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect AD9763's linearity performance subsequently degrade distortion performance.
DIGITAL INPUTS
input latches both DACs have stages. purposes, will refer input stage each latch Stage output stage these same latches Stage dual port mode, these controlled WRT1 WRT2. rising edge WRT1 WRT2, data will written into first stage respective input latch. next falling edge WRT1 WRT2, data transferred from first second stage, appears inputs latches. latches controlled CLK1 CLK2. Data present input latches written latch rising edge CLK1 CLK2. important remember that input data appear output AD9763, correct series clock control edges must applied input latches. example, convert digital data inputs PORT analog information output DAC1, rising edge must applied WRT1, then falling edge WRT1, then rising edge CLK1. same applies PORT with respective control inputs. Timing specifications dual port mode given Figures
DATA
AD9763's digital inputs consist independent channels. dual port mode, each dedicated 10-bit data port, line line. interleaved timing mode, function digital control pins changes described Interleaved Mode Timing section. 10-bit parallel data inputs follow straight binary coding where Most Significant (MSB) Least Significant (LSB). IOUTA produces full-scale output current when data bits Logic IOUTB produces complementary output with full-scale current split between outputs function input code. digital interface implemented using edge-triggered master slave latch. outputs updated following either rising edge, every other rising edge clock, depending whether dual interleaved mode being used. outputs designed support clock rate high MSPS. clock operated duty cycle that meets specified latch pulsewidth. setup hold times also varied within clock cycle long specified minimum times met, although location these transition edges affect digital feedthrough distortion performance. Best performance typically achieved when input data transitions falling edge duty cycle clock.
TIMING
WRT1/WRT2
CLK1/CLK2
IOUTA IOUTB
Figure Dual Mode Timing
DATAIN
AD9763 operate timing modes, dual interleaved, which described below. block diagram Figure represents latch architecture interleaved timing mode.
DUAL PORT MODE TIMING
DATAOUT
When mode Logic "1," AD9763 operates dual port mode. AD9763 functions distinct DACs. Aside from single bandgap reference shared both, each completely independent digital input control lines, well separate control line full-scale adjust. AD9763 features double buffered digital signal path. Data first enters chip through input latches. Through series control clock edges, this data then transferred latch each signal path. analog output function digital data stored latch, changes analog output will occur short propagation time after data written latch.
Figure Dual Mode Timing
REV.
-11-
AD9763
INTERLEAVED MODE TIMING
When mode grounded, AD9763 operates interleaved mode. CLK1 defined IQCLK, WRT1, WRT2 CLK2 pins become IQWRT, IQSEL IQRESET, respectively. Data PORT written DAC1 Stage DAC2 Stage rising edge IQWRT. control this dependent level IQSEL pin. rising edge IQWRT with IQSEL high will write input data PORT PORT input register, Stage while rising edge with IQSEL will write data PORT PORT input register, Stage falling edge IQWRT, data present Stage either input latch will written respective Stage will therefore present inputs latches. latches controlled IQCLK IQRESET. When IQRESET high, IQCLK disabled. When IQRESET goes low, following rising edge IQCLK will update both output latches with respective data from their inputs. interleaved mode, IQCLK divided two, that following this first rising edge, output registers will only updated every other rising edge. this way, IQRESET used synchronize routing data DACs.
IQSEL IQWRT PORT INPUT LATCH STAGE STAGE INTERLEAVED DATA PORT LOGIC PORT INPUT LATCH STAGE STAGE IQCLK IQRESET CONTROL LOGIC DAC1 LATCH
DATA
IQWRT
IQCLK
IOUTA IOUTB
Figure Interleaved Mode Timing
INTERLEAVED DATA
IQSEL
IQWRT
IQCLK
IQRESET OUTPUT PORT OUTPUT PORT DEINTERLEAVED DATA
DAC1 DAC2 LATCH
Figure Interleaved Mode Timing
DAC2
Figure Latch Structure Interleaved Mode
Timing specifications interleaved mode given Figures digital inputs CMOS-compatible with logic thresholds, VTHRESHOLD, approximately half digital positive supply (DVDD) VTHRESHOLD DVDD/2 20%) internal digital circuitry AD9763 capable operating over digital supply range result, digital inputs also accommodate levels when DVDD accommodate maximum high level voltage drivers VOH(MAX). DVDD will typically ensure proper compatibility with most logic families. Figure shows equivalent digital input circuit data clock inputs. sleep mode input similar with exception that contains active pull-down circuit, thus ensuring that AD9763 remains enabled this input left disconnected.
Since AD9763 capable being clocked MSPS, quality clock data input signals important achieving optimum performance. Operating AD9763 with reduced logic swings corresponding digital supply (DVDD) will result lowest data feedthrough on-chip digital noise. drivers digital data interface circuitry should specified meet minimum setup hold times AD9763 well required min/max input logic level thresholds. Digital signal paths should kept short lengths matched avoid propagation delay mismatch. insertion value resistor network (i.e., between AD9763 digital inputs driver outputs helpful reducing overshooting ringing digital inputs that contribute digital feedthrough. longer board traces high data update rates, stripline techniques with proper impedance termination resistors should considered maintain "clean" digital inputs. external clock driver circuitry should provide AD9763 with jitter clock input meeting min/max logic levels while providing fast edges. Fast clock edges will help minimize jitter that will manifest itself phase noise reconstructed waveform. Thus, clock input should driven fastest logic family suitable application. Note that clock input could also driven sine wave, which centered around digital threshold (i.e., DVDD/2) meets min/max logic threshold. This will typically result slight degradation phase noise, which becomes more noticeable higher sampling rates output frequencies.
-12-
REV.
AD9763
Also, higher sampling rates, tolerance digital logic threshold should considered since will affect effective clock duty cycle and, subsequently, into required data setup hold times.
DVDD
update rate fCLOCK, reconstructed digital input waveform. power dissipation directly proportional analog supply current, IAVDD, digital supply current, IDVDD. IAVDD directly proportional IOUTFS shown Figure insensitive fCLOCK.
DIGITAL INPUT
Figure Equivalent Digital Input
INPUT CLOCK DATA TIMING RELATIONSHIP
IAVDD
dependent relationship between position clock edges point time which input data changes. AD9763 rising edge triggered, exhibits sensitivity when data transition close this edge. general, goal when applying AD9763 make data transition close falling clock edge. This becomes more important sample rate increases. Figure shows relationship clock placement with different sample rates. Note that lower sample rates, much more tolerance allowed clock placement, while much more care must taken higher rates.
IOUTFS
Figure IAVDD IOUTFS
Conversely, IDVDD dependent both digital input waveform, fCLOCK, digital supply DVDD. Figures show IDVDD function full-scale sine wave output ratios OUT/fCLOCK) various update rates with DVDD DVDD respectively. Note IDVDD reduced more than factor when DVDD reduced from
125MSPS
IDVDD
100MSPS
65MSPS
25MSPS 5MSPS
0.10
TIME DATA CHANGE RELATIVE RISING CLOCK EDGE
Figure Clock Placement fCLK MSPS
SLEEP MODE OPERATION
0.20 0.30 RATIO fOUT/fCLK
0.40
0.50
Figure IDVDD Ratio DVDD
100MSPS
IDVDD
AD9763 power-down function that turns output current reduces supply current less than over specified supply range temperature range. This mode activated applying Logic Level SLEEP pin. SLEEP logic threshold equal AVDD. This digital input also contains active pull-down circuit that ensures AD9763 remains enabled this input left disconnected. AD9763 takes less than power down approximately power back
POWER DISSIPATION
125MSPS
65MSPS 25MSPS 5MSPS
power dissipation, AD9763 dependent several factors that include: power supply voltages (AVDD DVDD), full-scale current output IOUTFS, REV. -13-
0.10
0.20 0.30 RATIO fOUT/fCLK
0.40
0.50
Figure IDVDD Ratio DVDD
AD9763
CONTROL AMPLIFIER COMPENSATION DIFFERENTIAL COUPLING USING TRANSFORMER
most applications single RSET resistor used full-scale output current each shown Figure However, output frequencies below recommended that compensation network added each FSADJ parallel with RSET1 SET2 shown Figure Recommended values network Components with tolerances these nominal values used.
ACOM1
AD9763
+1.2V REFIO FSADJ1 REFERENCE SECTION
AVDD
transformer used perform differential-tosingle-ended signal conversion shown Figure differentially coupled transformer output provides optimum distortion performance output signals whose spectral content lies within transformer's passband. transformer such Mini-Circuits T1-1T provides excellent rejection common-mode distortion (i.e., even-order harmonics) noise over wide frequency range. also provides electrical isolation ability deliver twice power load. Transformers with different impedance ratios also used impedance matching purposes. Note that transformer provides coupling only.
AD9763
IOUTA MINI-CIRCUITS T1-1T
CURRENT SOURCE ARRAY
RLOAD IOUTB FSADJ2 CURRENT SOURCE ARRAY OPTIONAL RDIFF
Figure Differential Output Using Transformer
Figure Network AD9763
APPLYING AD9763 Output Configurations
following sections illustrate some typical output configurations AD9763. Unless otherwise noted, assumed that IOUTFS nominal applications requiring optimum dynamic performance, differential output configuration suggested. differential output configuration consist either transformer differential configuration. transformer configuration provides optimum high frequency performance recommended application allowing coupling. differential configuration suitable applications requiring coupling, bipolar output, signal gain and/or level-shifting, within bandwidth chosen amp. single-ended output suitable applications requiring unipolar voltage output. positive unipolar output voltage will result IOUTA and/or IOUTB connected appropriatelysized load resistor, RLOAD, referred ACOM. This configuration more suitable single-supply system requiring coupled, ground referred output voltage. Alternatively, amplifier could configured converter, thus converting IOUTA IOUTB into negative unipolar voltage. This configuration provides best linearity since IOUTA IOUTB maintained virtual ground. Note that IOUTA provides slightly better performance than IOUTB.
center primary side transformer must connected ACOM provide necessary current path both IOUTA IOUTB. complementary voltages appearing IOUTA OUTB (i.e., VOUTA VOUTB) swing symmetrically around ACOM should maintained with specified output compliance range AD9763. differential resistor, RDIFF, inserted applications where output transformer connected load, RLOAD, passive reconstruction filter cable. RDIFF determined transformer's impedance ratio provides proper source termination that results VSWR. Note that approximately half signal power will dissipated across RDIFF.
DIFFERENTIAL COUPLING USING
also used perform differential-to-singleended conversion shown Figure AD9763 configured with equal load resistors, RLOAD differential voltage developed across IOUTA IOUTB converted single-ended signal differential configuration. optional capacitor installed across IOUTA IOUTB, forming real pole low-pass filter. addition this capacitor also enhances amps distortion performance preventing DACs high slewing output from overloading amp's input. common-mode rejection this configuration typically determined resistor matching. this circuit, differential circuit using AD8047 configured provide some additional signal gain. must operate from dual supply since output approximately high speed amplifier capable preserving differential performance AD9763, while meeting other system level objectives (i.e., cost, power), should selected. amp's differential gain, gain setting resistor values, full-scale output swing capabilities should considered when optimizing this circuit.
-14-
REV.
AD9763
AD9763
IOUTA
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
IOUTB COPT
AD8047
Figure Differential Coupling Using
differential circuit shown Figure provides necessary level-shifting required single supply system. this case AVDD, which positive analog supply both AD9763 amp, also used level-shift differential output AD9763 midsupply (i.e., AVDD/2). AD8055 suitable this application.
Figure shows buffered single-ended output configuration which performs conversion AD9763 output current. maintains IOUTA IOUTB) virtual ground, thus minimizing nonlinear output impedance effect DAC's performance discussed Analog Output section. Although this single-ended configuration typically provides best linearity performance, distortion performance higher update rates limited U1's slewing capabilities. provides negative unipolar output voltage full-scale output voltage simply product OUTFS. full-scale output should within U1's voltage output swing capabilities scaling IOUTFS and/or improvement distortion performance result with reduced IOUTFS since signal current will required sink will subsequently reduced.
COPT
AD9763
IOUTA
IOUTB COPT
AD8055
AD9763
AVDD IOUTA
IOUTFS 10mA
IOUTB VOUT IOUTFS
Figure Single Supply Differential Coupled Circuit Figure Unipolar Buffered Voltage Output
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure shows AD9763 configured provide unipolar output range approximately +0.5 doubly terminated cable since nominal full-scale current, IOUTFS, flows through equivalent RLOAD this case, RLOAD represents equivalent load resistance seen IOUTA IOUTB. unused output (IOUTA IOUTB) connected ACOM directly matching RLOAD. Different values IOUTFS RLOAD selected long positive compliance range adhered additional consideration this mode integral nonlinearity (INL) discussed Analog Output section this data sheet. optimum performance, single-ended, buffered voltage output configuration suggested.
AD9763
IOUTA IOUTB IOUTFS 20mA
POWER GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Many applications seek high speed high performance under less than ideal operating conditions. these application circuits, implementation construction printed circuit board important circuit design. Proper techniques must used device selection, placement routing, well power supply bypassing grounding ensure optimum performance. Figures illustrate recommended printed circuit board ground, power signal plane layouts which implemented AD9763 evaluation board. factor that measurably affect system performance ability output reject variations noise superimposed analog digital power distribution. This referred Power Supply Rejection Ratio. variations power supply, resulting performance directly corresponds gain error associated with DAC's full-scale current, IOUTFS. noise supplies common applications where power distribution generated switching power supply. Typically, switching power supply noise will occur over spectrum from tens several MHz. PSRR frequency AD9763 AVDD supply over this frequency range shown Figure
VOUTA +0.5V
Figure Unbuffered Voltage Output
REV.
-15-
AD9763
TTL/CMOS LOGIC CIRCUITS TANTALUM POWER SUPPLY FERRITE BEADS ELECTROLYTIC CERAMIC AVDD 10-22 ACOM
PSRR
Figure Differential Filter Single Applications
APPLICATIONS Using AD9763 Quadrature Amplitude Modulation
0.20
0.30
0.40
0.50 0.60 0.70 0.80 FREQUENCY
0.90
1.00
1.10
Figure Power Supply Rejection Ratio AD9763
Note that units Figure given units (amps out/ volts in). Noise analog power supply effect modulating internal switches, therefore output current. voltage noise AVDD, therefore, will added nonlinear manner desired IOUT. relative different size these switches, PSRR very code-dependent. This produce mixing effect which modulate frequency power supply noise higher frequencies. Worst case PSRR either differential outputs will occur when full-scale current directed towards that output. result, PSRR measurement Figure represents worst case condition which digital inputs remain static full-scale output current directed output being measured. example serves illustrate effect supply noise analog supply. Suppose switching regulator with switching frequency produces noise and, simplicity sake (i.e., ignore harmonics), this noise concentrated kHz. calculate much this undesired noise will appear current noise superimposed DAC's full-scale current, IOUTFS, must determine PSRR using Figure kHz. calculate PSRR given RLOAD, such that units PSRR converted from V/V, adjust curve Figure scaling factor (RLOAD instance, RLOAD PSRR reduced (i.e., PSRR kHz, which Figure becomes VOUT/VIN). Proper grounding decoupling should primary objective high speed, high resolution system. AD9763 features separate analog digital supply ground pins optimize management analog digital ground currents system. general, AVDD, analog supply, should decoupled ACOM, analog common, close chip physically possible. Similarly, DVDD, digital supply, should decoupled DCOM close chip physically possible. those applications that require single supply both analog digital supplies, clean analog supply generated using circuit shown Figure circuit consists differential filter with separate power supply return lines. Lower noise attained using type electrolytic tantalum capacitors.
most widely used digital modulation schemes digital communications systems. This modulation technique found well spread spectrum (i.e., CDMA) based systems. signal carrier frequency that modulated both amplitude (i.e., modulation) phase (i.e., modulation). generated independently modulating carriers identical frequency with phase difference. This results in-phase carrier component quadrature carrier component phase shift with respect component. components then summed provide signal specified carrier frequency. common traditional implementation modulator shown Figure modulation performed analog domain which DACs used generate baseband components. Each component then typically applied Nyquist filter before being applied quadrature mixer. matching Nyquist filters shape limit each component's spectral envelope while minimizing intersymbol interference. typically updated symbol rate possibly multiple interpolating filter precedes DAC. interpolating filter typically eases implementation complexity analog filter, which significant contributor mismatches gain phase between baseband channels. quadrature mixer modulates components with in-phase quadrature carrier frequency then sums outputs provide signal.
ASIC NYQUIST FILTERS QUADRATURE MODULATOR CARRIER FREQUENCY
MIXER
Figure Typical Analog Architecture
this implementation, much more difficult maintain proper gain phase matching between channels. circuit implementation shown Figure helps improve upon matching between channels, well showing path upconversion using AD8346 quadrature modulator. AD9763 provides both DACs well common reference that will improve gain matching
-16-
REV.
AD9763
DVDD CLK1 RSET1 SLEEP AVDD CFILTER BBIN BBIP VPBF 1.82V
FSADJ1 LATCHES
IOUTA IOUTB
DATA INPUT WRT1
INPUT LATCHES
VOUT
DAC")
AD9763
WRT2 DATA INPUT RSET2 1.9k FSADJ2 RCAL REFIO ACOM1 CLK2 ACOM DCOM INPUT LATCHES
DAC")
LATCHES QOUTA QOUTB CFILTER
LOIPP BBQP PHASE SPLITTER LOIPN
BBQN 500mV WITH 1.2V
AD8346
NOTE:
RESISTOR NETWORK OHMTEK ORN5000D RESISTOR NETWORK TOMC1603-100D
Figure Baseband Implementation Using AD9763 AD8346
stability. RCAL used compensate mismatch gain between channels. mismatch attributed mismatch between RSET1 RSET2, effective load resistance each channel, and/or voltage offset control amplifier each DAC. differential voltage outputs both DACs AD9763 into respective differential inputs AD8346 matching networks. digital data into AD9763 different ways. dual port mode, digital information drives input port, while digital information drives other input port. interpolation filter precedes DAC, symbol rate will rate which system clock drives pins AD9763. interleaved mode, digital input stream Port contains information alternating digital words. Using IQSEL IQRESET, AD9763 synchronized data stream. internal timing AD9763 routes selected data correct output. interleaved mode, interpolation filter precedes AD9763, symbol rate will half that system clock driving digital data stream IQWRT IQCLK pins AD9763.
CDMA
Distortion transmit path lead power being transmitted defined band. ratio power transmitted in-band out-of-band often referred Adjacent Channel Power (ACP). This regulatory issue possibility interference with other signals being transmitted air. Regulatory bodies define spectral mask outside transmit band, must fall under this mask. distortion transmit path causes above spectral mask, then filtering, different component selection, needed meet mask requirements. Figure shows AD9763 reconstructing baseband, CDMA test vector with bandwidth MHz, centered 15.625 MHz, being sampled MHz. given test vector measured
Carrier Division Multiple Access, CDMA, transmit/ receive scheme where signal transmit path modulated with pseudorandom digital code (sometimes referred spreading code). effect this spread transmitted signal across wide spectrum. Similar waveform, CDMA waveform containing multiple subscribers characterized having high peak average ratio (i.e., crest factor), thus demanding highly linear components transmit signal path. bandwidth spectrum defined CDMA standard being used, operation implemented using spreading code with particular characteristics.
-100 -110 -120
FREQUENCY
Figure CDMA Signal, Sampled MSPS, Adjacent Channel Power
REV.
-17-
AD9763
DVDD CLK1 RSET1 FSADJ1 AVDD
LATCHES
IOUTA IOUTB
IIPP IIPN
AD6122
DATA INPUT WRT1
INPUT LATCHES
DAC")
AD9763
WRT2 DATA INPUT RSET2 1.9k FSADJ2 RCAL REFIO SLEEP CLK2 ACOM DCOM INPUT LATCHES
DAC")
LATCHES QOUTA QOUTB
LOIPP LOIPN IIQP IIQN
PHASE SPLITTER
MODOPP MODOPN TEMPERATURE COMPENSATION
REFIN GAIN CONTROL VGAIN
GAIN CONTROL SCALE FACTOR
TXOPP TXOPN
Figure CDMA Transmit Application Using AD9763 AD6122
Figure shows example AD9763 used W-CDMA transmitter application using AD6122 CDMA subsystem. AD6122 functions, such external gain control distortion characteristics, needed superior Adjacent Channel Power (ACP) requirements W-CDMA.
EVALUATION BOARD General Description
AD9763-EB evaluation board AD9763 10-bit dual converter. Careful attention layout circuit design, combined with prototyping area, allow user easily effectively evaluate AD9763 application where high resolution, high speed conversion required.
This board allows user flexibility operate AD9763 various configurations. Possible output configurations include transformer coupled, resistor terminated, single differential outputs. digital inputs used dual port interleaved mode, designed driven from various word generators, with on-board option resistor network proper load termination. When operating AD9763, best performance obtained when running Digital Supply (DVDD) Analog Supply (AVDD)
-18-
REV.
AD9763
PREPARING FUTURE COMPATIBILITY
AD9763 allows gain each channel independently connecting RSET resistor FSADJ1 another RSET resistor FSADJ2. flexibility reduce system cost, revision will introduced include mode where single RSET resistor used gain both channels simultaneously. Redefining ACOM1 (Pin control pin, named GAINCTRL, will support this additional mode. When GAINCTRL (i.e., connected AGND), independent channel gain control mode using resistors enabled. this mode, individual RSET resistors should connected FSADJ1 FSADJ2. When GAINCTRL high (i.e., connected AVDD), master/slave channel gain control mode using resistor enabled. this mode, single RSET resistor connected FSADJ1 resistor FSADJ2 removed.
REV.
-19-
AD9763
POWER DECOUPLING INPUT CLOCKS
DVDDIN BAN-JACK BAN-JACK TP10 BEAD DVDD TP37
AVDDIN
TP11 BEAD AVDD TP40
BAN-JACK TP38 TP39 BAN-JACK DCLKIN1
TP41
TP42
TP43
DGND
TP44
AGND
DCLKIN2
CLOCK DIVIDER
TP29 WRT1IN IQWRT
DGND;3,4,5
JP16
DVDD
DVDD
TP30 CLK1IN IQCLK
DGND;3,4,5
0.01
TP31
DGND;3,4,5
74VHC74
CLK2IN RESET TP32 WRT2IN IQSEL
DGND;3,4,5
DGND;7 DVDD;14
74VHC74
DGND;7 DVDD;14
DVDD
WRT1 CLK1 CLK2 WRT2
TP33 SLEEP
DGND;3,4,5
SLEEP
Figure Power Decoupling Clocks AD9763 Evaluation Board
-20-
REV.
AD9763
DIGITAL INPUT SIGNAL CONDITIONING
DCOM
DCOM
RP13
DCOM
RP11
DCOM
RP5,
DVDD RP5,
DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14
RP5,
RP5,
RP5,
RP5,
RP5,
RP5,
RP6,
RP6,
RP6,
RP6,
RP6,
RP6,
RP6,
DCLKIN1
DCOM
DCOM
RP14
DCOM
RP12
DCOM
RP7,
DVDD RP7,
DVDD DUTP23 DUTP24 DUTP25 DUTP26 DUTP27 DUTP28 DUTP29 DUTP30 DUTP31 DUTP32 DUTP33 DUTP34 DUTP35 DUTP36
RP7,
RP7,
RP7,
RP7,
RP7,
RP7,
RP8,
RP8,
RP8,
RP8,
RP8,
RP8,
RP8,
DCLKIN2 SPARES RP5,
RP8,
Figure Digital Input Signal Conditioning
REV.
-21-
AD9763
ANALOG OUTPUT SIGNAL CONDITIONING
DVDD
TP34
AGND;3,4,5 AGND;3,4,5
AGND;3,4,5
OUT1
0.001
0.01
AVDD
DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14
DB13P1 (MSB) DB12P1 DB11P1 DB10P1 DB9P1 DB8P1 DB7P1 DB6P1 DB5P1 DB4P1 DB3P1 DB2P1 DB1P1 DB0P1 DCOM1 DVDD1 WRT1 CLK1 CLK2 WRT2 DCOM2 DVDD2 DB13P2 (MSB) DB12P2
10pF
MODE AVDD IOUTB1 IOUTA1 FSADJ1 REFIO ACOM FSADJ2 IOUTB2
10pF
TP45
1.92k
REFIO TP36
TP46
1.92k
AD9763
IOUTA2 ACOM SLEEP DB0P2 DB1P2 DB2P2 DB3P2 DB4P2 DB5P2 DB6P2 DB7P2 DB8P2 DB9P2 DB10P2 DB11P2 SLEEP DUTP36 DUTP35 DUTP34 DUTP33 DUTP32 DUTP31 DUTP30 DUTP29 DUTP28 DUTP27 DUTP26 DUTP25 AVDD
10pF
10pF
AGND;3,4,5 AGND;3,4,5
WRT1 CLK1 CLK2 WRT2
TP35
AGND;3,4,5
OUT2
DUTP23 DUTP24
0.001
0.01
Figure AD9763 Output Signal Conditioning
-22-
REV.
AD9763
Figure Assembly, Side
REV.
-23-
AD9763
Figure Assembly, Bottom Side
-24-
REV.
AD9763
Figure Layer Side
REV.
-25-
AD9763
Figure Layer Ground Plane
-26-
REV.
AD9763
Figure Layer Power Plane
REV.
-27-
AD9763
Figure Layer Bottom Side
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Lead Thin Plastic Quad Flatpack (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
VIEW
(PINS DOWN)
0.276 (7.00)
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0.019 (0.5)
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-28-
REV.
PRINTED U.S.A.
0.354 (9.00)
C3582-0-7/99
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