ENCODE ENCODE 12-Bit, MSPS/105 MSPS Converter AD9432 FUNCTIO

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ENCODE ENCODE 12-Bit, MSPS/105 MSPS Converter AD9432 FUNCTIO

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FEATURES On-Chip Reference Track/Hold On-Chip Input Buffer Typical Power Dissipation MSPS Analog Bandwidth MSPS SFDR MSPS Differential Analog Input Range Single +5.0 Supply Operation +3.3 CMOS/TTL Outputs Twos Complement Output Format APPLICATIONS Communications Basestations `Zero-IF' Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) HDTV Broadcast Cameras Film Scanners GENERAL INTRODUCTION
ENCODE ENCODE
12-Bit, MSPS/105 MSPS Converter AD9432
FUNCTIONAL BLOCK DIAGRAM
PIPELINE OUTPUT STAGING D11-D0
TIMING
AD9432
VREFOUT VREFIN
AD9432 12-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuit optimized high speed conversion ease use. product operates MSPS conversion rate with outstanding dynamic performance over full operating range. requires only single power supply encode clock full-performance operation. external reference driver components required many applications. digital outputs TTL/CMOS compatible separate output power supply supports interfacing with logic. encode input supports either differential single-ended TTL/CMOS compatible.
Fabricated advanced BiCMOS process, AD9432 available 52-lead plastic quad flatpack package (LQFP) specified over industrial temperature range (-40°C +85°C).
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
AD9432-SPECIFICATIONS otherwise noted)
Parameter RESOLUTION ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (AIN-AIN) Common-Mode Voltage Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power ANALOG REFERENCE Output Voltage Tempco Input Bias Current SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth (tEL Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Output Rise Time (tR)2 Output Fall Time (tF) Out-of-Range Recovery Time Transient Response Time DIGITAL INPUTS Encode Input Common Mode Differential Input (ENC-ENC) Single-Ended Logic Voltage Logic Voltage Input Resistance Input Capacitance DIGITAL OUTPUTS Logic Voltage (VDD +3.3 Logic Voltage (VDD +3.3 Output Coding +25°C Full +25°C Full Full +25°C Full Full Full Full Full +25°C +25°C Full Full Full Full Full +25°C +25°C +25°C +25°C Full Full Full Full +25°C +25°C Full Full Full Full Full +25°C Full Full Temp Test Level
(VDD external reference; differential encode input, unless
AD9432BST-80 -0.75 0.25 -1.0 -1.0 -1.5 Guaranteed -5.0 +0.75 +1.0 +1.0 +1.5 +5.0 -0.75 -1.0 -1.0 -1.5 AD9432BST-105 0.25 Guaranteed -5.0 +0.75 +1.0 +1.0 +1.5 +5.0
Units Bits ppm/°C ppm/°C MSPS MSPS
0.25
0.25
0.05 0.05 Twos Complement 1000
0.05 0.05 Twos Complement 1100
POWER SUPPLY Power Dissipation3 Full Power Supply Rejection Ratio (PSRR) +25°C
mV/V
REV.
AD9432
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3 Signal-to-Noise Ratio (SINAD) (With Harmonics) 10.3 Effective Number Bits Second Third Harmonic Distortion Worst Harmonic Spur (Excluding Second Third) Two-Tone Intermod Distortion (IMD) fIN1 23.9 MHz; fIN2 30.3 fIN1 70.3 MHz; fIN2 71.3
Temp
Test Level
AD9432BST-80
AD9432BST-105
Units
+25°C +25°C +25°C +25°C
65.5
67.5 67.2 67.0 66.1
65.5
67.5 67.2 67.0 66.1
+25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C
64.5
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
Bits Bits Bits Bits
+25°C +25°C +25°C +25°C +25°C +25°C
NOTES Gain error gain temperature coefficients based only (with fixed external reference). measured from transition points ENCODE input 50%/50% levels digital outputs swing. digital output load during test exceed load current Rise fall times measured from 90%. Power dissipation measured with encode rated speed analog input. SNR/harmonics based analog input voltage -0.5 dBFS referenced full-scale input range. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
Analog Inputs -0.5 Digital Inputs -0.5 VREF -0.5 Digital Output Current Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Maximum Junction Temperature +175°C Maximum Case Temperature +150°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
ORDERING GUIDE Temperature Ranges Package Descriptions Package Option
Model AD9432BST -80, -105
-40°C +85°C 52-Lead Plastic Quad ST-52 Flatpack (LQFP) AD9432/PCB +25°C Evaluation Board
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9432 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9432
EXPLANATION TEST LEVELS Test Level
Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested +25°C; guaranteed design characterization testing industrial temperature range.
100% production tested. 100% production tested +25°C sample tested specified temperatures.
Sample tested only.
CONFIGURATION
VREFOUT VREFIN
ENCODE ENCODE DGND
IDENTIFIER
AD9432
VIEW (Not Scale)
DGND (LSB)
(MSB)
DGND
DGND
FUNCTION DESCRIPTIONS Number AD9432BST 15-20, 25-30 40-42
Name ENCODE ENCODE D11-6, D5-D0 DGND VREFIN VREFOUT
Function Analog Ground. Analog Supply Encode Clock ADC-Complementary. Encode Clock ADC-True (ADC samples rising edge ENCODE). Range Output. Digital Output. Digital Output Ground. Digital Output Power Supply (2.7 Connect. Reference Input (2.5 typical). Internal Reference Output (2.5 typical); Bypass with VCC. Analog Input-True. Analog Input-Complementary.
REV.
AD9432
DEFINITION SPECIFICATIONS Power Supply Rejection Ratio
Analog Bandwidth (Small Signal) analog input frequency which spectral power fundamental frequency determined analysis) reduced Aperture Delay delay between differential crossing ENCODE ENCODE instant which analog input sampled.
Aperture Uncertainty (Jitter)
ratio change input offset voltage change power supply voltage.
Signal-to-Noise Plus Distortion (SINAD)
ratio signal amplitude (set below full scale) value other spectral components, including harmonics excluding
Signal-to-Noise Ratio (SNR)
sample-to-sample variation aperture delay.
Differential Nonlinearity
ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics
Spurious-Free Dynamic Range (SFDR)
deviation code from ideal step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high minimum amount time that ENCODE pulse should left Logic state achieve rated performance; pulsewidth minimum time ENCODE pulse should left state. given clock rate, these specs define acceptable Encode duty cycle.
Integral Nonlinearity
ratio signal amplitude value peak spurious spectral component. peak spurious component harmonic. reported (i.e., degrades signal level lowered), dBFS (always related back converter full scale).
Two-Tone Intermodulation Distortion Rejection
deviation transfer function from reference line measured fractions using "best straight line" determined least square curve fit.
Minimum Conversion Rate
ratio value either input tone value worst third order intermodulation product; reported dBc.
Two-Tone SFDR
encode rate which lowest analog signal frequency drops more than below guaranteed limit.
Maximum Conversion Rate
ratio value either input tone value peak spurious component. peak spurious component product. reported (i.e., degrades signal levels lowered), dBFS (always related back converter full scale).
Worst Harmonic
encode rate which parametric testing performed.
Output Propagation Delay
delay between differential crossing ENCODE ENCODE time when output data bits within valid logic levels.
ratio signal amplitude value worst harmonic component, reported dBc.
REV.
AD9432
SAMPLE SAMPLE SAMPLE N+10 SAMPLE N+11
ENCODE ENCODE
SAMPLE
SAMPLE
D11-D0 DATA N-11 DATA N-10 DATA DATA
DATA
Figure Timing Diagram
VREFIN
DIGITAL OUTPUT
DIGITAL OUTPUT
Figure Equivalent Voltage Reference Input Circuit
Figure Equivalent Digital Output Circuit
VREFOUT
VREF OUTPUT ANALOG INPUT
Figure Equivalent Voltage Reference Output Circuit
Figure Equivalent Analog Input Circuit
ENCODE
ENCODE
Figure Equivalent Encode Input Circuit
REV.
Typical Performance Characteristics- AD9432
10.3MHz SFDR (-6.0dBFS) ENCODE 105MSPS
SINAD ENCODE MSPS
(-0.5dBFS) (-3.0dBFS)
ANALOG INPUT FREQUENCY
Figure SNR/SINAD/SFDR 10.3
Figure Harmonics fIN: MSPS
10.3MHz
ENCODE 105MSPS WORST OTHER (-0.5dBFS)
WORST OTHER (-6.0dBFS) WORST OTHER (-3.0dBFS)
-100 ENCODE MSPS
ANALOG INPUT FREQUENCY
Figure Harmonics 10.3
Figure Worst Case Spur (Other than Second Third) fIN: MSPS
ENCODE 105MSPS
ENCODE 105MSPS 10.3MHz (-0.53dBFS) 67.32dB SINAD 67.07dB SFDR -80.32dBc
SINAD (-3.0dBFS) SINAD (-6.0dBFS) SINAD (-0.5dBFS)
-100 -110
ANALOG INPUT FREQUENCY
-120 SAMPLES
Figure SINAD fIN: MSPS
Figure Spectrum: MSPS, 10.3
REV.
AD9432
-100 -110 -120 SAMPLES ENCODE 105MSPS 27.0MHz (-0.52dBFS) 67.3dB SINAD 67.0dB SFDR -83.1dBc -100 -110 -120 SAMPLES AIN1 29.3MHz (-7dBFS) AIN2 30.3MHz (-7dBFS) ENCODE 105MSPS
Figure Spectrum: MSPS,
Figure Two-Tone Spectrum, Wideband: MSPS, AIN1 29.3 MHz, AIN2 30.3
-100 -110 -120 SAMPLES ENCODE 105MSPS 40.9MHz (-0.56dBFS) 67.2dB SINAD 66.9dB SFDR -80dBc
-100 -110 -120 SAMPLES AIN1 70.3MHz (-7dBFS) AIN2 71.3MHz (-7dBFS) ENCODE 105MSPS
Figure Spectrum: MSPS, 40.9
Figure Two-Tone Spectrum, Wideband: MSPS, AIN1 70.3 MHz, AIN2 71.3
WORST CASE SPURIOUS dBFS -100 -110 -120 SAMPLES ENCODE 105MSPS 50.3MHz (-0.46dBFS) 67.0dB SINAD 66.7dB SFDR -80dBc
ANALOG INPUT POWER LEVEL dBFS ENCODE 105MSPS 50.3MHz dBFS
Figure Spectrum: MSPS, 50.3
Figure Single Tone SFDR
REV.
AD9432
1.00 0.75 0.50 0.25 0.00 VOLTAGE CURRENT
-0.25 -0.50 -0.75 -1.00
Figure Differential Nonlinearity: MSPS
Figure Voltage Reference Output Current Load
1.00 0.75 0.50 0.25 0.00
-0.25 -0.50 -0.75 -1.00
Figure Integral Nonlinearity: MSPS
REV.
AD9432
APPLICATION NOTES Theory Operation
AD9432 multibit pipeline converter that uses switched capacitor architecture. Optimized high speed, this converter provides flat dynamic performance frequencies near Nyquist. self-contained calibration feedback loop sequentially optimizes capacitor values within accuracy part 2048. This will limit transition error less than 0.25 LSB.
Often, cleanest clock source crystal oscillator producing pure sine wave. this configuration, with roughly symmetrical clock input, input ac-coupled biased reference voltage that also provides ENCODE. This ensures that reference voltage centered encode signal.
Digital Outputs
USING AD9432
ENCODE Input
digital outputs (2.7 TTL/CMOScompatible lower power consumption.
Analog Input
high speed converter extremely sensitive quality sampling clock provided user. track/hold circuit essentially mixer, noise, distortion, timing jitter clock will combined with desired signal output. that reason, considerable care been taken design ENCODE input AD9432, user advised give commensurate thought clock source. ENCODE input supports either differential single-ended fully TTL/CMOS compatible. Note that ENCODE inputs cannot driven directly from PECL level signals (VIHD max). PECL level signals easily accommodated coupling shown Figure Good performance obtained using MC10EL16 circuit drive encode inputs.
PECL GATE
analog input AD9432 differential buffer. input buffer self-biased on-chip resistor divider that sets common-mode voltage nominal (see Equivalent Circuits section). Rated performance achieved driving input differentially. Driving single-endedly will degrade performance. best dynamic performance, impedances should match. Special care taken design analog input section AD9432 prevent damage corruption data when input overdriven. nominal input range p-p.
AD9432
ENCODE ENCODE
Figure Coupling ENCODE Inputs
ENCODE Voltage Level Definition
voltage level definitions driving ENCODE ENCODE single-ended differential mode shown Figure ENCODE Inputs Differential Signal Amplitude (VID) min, High Differential Input Voltage (VIHD) Differential Input Voltage (VILD) Common-Mode Input (VICM) 1.25 min, High Single-Ended Voltage (VIHS) Single-Ended Voltage (VILS)
ENCODE ENCODE VIHD VICM VILD
Figure Full-Scale Analog Input Range
Voltage Reference
stable accurate voltage reference built into AD9432 (VREFOUT). input range adjusted varying reference voltage applied AD9432. appreciable degradation performance occurs when reference adjusted full-scale range tracks reference voltage changes linearly.
Timing
VIHS ENCODE
AD9432 provides latched data outputs, with pipeline delays. Data outputs available propagation delay (tPD) after rising edge encode command (see Figure length output data lines loads placed them should minimized reduce transients within AD9432; these transients detract from converter's dynamic performance. minimum guaranteed conversion rate AD9432 MSPS. internal clock rates below MSPS, dynamic performance degrade. Therefore, input clock rates below should avoided.
VILS
Figure Differential Single-Ended Input Levels
-10-
REV.
AD9432
Table Output Coding (VREF +2.5
Code +2047 -2048
AIN-AIN 1.000 -0.00049 -1.000
Digital Output 0111 1111 1111
0000 0000 0000 1110 0000 0000 1000 0000 0000
SINAD
Using AD8138 Drive AD9432
differential output from Analog Devices, Inc., AD8138 used drive AD9432 dc-coupled applications. AD8138 specifically designed driver applications. Superior performance maintained analog frequencies MHz. AD8138 provides single-ended-to-differential conversion, providing cost option transformer coupling applications well. circuit Figure breadboarded measured performance shown Figures figures shown supplies AD8138-performance cropped about dB-2 with single supply AD8138. Figure shows SINAD dBFS analog input frequency varied from with encode rate MSPS. measurements nominal conditions room temperature. Figure shows second third harmonic distortion performance under same conditions. common-mode voltage AD8138 outputs adjusted input VOCM provide common-mode voltage AD9432 inputs require.
Figure Measured SINAD (Encode MSPS)
-100
Figure Measured Second Third Order Harmonic Distortion (Encode MSPS)
AD9432
10pF
AD8138 22pF Vocm
10pF
Figure AD8138/AD9432 Schematic
REV.
-11-
AD9432
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
52-Lead Plastic Quad Flatpack (LQFP) (ST-52)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.472 (12.00)
SEATING PLANE VIEW
(PINS DOWN)
0.394 (10.0)
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.026 (0.65)
0.015 (0.38) 0.009 (0.22)
-12-
REV.
PRINTED U.S.A.
C3619-8-7/99

ENCODE ENCODE 12-Bit, MSPS/105 MSPS Converter AD9432 FUNCTIO

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