Dual Channel, Gain-Ranging with RSSI AD6600 11-bit, 20MSPS a

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Dual Channel, Gain-Ranging with RSSI AD6600 11-bit, 20MSPS a

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FEATURES Dual "IF" Inputs, 70-250 Diversity independent signals Separate Attenuation Paths Oversample Channels MSPS Single Carrier MSPS/channel Diversity Mode Total Signal Range from Automatic Gain-Ranging (AGC) from Converter Range >100 after Processing Gain Digital Outputs 11-Bit Word 3-Bit RSSI Word Clock, Indicator Single Power Supply Output DVCC +3.3V 775mW Power Dissipation APPLICATIONS Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA Wireless Local Loop, Fixed Access PRODUCT DESCRIPTION AD6600 mixed-signal receiver chip directly samples signals analog input frequencies MHz. device includes input channels, each with 1GHz input amplifiers 30dB automatic gain-ranging circuitry. Both channels sampled with 450MHz track-and-hold followed
Dual Channel, Gain-Ranging with RSSI
AD6600
11-bit, 20MSPS analog-to-digital converter. Digital RSSI outputs, channel indicator, Clock output, references, control circuitry on-chip. Digital output signals twos complement, CMOS-compatible interface directly +3.3V digital processing chips. primary dual analog input structure sampling both antennas two-antenna diversity receiver. However channels also used sample two, independent signals. Diversity, dual-channel mode, limited MSPS channel. single channel mode, full clock rate MSPS applied single carrier. AD6600 used stand-alone sampling chip, combined with AD6620 Digital Receive Signal Processor. AD6620 provides 10-25dB additional processing gain before passing data fixed floating point DSP. Driving AD6600 simplified using AD6630, differential amplifier. AD6630 easily matched inexpensive filters from MHz. Designed specifically cellular/PCS receivers, AD6600 supports GSM, IS-136, CDMA, Wireless LANs, well proprietary interfaces used WLL/fixed access systems. Units available plastic, surface-mount packages (44-pin TQFP) specified over industrial temperature range (-40°C +85°C).
NOISE FILTER
PRELIMINARY TECHNICAL DATA
-12,
RESONANT PORT
ATTEN
GAIN DETECT PEAK RSSI RSSI GAIN +12, GAIN Encode CONVERTER
TWOS
AB_OUT
ANALOG COMPLEMENT
SELECT GAIN
Encode RSSI
RSSI [2:0]
ATTEN
-12,
CLK2X
A_SEL
B_SEL
AVCC
DVCC
FUNCTIONAL BLOCK DIAGRAM REV. Analog Devices Specification
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringement patents other rights third parities which result from use. license granted implication otherwise under patent rights Analog Devices. Revcode:010699; AD6600 Marketing Administrator: (781) 937-1480
AD6600 SPECIFICATIONS SPECIFICATIONS (AVCC +5V, DVCC +3.3V; TMIN -40°C, TMAX +85°C unless otherwise specified)
Test AD6600AST Parameter Temp Level Units ANALOG INPUTS (AIN, BIN, Full Differential Analog Input Voltage Range1 Full Differential Analog Input Resistance2 +25°C Differential Analog Input Capacitance PEAK DETECTOR (internal), RSSI Resolution Bits RSSI Gain Step Full RSSI Hysterisis3 Full RESONANT PORT (FLT, Full Differential Port Resistance Full 1.75 Differential Port Capacitance CONVERTER Resolution Full Bits ENCODE INPUTS (ENC, Full Differential Input Voltage (ac-coupled)4 +25°C Differential Input Resistance +25°C Differential Input Capacitance MODE INPUTS (A_SEL, B_SEL)5 Input High Voltage Range Full 4.75 5.25 Input Voltage Range Full POWER SUPPLY Supply Voltages Full 4.75 5.25 AVCC Full 5.25 DVCC Supply Current AVCC (AVCC 5.0V) Full DVCC (DVCC 3.3V) Full POWER CONSUMPTION6 Full NOTES Analog Input Range function input frequency. specifications 70-250 inputs. Analog Input Impedance function input frequency. specifications 70-450 inputs. digital hysterisis used eliminate level uncertainty RSSI threshold points noise amplitude variations. Encode inputs should ac-coupled driven differentially. "Encoding AD6600" details. A_SEL B_SEL should tied directly ground AVCC. Maximum power consumption computed maximum current nominal supplies.
DIGITAL SPECIFICATIONS (AVCC +5V, DVCC +3.3V; TMIN -40°C, TMAX +85°C unless otherwise specified)
Test AD6600AST Parameter (Conditions) Temp Level LOGIC OUTPUTS (D10 AB_OUT, RSSI2-0)1 Logic Compatibility CMOS Logic Voltage (DVCC +3.3V) Full DVCC-0.2 Logic Voltage (DVCC +3.3V) Full Logic Voltage (DVCC +5.0V) Full DVCC-0.35 Logic Voltage (DVCC +5.0V) Full 0.35 Output Coding (D10 Twos Complement CLK2X OUTPUT1,2 Logic Voltage (DVCC +3.3V) Full DVCC-0.2 Logic Voltage (DVCC +3.3V) Full Logic Voltage (DVCC +5.0V) Full DVCC-0.3 Logic Voltage (DVCC +5.0V) Full 0.35 NOTES Digital output load gate. CLK2X output voltage levels, high low, tested switching rate 10MHz. Units
REV.
AD6600 SPECIFICATIONS TIMING REQUIREMENTS SWITCHING SPECIFICATIONS1
(AVCC +5V, DVCC +3.3V; MSPS; TMIN -40°C, TMAX +85°C unless otherwise specified) Test AD6600AST Parameter Name Temp Level Units CONVERTER fENC 1/(tENC) MSPS Conversion Rate MSPS Maximum Conversion Rate Full MSPS Minimum Conversion Rate Full psRMS Aperture Uncertainty +25°C ENCODE INPUTS (ENC, tENC Full Period tENCH Full Pulsewidth High3 tENCL Full Pulsewidth Low4 CLOCK OUTPUT (CLK2X)5 Output Frequency 2*fENC Full MSPS Output Period6 tCLK2X_1 tENCL Full tCLK2X_2 Full tENCH CLK2X Pulsewidth Low6 tCLK2XL Full tENCH/2 Output Risetime8 Full Output Falltime8 Full OUTPUT RISE/FALL TIMES9 Full Output Risetime (D10:D0, RSSI2:0) Full Output Falltime (D10:D0, RSSI2:0) Full Output Risetime (AB_OUT) Full Output Falltime (AB_OUT) NOTES AD6600 Timing Diagrams. switching specifications tested driving differentially. Several timing specifications function Encode high time, tENCH these specifications shown data tables timing diagrams. Encode duty cycle should kept close possible. Encode pulse directly affects amount settling time available resonant port. "External Analog (Resonant) Filter" section details. Clock generated internally, therefore some specifications functions encode period duty cycle. timing measurements from CLK2X referenced 2.0Vcrossing. This specification function Encode period duty cycle; reference timing diagrams Figure This specification function Encode period duty cycle. Output rise time measured from point point total CLK2X voltage swing; output fall time measured from point point total CLK2X voltage swing. Output rise time measured from point point total data voltage swing; output fall time measured from point point total data voltage swing. outputs specified with 10pF load.
REV.
AD6600 SPECIFICATIONS TIMING REQUIREMENTS SWITCHING SPECIFICATIONS cont.1
(AVCC +5V, DVCC +3.3V; MSPS, Duty Cycle 50%; TMIN -40°C, TMAX +85°C unless otherwise specified) Test AD6600AST Parameter Name Temp Level Units ENCODE/CLK2X Encode Rising CLK2X Falling6 Full Encode Rising CLK2X Rising5 (tENCH)/2 Full 25.7 27.2 28.7 Encode 13MSPS, Duty Cycle Full 19.0 20.5 22.0 Encode 20MSPS, Duty Cycle Full CLK2X/DATA (D10:0, RSSI2:0) CLK2X DATA Rising Delay6 t2X_DRL Full CLK2X DATA Hold Time6 tH_D2X Full 25°C CLK2X DATA Falling Low6,8 10.0 15.0 20.0 t2X_DFL Full 11.0 15.5 22.0 Full CLK2X DATA Setup Time5 tENCH t2X_DFL tS_D2X Full Encode 13MSPS, Duty Cycle 16.5 23.0 25°C Encode 20MSPS, Duty Cycle8 10.0 Full CLK2X/AB_OUT 11.0 t2X_ARL Full CLK2X AB_OUT Rising Delay6 11.0 tH_A2X Full CLK2X AB_OUT Hold Time6 25°C 12.0 18.0 23.0 t2X_AFL CLK2X AB_OUT Falling Delay6,8 Full 10.7 19.0 26.0 Full tENCH t2X_AFL tS_A2X CLK2X AB_OUT Setup Time5 Full 12.5 19.5 Encode 13MSPS, Duty Cycle 25°C Encode 20MSPS, Duty Cycle8 Full -1.0 ENCODE/DATA (D10:0, RSSI2:0) t2X_DRL Full tEN_DRL ENCODE DATA Rising Delay5 tEN_DRL Full tH_DEN ENCODE DATA Hold Time5 28.7 33.7 Full Encode 13MSPS, Duty Cycle 22.0 27.0 Full Encode 20MSPS, Duty Cycle t2X_DFL Full tEN_DFL ENCODE DATA Falling Delay5 Full tENC tEN_DFL tS_DEN ENCODE DATA Delay (Setup)5 Full 26.2 34.2 Encode 13MSPS, Duty Cycle 25°C 14.5 Encode 20MSPS, Duty Cycle8 Full 14.0 ENCODE/AB_OUT ENCODE AB_OUT Rising Delay5 tEN_ARL Full t2X_ARL ENCODE AB_OUT Delay (Hold)5 tH_AEN Full tEN_ARL Encode 13MSPS, Duty Cycle Full 32.7 38.2 Encode 20MSPS, Duty Cycle Full 26.0 31.5 ENCODE AB_OUT Falling Delay5 tEN_AFL Full t2X_AFL ENCODE AB_OUT Delay (Setup)5 tS_AEN Full tENC tEN_AFL Encode 13MSPS, Duty Cycle Full 22.2 30.7 25°C Encode 20MSPS, Duty Cycle8 11.5 Full 10.5 NOTES AD6600 Timing Diagrams. switching specifications tested driving differentially. Several timing specifications function Encode high time, tENCH these specifications shown data tables timing diagrams. Encode duty cycle should kept close possible. Reference AD6600 Timing Diagrams Clock generated internally, therefore some specifications functions encode period duty cycle. This specification function Encode period duty cycle. This specification function Encode period duty cycle. CLK2X referenced 2.0Vcrossing; digital output levels referenced 2.0V crossings; outputs with 10pF load. these particular specifications, "+25°C" specification valid from +25°C +85°C. "Full" temperature specification includes cold temperature extreme covers entire range, -40°C +85°C. REV.
AD6600 SPECIFICATIONS SPECIFICATIONS
(AVCC +5V, DVCC +3.3V; MSPS, Duty Cycle 50%; TMIN -40°C, TMAX +85°C unless otherwise specified) Test AD6600AST Parameter Temp Level Units ANALOG INPUTS1 Analog Input Bandwidth2 Full Differential Analog Input Voltage Range Full 2.45 Full 2.57 Full 2.62 Full 2.86 Differential Analog Input Impedance3 +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C j107 Full-scale Input Power Full Full Full Full Full-scale Gain Tolerance4 Full ±0.5 70-250 +25°C -1.0 ±0.1 +1.0 Gain Matching (Input A:B) Full ±0.1 70-250 Full -0.5 ±0.05 +0.5 Range-to-Range Gain Tolerance Full 70-250 ±0.1 Range-to-Range Phase Tolerance Full degree Full degree Channel Isolation6 Full Noise7 Full µVrms Minimum Attenuation Level Full µVrms Maximum Attenuation Level Attenuator 3OIP8 Full NOTES AIN, BIN, AD6600 analog inputs unconditionally stable guarantee proper operation over 70-250MHz specified operating range. Circuit board layout critical this device, proper layout must employed achieve specified results. Analog Input Bandwidth determined internal track-and-hold. front-end attenuators have bandwidth 1GHz Measured real imaginary values using Network Analyzer. Full-scale gain tolerance typical variation gain given input frequency. nominal value fullscale input power function frequency shown previous specification. Fullscale gain tolerance measured 200MHz analog input referenced 6.7dBm nominal fullscale input power. gain measurement test, input signal level -6dBFS. Tuning port bandwidth MHz. Main channel fullscale input power. Diversity channel swept from -20dBFS -90dBFS. Measurement includes thermal quantization noise 70MHz analog input. Tuning port bandwidth 50MHz. Test tones 160.05MHz 170.05MHz.
REV.
AD6600 SPECIFICATIONS SPECIFICATIONS cont.
(AVCC +5V, DVCC +3.3V; MSPS, Duty Cycle 50%; TMIN -40°C, TMAX +85°C unless otherwise specified) Test AD6600AST Parameter Temp Level Units Signal-to-Noise Ratio (SNR)1,2,3 +25°C -1dBFS +25°C 54.5 -6dBFS +25°C -10dBFS +25°C 48±6 -12dBFS -42dBFS +25°C -54dBFS +25°C -1dBFS +25°C -6dBFS +25°C -10dBFS +25°C 48±6 -12dBFS -42dBFS +25°C -54dBFS +25°C 57.5 -1dBFS1 +25°C 53.5 -6dBFS +25°C -10dBFS1 +25°C 48±6 -12dBFS -42dBFS2 +25°C -54dBFS3 +25°C -1dBFS +25°C 53.5 -6dBFS +25°C -10dBFS +25°C 48±6 -12dBFS -42dBFS +25°C -54dBFS HARMONIC Full -1dBFS Full -6dBFS 68±6 Full -12dBFS -42dBFS Full -1dBFS Full -6dBFS 67±6 Full -12dBFS -42dBFS MHz1,2,3 +25°C -1dBFS Full -6dBFS +25°C -10dBFS Full -12dBFS -42dBFS 65±6 Full -54dBFS Full -1dBFS Full -6dBFS Full -12dBFS -42dBFS 65±6 NOTES Measurements -1dFBS, -6dBFS, -10dBFS highest attenuation mode, RSSI Each gain-range checked ~3dB from RSSI trip point (not hysterisis); nominally -16dBFS (RSSI 100), -22dBFS (RSSI 011), -28dBFS (RSSI 010), -35dBFS (RSSI 001). Measurement dBFS lowest attenuation mode, RSSI 000.
REV.
AD6600 SPECIFICATIONS SPECIFICATIONS cont.
(AVCC +5V, DVCC +3.3V; MSPS, Duty Cycle 50%; TMIN -40°C, TMAX +85°C unless otherwise specified) Test AD6600AST Parameter Temp Level Units HARMONIC -1dBFS Full -6dBFS Full -12dBFS -42dBFS Full 67±6 -1dBFS Full -6dBFS Full -12dBFS -42dBFS Full 66±6 MHz1,2,3 +25°C -1dBFS Full -6dBFS +25°C -10dBFS Full 65±6 -12dBFS -42dBFS Full -54dBFS Full -1dBFS Full -6dBFS 65±6 Full -12dBFS -42dBFS WORST OTHER SPUR (4th higher) 74.5 Full -1dBFS Full -6dBFS 68±6 Full -12dBFS -42dBFS Full -1dBFS Full -6dBFS 67±6 Full -12dBFS -42dBFS +25°C -1dBFS Full -6dBFS +25°C -10dBFS Full 65±6 -12dBFS -42dBFS -1dBFS Full 66.5 -6dBFS Full -12dBFS -42dBFS Full 65±6 NOTES Measurements -1dFBS, -6dBFS, -10dBFS highest attenuation mode, RSSI Each gain-range checked ~3dB from RSSI trip point (not hysterisis); nominally -16dBFS (RSSI 100), -22dBFS (RSSI 011), -28dBFS (RSSI 010), -35dBFS (RSSI 001). Measurement dBFS lowest attenuation mode, RSSI 000.
REV.
AD6600 SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1 Parameter Units ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage2 AVCC Analog Input Current2 Digital Input Voltage3 AVCC Output Current4 AVCC Resonant Port Voltage5 ENVIRONMENTAL6 Operating Temperature Range (Ambient) Maximum Junction Temperature +150 Lead Temperature (Soldering, sec) +300 Storage Temperature Range (Ambient) +150 NOTES Absolute maximum ratings limiting values applied individually, beyond which serviceability circuit impaired. Functional operability necessarily implied. Exposure absolute maximum rating conditions extended period time affect device reliability. Pins AIN, BIN, Pins ENC, A_SEL, B_SEL Pins D10:0, RSSI2:0, AB_OUT, CLK2X Pins FLT, Typical thermal impedance (44-pin TQFP); 16°C/W, 55°C/W EXPLANATION TEST LEVELS Test Level 100% production tested. 100% production tested +25°C guaranteed design characterization temperature extremes. Parameter guaranteed design characterization testing. Parameter typical value only.
ORDERING GUIDE Model AD6600AST AD6600ST/PCB Temperature Range -40°C +85°C (Ambient) Package Description 44-Terminal TQFP (Thin Quad Plastic Flatpack) Evaluation Board with AD6600AST Package Option ST-44
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD6600 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
REV.
AD6600 SPECIFICATIONS
FUNCTION DESCRIPTIONS Name Function DVCC Digital Digital outputs. +3.3V. Ground. Internal bias point. Bypass GND. AVCC power supply. RSSI[2:0] RSSI digital output bits. B_SEL, A_SEL Mode Select pins analog input channel sampling. True analog input channel Complementary analog input channel Resonant Filters pins external noise filter. Complementary analog input channel True analog input channel Complementary Encode input. True Encode input. CLK2X clock output used clocking digital filter chips. AB_OUT Digital output flag indicating whether output input (high) (low). Digital data output (Least significant bit)1 D1-D9 Digital data output bits1 Digital data output (Most significant bit)1 NOTES Digital Outputs (D10:D0) Twos Complement Format
CONFIGURATION
0(MSB)
(LSB)
DVCC AVCC RSSI2 RSSI1 RSSI0 B_SEL A_SEL
AD6600 VIEW (Not Scale)
DVCC AVCC AB_OUT CLK2X AVCC
AVCC
AVCC
REV.
AVCC
AVCC
AD6600 SPECIFICATIONS
DEFINITIONS SPECIFICATIONS Analog Bandwidth analog input frequency which spectral power fundamental frequency determined analysis) reduced bandwidth determined internal track-and-hold when filter node resonated. Aperture Delay delay between point rising edge ENCODE command instant which analog input sampled. Aperture Uncertainty (Jitter) sample-to-sample variation aperture delay. Attenuator 3OIP third order intercept point front AD6600. point where third order products would theoretically intercept input signal level input level could increase without bounds. This measured using within AD6600 while input stimulated with dual tones minimum attenuation (i.e. maximum gain) range. Channel Isolation amount signal leakage from channel next when channel driven with fullscale input, other channel swept from dBFS -90dBFS with frequency offset. leakage measured side with smaller signal. Differential Analog Input Resistance, Differential Analog Input Capacitance Differential Analog Input Impedance real complex impedances measured each analog input port. resistance measured statically capacitance differential input impedances measured with network analyzer. Differential Analog Input Voltage Range peak peak differential voltage that must applied converter generate fullscale response. Peak differential voltage computed observing voltage single subtracting voltage from other pin, which degrees phase. Peak-to-peak differential computed rotating inputs phase degrees taking peak measurement again. Then difference computed between both peak measurements. Differential Nonlinearity deviation code width from ideal step. Differential Resonant Port Resistance resistance shunted across resonant port (nominally ohms). Used determine filter bandwidth gain that stage. Encode Pulse Width/Duty Cycle Pulse width high minimum amount time that ENCODE pulse should left logic state achieve rated performance; pulse width minimum time ENCODE pulse should left state. timing implications changing tENCH text. give clock rate, these specs define acceptable Encode duty cycle. Fullscale Gain Tolerance Unit unit variation fullscale input power. Fullscale Input Power Expressed dBm. Computed using following equation:
VFullscalerms Input .001
PowerFullscale
Gain Matching (Input A:B) Variation fullscale power between inputs. Harmonic Distortion, ratio signal amplitude value second harmonic component, reported dBc. Harmonic Distortion, ratio signal amplitude value third harmonic component, reported dBc. Integral Nonlinearity deviation transfer function from reference line measured fractions using "best straight line" determined least square curve fit. Minimum Conversion Rate encode rate which lowest analog signal frequency drops more than below guaranteed limit. Maximum Conversion Rate encode rate which parametric testing performed. Noise (for range within ADC)
Vnoise .001*10
SNRdBc SignaldBFS
Where input impedance, fullscale device frequency question, value particular input level Signal signal level within reported below fullscale. This value includes both thermal quantization noise.
REV.
AD6600 SPECIFICATIONS
DEFINITIONS SPECIFICATIONS cont. Range-Range Gain Tolerance gain error RSSI attenuator ladder from range next. Range-Range Phase Tolerance phase error RSSI attenuator ladder from range next. Differential Resonant Port Capacitance capacitance between resonant pins. Used determine filter bandwidth resonant frequency. RSSI Gain Step input amplitude span between taps RSSI (received signal strength) attenuator ladder. Ideally each stage should span input power. RSSI Hysterisis amount movement RSSI switch points depending direction approach. Hysterisis prevents unnecessary RSSI toggling when input signal power near threshold. Signal-to-Noise Ratio (without Harmonics) ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics Worst Other Spur ratio signal amplitude value worst spurious component (excluding harmonic) reported dBc.
AD6600 TRANSFER FUNCTION
(dB)
-100 Level (dBFS) Figure AD6600 versus Input Power
REV.
AD6600 SPECIFICATIONS
EQUIVALENT CIRCUITS
AVCC
ATTENUATOR STAGE
EQUIVALENT INPUT SHOWN ONLY
AVCC VREF
4X/8X GAIN STAGE
GAIN
Figure Analog Input Stage (Channel shown; Channel equivalent)
External Filter
AVCC AVCC AVCC
From Gain Stage
Figure Resonant Noise Filter) Port
REV.
AD6600 SPECIFICATIONS
EQUIVALENT CIRCUITS cont.
AVCC
AVCC
ISEL ISEL_B
AVCC
A_SEL BIAS
B_SEL
Figure A_SEL, B_SEL Input Mode Pins
AVCC
AVCC
AVCC ENCODE TIMING CIRCUITS
ENCODE
Figure Encode Inputs
DVCC DVCC
CURRENT MIRROR
CURRENT MIRROR
DVCC VREF VREF RSSI[2:0]
DVCC CLK2X AB_OUT
CURRENT MIRROR
CURRENT MIRROR
Figure Digital Outputs
Figure CLK2X, AB_OUT Outputs
REV.
AD6600 SPECIFICATIONS
AD6600 TIMING DIAGRAMS
tENCH
tENCL
tENC
ENCODE tCR1 tCF1 CLK2X
CLK2X2
tCR2 tCLK2XL
CLK2X1
tCLK2X2 tCLK2XL tCLK2XH2
CLK2X2
tCLK2X1 tCLK2XH1
CLK2X1 CLK2X2
tCF2
t2X1_DFL t2X1_DRL D[10:0], RSSI[2:0]
t2X1_ARL
t2X1_AFL
AB_OUT
Figure Encode CLK2X Delays CLK2X Propagation Delays
tENCH
tENCL
tENC
ENCODE tCR1 tCF1 CLK2X
CLK2X2
tCR2 tCLK2XL
CLK2X1
tCLK2X2 tCLK2XL tCLK2XH2
CLK2X2
tCLK2X1 tCLK2XH1
CLK2X1 CLK2X2
tCF2
tH_D2X D[10:0], RSSI[2:0]
tS_D2X
tH_D2X
tS_D2X
tH_A2X
tS_A2X
tH_A2X
tS_A2X
AB_OUT
Figure CLK2X Setup Hold Time Characteristics
REV.
AD6600 SPECIFICATIONS
AD6600 TIMING DIAGRAMS cont.
tENCH
tENCL
tENC
ENCODE
ENCODE
ENCODE
ENCODE
tCR1 tCF1 CLK2X
CLK2X2
tCR2 tCLK2XL
CLK2X1
tCLK2X2 tCLK2XL tCLK2XH2
CLK2X2
tCLK2X1 tCLK2XH1
CLK2X1 CLK2X2
tCF2
tEN_DFL tEN_DRL D[10:0], RSSI[2:0]
tEN_AFL
tEN_ARL
AB_OUT
Figure Encode CLK2X Delays Encode Propagation Delays
tENCH
tENCL
tENC
ENCODE
ENCODE
ENCODE
ENCODE
tCR1 tCF1 CLK2X
CLK2X2
tCR2 tCLK2XL
CLK2X1
tCLK2X2 tCLK2XL tCLK2XH2
CLK2X2
tCLK2X1 tCLK2XH1
CLK2X1 CLK2X2
tCF2
tH_DEN D[10:0], RSSI[2:0]
tS_DEN
tH_DEN
tS_DEN
tH_AEN
tS_AEN
tH_AEN
tS_AEN
AB_OUT
Figure Encode Setup Hold Time Characteristics
REV.
AD6600 SPECIFICATIONS
AD6600 TIMING DIAGRAMS cont.
CLK2X
D[10:0], RSSI[2:0]
AB_OUT Figure Typical Output Rise Fall Times
ENCODE
CLK2X Figure Encode MSPS, Duty Cycle
ENCODE
CLK2X Figure Encode MSPS, Duty Cycle
REV.
AD6600 SPECIFICATIONS
THEORY OPERATION AD6600, dual-channel, gain-ranging integrates analog circuitry with high-speed data conversion. Each analog input stage 1GHz, -24dB, phase-compensated step attenuator; step size each attenuator 12dB. Both input stages drive analog multiplex function followed +12/+18 gain amplifier. simple noise filter output gain amplifier required resonate desired This resonant filter port precedes wide input bandwidth (450MHz) track-and-hold followed 11-bit analog-to-digital converter (ADC). high-speed synchronous peak detector monitors signal strength both input channels. peak detector drives RSSI circuitry that automatically adjusts attenuation gain clock clock basis. Both three RSSI indicator bits eleven bits available output providing exponent mantissa data format. Together these integrated components form sampling, high dynamic range system.
NOISE FILTER
maximum gain. However when input signal level gets into gain-ranging section (approx. -42dBFS), contained between about between including effects hysterisis. Although graph above does indicate there slight differences between from gain range next gain switches between 12dB 18dB. Once final RSSI range been exceeded (approx. -12dBFS), again increases input power increase until converter fullscale reached. Again, this performance very much like effects typical analog loop. AD6600 SUBCIRCUITS Input Step Attenuator Gain Stage AD6600 identical input attenuators, channel channel These dual inputs typically used diversity channels also process independent signals. maximum oversampling device used single channel mode; this case only input channel required. attenuator steps attenuator settings based decisions RSSI stage (ref. Peak Detector/RSSI section). outputs attenuators connect analog multiplexer that selects either channel subsequent processing (ref. Input Mode). selected signal drives dual-gain amplifier either selected gain also determined RSSI stage. Therefore, based possible combinations attenuation gain, input signal receives voltage gain steps (Table Overall gain-matching typically within 0.1dB. with bandwidth GHz, phase delay through front-end ranges from degrees depending input frequency. Additionally, input impedance does change with attenuator settings there distortion. Attenuator Gain Total RSSI Word
-12,
RESONANT PORT
ATTEN
GAIN DETECT PEAK RSSI RSSI GAIN +12, GAIN Encode CONVERTER
TWOS COMPLEMENT
AB_OUT
ANALOG
SELECT GAIN Encode
RSSI
RSSI [2:0]
ATTEN
-12,
TIMING
CLK2X
A_SEL
B_SEL
AVCC
DVCC
helpful view this device stand-alone using automatic gain control. gain-control referred this data sheet gain-ranging, works maintain constant over wide range possible.
(dBFS)
Table Attenuator Gain Settings
High Speed Peak Detector RSSI Circuitry peak detector along with attenuator dual gain amplifier form control loop within AD6600. peak detector designed follow analog input clock cycle before conversion actually made. Therefore, while converter section AD6600 converting sample `n', peak detector already looking sample `n+1'. While looking `n+1' sample (the calibration period), peak detector examines envelope input signal. more envelope that tracked, more accurate gain setting. very least, peak detector must presented either positive negative sinusoidal peak, which represents about cycle sine wave.
(dB)
12dB WINDOW
Figure Gain-Ranging stated previously, AD6600 floating-point output: eleven mantissa bits three exponent bits. shown Figure lowest input levels increases increase input power. this range, AD6600 REV.
AD6600 SPECIFICATIONS
Since peak detector works complete cycle prior conversion, absolute minimum frequency that determined twice sample rate channel. Therefore MSPS, minimum frequency that sampled would MHz. Note that more cycles input that monitored peak detector, more accurate gain setting will Therefore, actual minimum frequency recommended higher than this. minimum specified frequency MHz. Since RSSI control loop performed sample sample basis, AD6600 follows signals into deep fade very accurately. Hysterisis AD6600 employs hysterisis prevent gain-ranging from unnecessarily changing when signal envelope near RSSI threshold. hysterisis digital will account exactly shift depending whether signal increasing decreasing. This effect shown dashed lines overall transfer function, Figure External Noise Filter, Resonant Port output attenuator/gain stage drives wide bandwidth track-and-hold (T/H), followed encoder. Because attenuator/gain stage very wide bandwidth GHz), filter "resonant port" provided limit amount wideband noise delivered ADC. simple filter does provide signal selectivity should typically wide. However, because ADC's track-and-hold itself wide bandwidth (~450MHz), this noise-limiting filter critical meeting overall sensitivity. Specific details selecting components resonant port provided later text (Understanding External Analog Filter). Encoder After calibration period complete (one clock cycle), appropriate gain attenuator settings determined set. Once settled, internal track-and-hold freezes input signal that encoder digitize signal. During digitization, peak detector/RSSI circuitry already looking next sample. When AD6600 dual channel mode, process interleaved: while channel monitored signal strength, channel digitized. This allows RSSI update clock clock basis.
Encode Digitize Data Hold Track Digitize Hold
Input Internal Clock RSSI Calibration Amplifier Control RSSI Cal. Noise Filter Discharge
RSSI
Noise Filter Settling
Input
Clamped Noise Filter Settling
Figure AD6600 Internal Timing Figure shows internal timing chip works. encode applied device initiates several actions. first most important that track-and-hold placed hold thus sampling analog input that instant. second action that peak detector RSSI circuitry initialized. During this period, analog input envelope monitored determine signal power. AD6600 calibration mode about quarter encode period. While AD6600 calibration, external noise filter discharged amplifier driving filter disabled. Since this filter shared between input channels dual channel mode, this greatly reduces feed-though between channels that would otherwise exist. quarter encode period after calibration complete, amplifier re-enabled allowed settle signal conditions sampling wideband next encode signal. final action that signal resonant port sampled track-and-hold. This happens next rising edge encode. Input Mode Select AD6600 operating modes: single channel dual channel. single channel mode, always samples channel always samples channel dual channel mode, converter sampling channel channel alternating Encode cycles. control pins provided select desired mode operation. A_SEL B_SEL arbitrate selection these input channels connected output. Table shows truth table selection input. Output Encode Clock
Mode Dual: Single: Single: Valid
A_SEL
B_SEL
Table Selecting AD6600 Operating Mode A_SEL B_SEL logic inputs should tied directly ground analog volts analog). REV.
AD6600 SPECIFICATIONS
dual channel mode, AB_OUT signal indicates which input currently available digital output. When AB_OUT digital output digitized version channel Likewise, when AB_OUT channel available digital output (Table A_SEL B_SEL D[10:0], RSSI[2:0] ABOUT Outputs Data Encode Clock RSSI 11-Bit Word DATA DATA DATA DATA DATA DATA 16-bit Data Format DATA DATA DATA DATA DATA DATA Corresponds shift right
Table 16-Bit, Fixed-Point Data Format Table ABOUT Dual Channel Operation Data Output Stage output stage provides data form mantissa, D[10:0], exponent, RSSI[2:0] where D[10:0] represents output 11-bit coded twos complement, RSSI[2:0] represents gain-range setting coded offset binary. Table shows nominal gain-ranges nominal, 2Vpp differential fullscale input. Keep mind that actual fullscale input voltage power will vary with input frequency. Differential Analog Input Voltage (VPP) 0.25 0.125 0.25 0.0625 0.125 0.03125 0.0625 0.03125 RSSI [2:0] Binary Decimal Equiv. Attenuation Gain (dB) When mated with AD6620, Digital Receive Processor chip, AD6600 floating point data (mantissa exponent) automatically converted 16-bit twos complement format AD6620. APPLYING AD6600 Encoding AD6600 AD6600 encode signal must high quality, extremely phase noise source prevent degradation performance. Digitizing high frequency signals range 70-250MHz) places premium encode clock phase noise. performance easily degrade 3-4dB with 70MHz input signals when using questionable clock source. higher 250MHz) with questionable clock sources higher slew rates input signals reduce performance even further. AN501, "Aperture Uncertainty System Performance" complete details. optimum performance AD6600 must clocked differentially. encode signal usually ac-coupled into pins transformer capacitors. These pins biased internally require additional bias. Figure shows preferred method clocking AD6600. sine source (low jitter) converted from single-ended differential using transformer. backto-back Schottky diodes across transformer secondary limit clock excursions into AD6600 approximately 0.8Vp-p differential. This helps prevent sharp edges clock from feeding other portions AD6600, limit noise presented encode inputs. crystal clock oscillator also used drive transformer appropriate limiting resistor (typically 100) placed series with primary.
T1-1T ENCODE AD6600 ENCODE 5082-2810 DIODES
Table Interpreting RSSI Bits digital processing chip which follows AD6600 combine bits twos complement data, with RSSI bits form 16-bit equivalent output word. Table explains RSSI data interpreted when using ASIC. Basically, circuit performs right shifts data depending RSSI word. This also performed software using following pseudo code fragment. r0=dm(rssi); r2=5; r0=r2-r0; r1=dm(adc);(11 bits, justified into word) rshift r0;(arithmetic shift extend sign bit) result shifted data fixed-point word that used normal 16-bit word.
SINE SOURCE
Figure Transformer-Coupled Sine Source
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AD6600 SPECIFICATIONS
jitter ECL/PECL clock available, another option ac-couple differential ECL/PECL signal encode input pins shown Figure
0.1uF ENCODE ECL/ PECL 0.1uF AD6600 ENCODE
suited many application AD6600. more information AD6630, reference AD6630 datasheet. When general purpose gain blocks used, matching easily achieved using transformer. Most gain blocks available with 50ohm input output ports. Thus matching 200ohm impedance AD6600 requires only 1:4(impedance ratio) transformer shown Figure
from mixer output Gain Block
AD6600
Figure Transformer-Coupled Gain Block rare case that better matching required, conjugate match between amplifier selected transformercoupled analog input achieved placing matching network between amplifier transformer (Figure 21). more details matching, reference mentioned above more details.
Figure AC-Coupled ECL/PECL Encode Driving Analog Inputs with most high-speed, high dynamic range analog-todigital converters, analog input AD6600 differential. Differential inputs allow much improvement performance on-chip signals processed through attenuation gain stages. Most improvement result differential analog stages having high rejection even order harmonics. There also benefits level. First, differential inputs have high common mode rejection stray signals such ground power noise. Also, they provide good rejection common mode signals such local oscillator feed-through. Driving differential analog input introduces some challenges. Most RF/IF amplifiers single-ended obviously interface AD6600. However, using simple techniques, clean interface possible. recommended method drive analog input port shown below. AD6600 input actually designed match easily filter such SAWTEK 855297. This allows filter used differential mode, which often improves operations filter. Using network analyzer data both filter output AD6600 input ports (see data tables AD6600 data), conjugate match used maximum power transfer. Often adequate match achieved simply using shunt inductor make port look real (Figure 19). more details exactly match networks, Circuit Design Chris Bowick, ISBN: 0-672-21868-2.
from mixer output AD6630 AD6600
from mixer output Gain Block
Matching Network
AD6600
Figure Gain Block Matching Network Understanding External Analog Filter primary tradeoffs must made when designing external resonant filter. obvious bandwidth filter. second obvious tradeoff settling time filter nodes. Resonant Filter Bandwidth determines amount noise that limited center frequency chosen. resonant filter wide, little noise improvement seen. resonant filter narrow, amplitude variation seen tolerance filter components. narrow filter center these tolerances drift), 4x/8x signal will fall transition band filter. optimum starting point this filter approximately 50MHz. Resonant Filter Settling limits amount capacitance this filter. output 4x/8x amplifier clamped when processing input (encode high time). This prevents output from feeding through (T/H) corrupting results. But, upon falling edge encode, must come clamp present accurate signal T/H. external filter determines settling amp. output does settle, sees attenuated signal. obviously narrow bandwidth desired improve noise performance, filter narrow, will settle will attenuated signal.
Figure Cascaded Filters with AD6630 Where gain required, AD6630 differential, noise, gain block recommended. This amplifier provides gain provides limiting prevent damage filter AD6600. AD6630 designed reside between filters. This noise device ideally
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AD6600 SPECIFICATIONS
AVCC
time; number bits
RESONANT FILTER PORT
Ctotal (Tencode 0.5) 38.5ns 13.6 8192) ln(8192)
From Gain Stage
CLAMP
ENCODE
Figure 4x/8x Amplifier Clamp Circuitry Figure shows simplified model 4x/8x amplifier. point note resistor values collector legs ohms nominal with tolerance +/-20%. filter performance determined these values conjunction with internal parasitic capacitance, board parasitics, external filter components.
ENCODE Hold Track Hold
this case, Ctotal includes parasitics external capacitance. nominally ohms. 8192 (4*2048), which converter bits, 2048). settling purposes, with 13MSPS encode duty cycle, maximum allowable capacitance proper settling Ctotal 13.6pF. stated above this Ctotal includes external capacitors, board parasitics, AD6600 parasitics. parasitics AD6600 (lead, internal bond pad, internal connections) 1.75pF 0.35pF (differential). resistors maximum value (315 +20%), maximum allowable capacitance Ctotal 11.3pF. duty cycle less than then maximum allowable capacitance decreased further, allow settling. Power Supplies Care should taken when selecting power source. Linear supplies strongly recommended. Switching supplies tend have radiated components that "received" AD6600. Each power supply pins should decoupled closely package possible using 0.1uF chip capacitors. AD6600 separate digital analog power supply pins. analog supplies denoted AVCC digital supply pins denoted DVCC. Although analog digital supplies tied together, best performance achieved when supplies separate. This because fast digital output swings couple switching back into analog supplies. Note that AVCC must held within Volts; however DVCC supply varied according output digital logic family. AD6600 specified DVCC 3.3V this common supply digital ASICS.
RESONANT FILTER
Clamped
Settling
Figure 4x/8x Amplifier Settling Figure shows settling important this circuit. 4x/8x doesn't settle (come clamp) then amplitude presented will decreased. This results decreased gain when filter capacitance high. This explains total capacitance that allowed external filter varies depending clock rate (actually encode clock high time). encode 13MSPS duty cycle then allowable settling time 38.5ns (1/2 encode time). assumption that should allowed settle this time period. This been proven with both simulation empirical analysis. settling assumed circuit, then:
REV.
AD6600 SPECIFICATIONS
Output Loading Care must taken when designing data receivers AD6600. Note from equivalent circuits shown earlier (ref. Equivalent Circuits) that D[10:0] RSSI[2:0] contain 500-ohm output series resistor. minimize capacitive loading, there should only gate each output pin. Extra capacitive loading will increase output timing invalidate timing specifications. CLK2X AB_OUT contain output series resistors. Testing digital output timing performed with 10pF loads. Layout Information schematic evaluation board (Figures represents typical implementation AD6600. multilayer board recommended achieve best results. highly recommended that high quality, ceramic chip capacitors used decouple each supply ground directly device. pinout AD6600 facilitates ease implementation high frequency, high resolution design practices. digital outputs segregated sides chip, with inputs opposite side isolation purposes. Care should taken when routing digital output traces. prevent coupling through digital outputs into analog portion AD6600, minimal capacitive loading should placed these outputs. recommended that fan-out only used AD6600 digital outputs. layout analog inputs external resonant filter critical. digital traces must routed near, under, above these portions circuit. transformers used coupling into analog inputs must located close possible analog inputs AD6600. external resonant filter components must physically close filter-input pins, separated from analog inputs. layout Encode circuit equally critical. noise received this circuitry will result corruption digitization process lower overall performance. Encode clock must isolated from digital outputs analog inputs. Evaluation Board evaluation board AD6600 straightforward, containing required circuitry evaluating device. only external connections required power supplies, clock, analog inputs. evaluation board includes option onboard, clock oscillator encode. Power analog supply pins AD6600 connected power terminal block (TB1). Power digital interface supplied J201, e-hole located adjacent J201. supply vary between +3.3V 5.0V sets level output digital data (J201). J201 connector mates directly with AD6620 (Receive Signal Processor) evaluation board, part# AD6620S/PCB, allowing complete evaluation system performance. analog inputs connected connectors BIN, which transformer-coupled AD6600 inputs. transformers have turns-ratio match input resistance AD6600 (200 ohms) ohms connectors. Encode signal generated using onboard crystal oscillator, U100. onboard crystal used, R104 must removed from board prevent loading oscillator's output. on-board oscillator replaced external encode source connector labeled ENCODE. external source used, must high quality very phase noise source. high-IF range AD6600 (70-250MHz) demands that Encode clock sufficiently pure maintain performance. AD6600 output data latched using 74LCX574 (U201, U202) latches. clock these latches determined jumper selection header clock delayed version encode clock (CLKA, CLKB), CLK2X generated AD6600. clock also distributed with output data (J201) that labeled CLKX (pin J201). CLKX selected with jumpers header CLKA, CLKB, CLK2X. resonant filter components (SEL2, omitted. user must install proper values based chosen. "Understanding External Analog Filter" section data sheet guidelines selecting these components.
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AD6600 SPECIFICATIONS
Item Quantity Reference AIN, BIN, ENCODE C102-108, C111, C114, C117-118, C120-121, C299 C112-113, C115-116 CR2-3 J201 R1-2 R100-101 R103 R104 R298 R299 T1-2, Description Connector 0.1uF Chip Inductance 0.1uF Chip 1N2810 Schottky Diode AD6600AST 20-Pin Double Male Header 50-Pin Double Male Header, Right Angle Omitted Surface Mount Resistor 1206, Surface Mount Resistor 1206, Surface Mount Resistor 1206, Surface Mount Resistor 1206, 3.9k Surface Mount Resistor 1206, Surface Mount Transformer Mini-Circuits T4-1T
Table AD6600ST/PCB Bill Material
Figure AD6600ST/PCB Schematic Diagram, Page
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AD6600 SPECIFICATIONS
Figure AD6600ST/PCB Schematic Diagram, Page
Figure AD6600ST/PCB Side Silk Screen REV.
Figure AD6600ST/PCB Side Copper
AD6600 SPECIFICATIONS
Connecting AD6600 with AD6620 AD6600 interfaces directly AD6620 Digital Receive Signal Processor shown Figure addition external components required. Note that layout requirements discussed previously apply deviations result degraded performance. digital outputs AD6600 must connect directly AD6620 inputs with additional fan-out. Additional loading outputs will compromise timing performance.
(MSB) IN15
AD6600
(LSB)
AD6620
EXP2 EXP1 EXP0
Figure AD6600ST/PCB Bottom Side Copper
RSSI2 RSSI1 RSSI0 AB_OUT CLK2X
Figure AD6600/AD6620 Connections Figure shows timing details between AD6600 AD6620. Clock D[10:0], RSSI[2:0], AB_OUT captured AD6620. Since AB_OUT changed state from previous clock, D[10:0] RSSI[2:0] processed AD6620. This clock allows adequate setup hold time AB_OUT, D[10:0], RSSI[2:0] captured AD6620. Clock2, D[10:0], RSSI[2:0], AB_OUT captured AD6620. Since AB_OUT changed from previous clock, D[10:0] RSSI[2:0] ignored AD6620. This clock concerned only with AB_OUT setup hold time. Figure AD6600ST/PCB Power Supply Layer (Negative)
Figure AD6600ST/PCB Ground Layer (Negative) REV.
AD6600 SPECIFICATIONS
Timing w.r.t. CLKK2X (Encode 13MSPS, Duty Cycle 50%)
38.5 38.5 Clock1 Clock2
CLK2X
16.5 16.5
D[10:0], RSSI[2:0]
12.5
AB_OUT
Figure AD6600 AD6620 Timing 13MSPS
AD6600AST OUTLINE DIMENSIONS
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.472 (12.00)
SEATING PLANE VIEW
(PINS DOWN)
0.394 (10.0)
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.031 (0.80)
0.018 (0.45) 0.012 (0.30)
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Dual Channel, Gain-Ranging with RSSI AD6600 11-bit, 20MSPS a

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