Serial Digital Controlled Variable Gain Line Driver AD8320 REFERE

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Serial Digital Controlled Variable Gain Line Driver AD8320 REFERE

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FEATURES 8-Bit Serial Gain Control V/V/LSB Linear Gain Response Gain Range 0.20 Gain Accuracy Upper Bandwidth: Compression Point Drives Distortion Signals into Load: SFDR SFDR Single Supply Operation from Maintains Output Impedance Power-Up Power-Down Condition Supports Input Control Standard APPLICATIONS Coaxial Cable Driver Cable Telephony Systems High Speed Data Modems Interactive Set-Top Boxes Plug-In Modems Interfaces with AD9853 Controlled Digital Modulator High Performance Digitally Controlled Variable Gain Block
Serial Digital Controlled Variable Gain Line Driver AD8320
REFERENCE
AD8320
VOUT
VREF
INV.
ATTENUATOR CORE
REVERSE
BUF. DATA LATCH POWERDOWN/ SWITCH INTER.
DATA SHIFT REGISTER
DATEN
SDATA
DESCRIPTION
AD8320 digitally controlled variable gain amplifier optimized coaxial line driving applications. 8-bit serial word determines desired output gain over range (256 gain levels). AD8320 provides linear gain response. AD8320 made digitally controlled variable attenuator which preceded noise, fixed gain buffer followed distortion high power amplifier. AD8320 input impedance accepts single-ended input signal with specified analog input level 0.310 p-p. output specified driving load, such coaxial cable, although AD8320 capable driving other loads. Distortion performance achieved with output level (3.1 p-p) MHz, while distortion achieved with output level (6.2 p-p). performance cost advantage AD8320 results from ability maintain constant output impedance during power-up power-down conditions. This eliminates need external back-termination, resulting twice effective output voltage when compared standard operational amplifier. Additionally, on-chip termination
results glitch output during power-down power-up transitions, eliminating need external switch. AD8320 packaged 20-lead SOIC operates from single through supply operational temperature range -40°C +85°C.
18dBm
DISTORTION
8dBm
12dBm
4dBm FREQUENCY
Figure Worst Harmonic Distortion Frequency Various Output Levels
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998
AD8320-SPECIFICATIONS otherwise noted)
Parameter INPUT CHARACTERISTICS Full-Scale Input Voltage Input Resistance Input Capacitance GAIN CONTROL INTERFACE Gain Range Full Scale (Max) Gain Gain Offset (Min) Gain Gain Scaling Factor OUTPUT CHARACTERISTICS Bandwidth Bandwidth Roll-Off Bandwidth Peaking Output Offset Voltage Output Offset Drift Output Noise Spectral Density Conditions
0.310 p-p,
0.310 0.155
unless
Units (V/V) (V/V) V/V/LSB mV/°C nV/Hz nV/Hz nV/Hz mdB/°C mdB/V
Gain, POUT dBm, Gain, POUT dBm,
(20) -10.0 (0.316) 0.077 Gain Codes Gain Codes Full Temperature Range Max. Gain, Frequency Min. Gain, Frequency Frequency Power Power Down Gain, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, POUT dBm, MHz, Gain Codes Full Temperature Range Gain, 0.31 Gain, 0.31 Gain, Gain, Gain, (PD) Duty Cycle 0.25 22.5 -57.0 -43.0 -46.0 -57.0 -42.5 -43.0 32.5 28.5
Compression Point Output Impedance Overload Recovery OVERALL PERFORMANCE Worst Harmonic Distortion
-52.0 -39.0 -42.0 -52.0 -39.0 -40.0
Order Intercept
Full-Scale (Max Gain) Accuracy Gain Offset (Min Gain) Accuracy Gain Accuracy Gain Drift Gain Variation w/Supply Output Settling Gain Change TDATEN Input Change POWER CONTROL Power-Down Settling Time Power-Up Settling Time Power-Down Pedestal Offset Spectral Output Leakage Maximum Reverse Power POWER SUPPLY Specified Operating Range Quiescent Current Power Down Power Power Down, =+12
-0.75
0.75
REV.
AD8320 LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA,
Parameter Logic Voltage Logic Voltage Logic Current (VINH CLK, SDATA, DATEN Logic Current (VINL CLK, SDATA, DATEN Logic Current (VINH Logic Current (VINL
Full Temperature Range)
Units
-450 -320
TIMING REQUIREMENTS (Full Temperature Range,
Parameter Clock Pulse Width (TWH) Clock Period (TC) Setup Time SDATA Clock (TDS) Setup Time DATEN Clock (TES) Hold Time SDATA Clock (TDH) Hold Time DATEN Clock (TEH) Input Rise Fall Times, SDATA, DATEN, Clock (TR,
SDATA
VALID DATA WORD MSB. .LSB
Supply Range, FCLK unless otherwise noted.)
12.0 32.0 17.0 Units
VALID DATA WORD
DATEN
CLOCK CYCLES
GAIN TRANSFER (G1) TOFF
GAIN TRANSFER (G2)
ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL
Figure Serial Interface Timing
VALID DATA
MSB-1
MSB-2
Figure
REV.
AD8320
ABSOLUTE MAXIMUM RATINGS* CONFIGURATION
SDATA DATEN VOCM
VREF
Supply Voltage Pins -0.8 Input Voltages Pins Pins -0.8 Internal Power Dissipation Small Outline (RP) Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature, Soldering seconds +300°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
AD8320
VIEW (Not Scale)
VOUT
ORDERING GUIDE
Model AD8320ARP AD8320-EB
Temperature Range -40°C +85°C
Package Description 20-Lead Thermally Enhanced Power SOIC* Evaluation Board
Package Option RP-20
53°C/W
*Shipped tubes pieces/tube) packed J-STD-020.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD8320 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. FUNCTION DESCRIPTIONS
WARNING!
SENSITIVE DEVICE
Function SDATA
Description Serial Data Input. This digital input allows 8-bit serial (gain) word loaded into internal register with (most significant bit) first. Clock Input. clock port controls serial attenuator data transfer rate 8-bit master-slave register. Logic transition latches data transfers data slave. This requires input serial data word valid before this clock transition. Data Enable Input. This port controls 8-bit parallel data latch shift register. Logic transition transfers latched data attenuator core (updates gain) simultaneously inhibits serial data transfer into register. transition inhibits data latch (holds previous gain state) simultaneously enables register serial data load. Common External Ground Reference. VCC/2 Reference Pin. output reference level that equal supply voltage (VCC). This port should externally decoupled (0.1 cap). Power-Down Logic Input. Logic powers down (shuts off) power amplifier disabling output signal enabling reverse amplifier. Logic enables output power amplifier disables reverse amplifier. Common Positive External Supply Voltage. Output Signal Port. biased approximately VCC/2. Internal Bypass. This must externally decoupled (0.1 cap). Input Reference Voltage (typically 27°C). This port should externally decoupled (0.1 cap). Analog Voltage Input Signal Port. biased VREF voltage.
DATEN
VOCM
VOUT VREF
REV.
Typical Performance Characteristics-AD8320
10MHz
GAIN ERROR
0.45 0.30 10MHz
GAIN ERROR
GAIN ERROR
10MHz
0.15
42MHz 65MHz
0.15 0.30 0.45
GAIN CONTROL Decimal
GAIN CONTROL Decimal
GAIN CONTROL Decimal
Figure Gain Error Gain Control Various Temperatures
Figure Gain Error Gain Control Various Frequencies
Figure Gain Error Gain Control Different Supply Voltages
255D 170D GAIN
GAIN
255D 170D
FEEDTHROUGH 100k
GAIN
14dBm
12V, 100M FREQUENCY
8dBm
100k
100M FREQUENCY
100k
100M FREQUENCY
Figure Response
Figure Response
Figure Input Signal Feedthrough Frequency
10MHz
10MHz
OUTPUT NOISE
OUTPUT NOISE
GAIN,
OUTPUT NOISE
GAIN, GAIN,
GAIN, 100k
GAIN CONTROL Decimal
GAIN CONTROL Decimal
FREQUENCY
100M
Figure Output Referred Noise Gain Control Various Temperatures
Figure Output Referred Noise Gain Control Different Supply Voltages
Figure Output Referred Noise Frequency
REV.
AD8320
65MHz, 18dBm
DISTORTION
DISTORTION
DISTORTION
42MHz, 18dBm
12dBm 10dBm 8dBm 4dBm
10dBm
12dBm
42MHz, 12dBm 65MHz, 12dBm GAIN CONTROL Decimal
8dBm
4dBm
FREQUENCY
FREQUENCY
Figure Worst Harmonic Distortion Gain Control
Figure Worst Harmonic Distortion Frequency Various Output Levels
Figure Worst Harmonic Distortion Frequency Various Output Levels
18dBm 42MHz
18dBm
DISTORTION
18dBm
PERCENTAGE
DISTORTION
8dBm
12dBm
8dBm
12dBm
4dBm
4dBm
FREQUENCY
FREQUENCY
HARMONIC DISTORTION
Figure Worst Harmonic Distortion Frequency Various Output Levels
Figure Worst Harmonic Distortion Frequency Various Output Levels
Figure Distribution Worst Harmonic Distortion
18dBm 65MHz
12dBm 42MHz
30.0 12dBm 65MHz
PERCENTAGE
22.5
PERCENTAGE
PERCENTAGE
15.0
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
Figure Distribution Worst Harmonic Distortion
Figure Distribution Worst Harmonic Distortion
Figure Distribution Worst Harmonic Distortion
REV.
AD8320
42MHz, 12dBm
ORDER INTERCEPT
POUT
18dBm GAIN
12dBm
65MHz 18dBm
DISTORTION
18dBm
42MHz 18dBm
65MHz, 12V, 12dBm TEMPERATURE
41.2 42.0 42.4 41.6 FREQUENCY 42.8
FREQUENCY
Figure Harmonic Distortion Temperature
Figure Two-Tone Intermodulation Distortion
Figure Third Order Intercept Frequency
GAIN
310mV GAIN 10MHz
GAIN
310mV GAIN 10MHz
22pF 100pF
150pF
20mV
12.5nsec
1.2V
12.5nsec
100k 100M FREQUENCY
Figure Transient Response
Figure Transient Response
Figure Response Various Capacitive Loads
GAIN
OUTPUT VOLTAGE Volts
GAIN 1MHz
22pF 100pF 150pF
GAIN 22pF 100pF
GAIN 1MHz
22pF 100pF 150pF
150pF
500mV
TIME Seconds
5nsec
100k 100M FREQUENCY
5nsec
Figure Transient Response Various Capacitive Loads
Figure Response Various Capacitive Loads
Figure Transient Response Various Capacitive Loads
REV.
AD8320
100mV
GAIN
VOUT
GAIN
1.25V
40MHz GAIN
VOUT
VOUT
DATEN
75nsec
250nsec
500mV
20nsec
Figure Power-Up/Power-Down Glitch
Figure Clock Feedthrough
Figure Overload Recovery
2.50V
40MHz GAIN
2.00V
12V, 40MHz GAIN
2.50V
12V, 40MHz GAIN .310V
VOUT
VOUT
VOUT
DATEN
20nsec
250mV
20nsec
20nsec
Figure Overload Recovery
Figure Output Settling Time Input Change
Figure Output Settling Time Gain Change
SUPPLY CURRENT
12V,
OUTPUT IMPEDANCE
INPUT IMPEDANCE
12V,
12V, 12V,
TEMPERATURE
100k
100M FREQUENCY
100k
FREQUENCY
100M
Figure Input Impedance Frequency
Figure Output Impedance Frequency
Figure Supply Current Temperature
REV.
AD8320
OPERATIONAL DESCRIPTION
AD8320 digitally controlled variable gain power amplifier that optimized driving cable. multifunctional bipolar device single silicon, incorporates analog features necessary accommodate reverse path (upstream) high speed MHz) cable data modem cable telephony requirements. AD8320 overall gain range (-10 capable greater than operation output signal levels exceeding dBm. Overall, when considering device's wide gain range, distortion, wide bandwidth variable load drive, device used many variable gain block applications. digitally programmable gain controlled three wire "SPI" compatible inputs. These inputs called SDATA (serial data input port), DATEN (data enable input port) (clock input port). Function Descriptions Functional Block diagram. AD8320 programmed 8-bit "attenuator" word. These eight bits determine programmable gain settings. attenuator core description below. gain linear V/V/LSB described following equation: 0.316 0.077 Code where code decimal equivalent 8-bit word. example, bits logic "1," decimal equivalent equals 19.95 gain scaling factor 0.077 V/V/LSB, with offset 0.316 (-10.0 dB). Figure shows linear gain versus decimal code Figure shows gain versus decimal code. Note nonlinearity that results when viewed versus code. step size increases attenuation increases (i.e., gain decreases) reaches maximum step size approximately (gain change between decimal).
GAIN
GAIN
LOG10 (0.316 0.077 CODE)
GAIN Code Decimal
Figure Gain Gain Control
attenuator core viewed eight binarily weighted (differential in-differential out) transconductance (gm) stages with phase" current outputs eight stages connected parallel their respective differential load resistors (not shown). core differential output signals also degrees phase equal amplitude. input stages likewise parallel, connected inverting input amplifier buffer outputs shown. Nine bits plus accuracy achieved gain settings over specified frequency, supply voltage temperature range. actual total core attenuation determined which combination binarily weighted stages selected data latch. With bits, levels attenuation programmed. This results attenuation range dB). gain equation above.
REFERENCE
AD8320
VOUT
0.316 0.077
CODE
VREF
INV.
ATTENUATOR CORE
REVERSE
POWER-UP
POWER-DOWN
BUF. DATA LATCH POWER- DOWN SWITCH INTER.
DATA SHIFT REGISTER
DATEN
SDATA
Figure Functional Block Diagram
GAIN Code Decimal
Figure Linear Gain Gain Control
AD8320 composed three analog functions powerup forward mode (Figure 42). input inverter/buffer amplifier provides single-ended differential output conversion. output signals nominally degrees phase equal amplitude with differential voltage gain dB). Maintaining close degrees equal amplitude required proper gain accuracy attenuator core over specified operating frequency. input buffer/inverter also provides equal voltages core inputs internal reference. This required ensure proper core linearity over full specified power supply range REV.
update AD8320 gain, following digital load sequence required. attenuation setting determined 8-bit word data latch. This 8-bit word serially loaded (MSB first) into shift register each rising edge clock. Figure During this data load time (T), DATEN data latch latched holding previous data word keeping attenuation level unchanged. After eight clock cycles data word fully loaded DATEN switched high. This enables data latch (becomes transparent) loaded register data passed attenuator with updated gain value. Also this DATEN transition, internal clock disabled, thus inhibiting serial input data.
AD8320
SDATA
VALID DATA WORD MSB. .LSB VALID DATA WORD
DATEN
CLOCK CYCLES
GAIN TRANSFER (G1) TOFF
GAIN TRANSFER (G2)
ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL
Figure Serial Interface Timing
power amplifier basic modes operation; forward power-up mode reverse power-down mode. power-up mode power amplifier stage enabled differential output core signal amplified With core attenuation range input gain, overall AD8320 gain range this mode, single-ended output signal maintains level VCC/2. This output level provides optimum large signal linearity allows coupling output necessary. output stage unique that maintains dynamic output impedance This allows direct cable connection results added load power versus using series back-termination resistor required with traditional output impedance amplifiers. power amplifier will also drive lower higher output loads, although device's gain (not gain range) will change accordingly (see Applications section). power-down mode power amplifier turned "reverse" amplifier (the inner triangle Figure enabled. During this transition, output power amplifier's input stage also disabled, resulting forward output signal (S21 although attenuator core input amplifier/ buffer signals affected (S11 function reverse amplifier maintain VCC/2 output port (VOUT) during power-down. This required minimize line reflections (S22 ensures proper filter operation forward mode device sharing same (i.e., multiplexed configuration). (See Applications section.) time domain, switches states, transitional glitch pedestal offset results. (See Figures 43.) powered down supply current drops versus (VCC power-up mode. Generally, using power-down input (PD) switching allows multiple devices multiplexed splitters (N-1 off, reduces overall total power consumption required cable data applications. cable telephony, power-down current generally needs much lower during
what referred sleep standby modes, supply switching PFETS equivalent, described applications section, would required.
APPLICATIONS
AD8320 primarily intended used return path (also called upstream path) line driver cable modem cable telephony applications. Data transmitted modulated either QPSK format. This done either dedicated QPSK/QAM modulator such AD9853. amplifier receives input signal either from dedicated QPSK/QAM modulator from DAC. both cases, signal must low-pass filtered before being applied line driving amplifier.
MODEM RECEIVE CIRCUITRY SUBSCRIBER CENTRAL OFFICE
DIPLEXER ORDER ELLIPTIC PASS FILTER
AD9853
AD8320
Figure Block Diagram Cable Modem's Upstream Driver Section
amplifier drives line through diplexer. insertion loss diplexer typically result, line driver must deliver power level roughly greater than required applicable cable modem standard that diplexer losses canceled out. Because distance central office varies from subscriber subscriber, signals from different subscribers will attenuated differing amounts. result, line driver required vary gain that signals arriving central office have same amplitude.
-10-
REV.
AD8320
Basic Connection
Figure shows basic schematic operating AD8320. Because amplifier operates from single supply, input signal must ac-coupled using capacitor. input bias level about This bias level available VREF (Pin used externally bias signals dc-coupling desired. Under conditions, decoupling capacitor must connected VREF pin. VREF voltage used externally, should buffered first. AD8320 (Pin input impedance Typically, video applications, termination favored. result, external shunt resistance (R1) ground required create overall input impedance termination required, 64.9 shunt resistor should used. Note, avoid loading pin, ac-coupling capacitor should placed between input shunt resistor shown Figure output side, VOUT also bias level. this case bias level midway between supply voltage ground. output signal must therefore ac-coupled before being applied load. bias voltage available VOCM (Pin used dc-coupled applications. This node must decoupled ground using capacitor. VOCM voltage used externally, should buffered. Since AD8320 dynamic output impedance external back termination resistor required. output signal being evaluated test equipment such spectrum analyzer, adapter (commonly called pad) should used maintain properly matched circuit.
Varying Gain
timing diagram AD8320's serial interface shown Figure write cycle device initiated falling edge DATEN. This followed eight clock pulses that clock control word. Because clock signal level triggered, data effectively clocked falling edge CLK. After control word been clocked DATEN line goes back high, allowing gain updated (this takes about ns). relationship between gain control word given equation: Gain (V/V) 0.077 Code 0.316 where code decimal equivalent gain control word 255). gain given equation: Gain (dB) log10 (0.077 Code 0.316) digital interface also contains asynchronous power-down mode. normally high line pulled time. This turns output signal after reduces quiescent current between (depending upon power supply voltage). this mode, programmed gain maintained.
Clock Line Feedthrough
Clock feedthrough results signal appearing superimposed output signal (see Figure 32). this impinges upon dynamic range application, clock signal should noncontinuous, i.e., should only turned eight cycles during programming.
Power Supply Decoupling
gain AD8320 varied over range from varying 8-bit gain setting word.
AD8320 should powered with good quality (i.e., noise) single supply between order achieve output power level (6.2 p-p) into
+12V
VOUT DIPLEXER
INPUT VREF
REFERENCE
AD8320
VOCM ATTENUATOR CORE
DATA LATCH POWERDOWN SWITCH INTER.
*FOR INPUT IMPEDANCE DATA SHIFT REGISTER DATEN
SDATA
SDATA DATEN
Figure Basic Connection
REV.
-11-
AD8320
supply voltage least required. achieve signal level (about p-p) into minimum supply level required. However, lowest possible distortion, power supply voltage should raised high possible. varying power supply from quiescent current increases from Careful attention must paid decoupling power supply pins. capacitor, located fairly close device, required provide good decoupling lower frequency signals. addition, five decoupling capacitors should located close each five power supply pins 20). capacitor must also connected labeled (Pin 14), provide decoupling internal node device. ground pins should connected impedance ground plane.
Alternative Power-Down Mode
HEXFET power MOSFET (International Rectifier part number IRLML5103) used turn current supply pins AD8320. Under normal operating conditions, gate (labeled POWER-DOWN) should grounded. Pulling gate within supply will open switch reduce current amplifier zero. cable modem cable telephony applications modem must always present output impedance line. This forces line driver always present impedance diplexer. this application, single pole double throw switch (AS103, Alpha Semiconductor) used switch external impedance when AD8320 turned off. This resistor then mimics dynamic output impedance AD8320. CMOS logic used drive voltages driving switch V2). Before AD8320 turned back again, gain needs known level. This done holding AD8320 after POWER-DOWN gone high. While held low, 8-bit serial data stream clocked into AD8320. During this time quiescent current will increase However, this time period small about this mode output settles about after rising edge Alternatively, DATEN held AD8320 powered device will power minimum gain. this mode, output settles after about Note that both cases, capacitor VOCM been reduced from 0.01 facilitate faster turn-on time. other capacitors circuit should connected shown Figure
previously mentioned, AD8320 into power sleep mode pulling low. lower power consumption required during power-down mode, alternative scheme used shown Figure
VCC+12V POWERDOWN
IRLML5103
VOUT
DATEN SDATA
VOUT VOCM AS103 (SEETEXT)
AD8320*
0.01
ADDITIONAL PINS DECOUPLING CAPACITORS OMITTED CLARITY 10-12V POWERDOWN 3-5V DATEN 3-5V
SDATA OUTPUT
97mA QUIESCENT CURRENT 32mA
97mA
Figure Alternative Power-Down Mode with Timing
-12-
REV.
AD8320
MODEM RECEIVE CHANNEL 58dBmV DIPLEXER +12V
11dBmV
AD603*
VPOS VOUT 20pF
AD8320*
61dBmV
FBDK 41dBmV VNEG COMM GNEG GPOS +0.5V
REFIN
AD7801*
AGND DGND LDAC D0-D7 D0-D7 DATA ENABLE
*ADDITIONAL PINS DECOUPLING CAPACITORS OMITTED CLARITY
74HCT164*
Figure Enhanced Dynamic Range Circuit
Enhanced Dynamic Range Application
AD8320 combined with AD603 give additional dynamic range shown Figure AD603 voltage controlled variable gain amplifier. gain AD603 determined difference voltage between GPOS GNEG pins. This differential voltage range this example, voltage GNEG tied +0.5 voltage GPOS varied from gain AD603 changes from with slope mV/dB (i.e., linear dB). gain control voltage supplied AD7801 DAC. output voltage +2.5 divided down range AD603 using resistor attenuator network. order that same gain control word used both AD603 AD8320, serial data stream converted parallel format AD7801 using serial-toparallel shift register. rising edge enable pulse simultaneously updates both amplifiers. control word varied from 00Dec 255Dec, gain signal chain varies from (there attenuation between AD603 AD8320). practice, this circuit usable lower gain range small input signal dBmV about p-p). Figure shows spectrum output signal frequency output level dBmV (3.1 p-p, gain). gain code transfer function amplifiers along with overall gain shown Figure overall gain transfer function combines linear transfer function with linear Volts/Volt transfer function. clear from Figure that overall gain transfer function considered approximately linear over range.
Figure Output Spectrum Enhanced Dynamic Range Circuit (Output Level dBmV, Frequency MHz)
AD8320/AD603
GAIN
AD8320
AD603 GAIN CONTROL WORD Decimal
Figure Gain Transfer Function Enhanced Dynamic Range Circuit
REV.
-13-
AD8320
Varying Gain Varying Load Impedance
already mentioned, AD8320 dynamic output impedance specified gain range assumes that output terminated with load impedance. Varying load impedance allows gain varied, maximum twice specified gain (for variation gain with load resistance shown Figure case gain control word 255Dec (i.e., gain).
tested demonstrate specified high speed performance device. Figure shows schematic evaluation board. silkscreen component side layer shown Figure layout board shown Figure Figure evaluation board package includes fully populated board with BNC-type connectors along with Windows®-based software controlling board from PC's printer port standard printer cable. prototyping area provided allow additional circuitry board. single supply ground board brought over this area available strips. There also extra strips available prototyping area which used additional power supplies. board should powered with good quality (i.e., noise) single supply between Extensive decoupling provided board. capacitor, located fairly close device, provides good decoupling lower frequency signals. addition, more importantly, five decoupling capacitors located close each five power supply pins 20).
GAIN
RLOAD
1000
10000
Controlling Evaluation Board from
Figure Gain RLOAD (Gain Control Word 255Dec)
gain described following equation:
RLOAD 0.316 0.077 Code RLOAD
where Code decimal equivalent 8-bit word.
Evaluation Board
layer evaluation board AD8320 available (part number AD8320-EB). This board been carefully laid
VREF INPUT VREF
evaluation board ships with Windows-based control software. standard printer cable used connect evaluation board PC's printer port (also called parallel port). cable length should kept less than about feet. wiring standard printer cable, with respect signal lines that used this application, shown Figure Although software controls evaluation board PC's parallel port, AD8320 digital interface serial. Three parallel port's eight bits (and digital ground line) used implement this serial interface. fourth used control pin.
VOUT OUTPUT
REFERENCE
AD8320
ATTENUATOR CORE DATA LATCH POWERDOWN SWITCH INTER VOCM
VOCM
DATA SHIFT REGISTER OPTIONAL 19-30, SDATA DATEN
36-PIN CENTRONICS CONNECTOR
Figure Evaluation Board Schematic
trademarks property their respective holders.
-14-
REV.
AD8320
control software requires Windows later operate. install software, insert disk labeled "Disk file called SETUP.EXE. Additional installation instructions will given on-screen. Before beginning installation, important close other Windows applications that running. When launch installed control software from Windows, will asked select printer port using. Most modern have only printer port, usually called LPT1. However, some laptop computers port. Figure shows main screen control software. Using slider, gain AD8320's range. gain displayed on-screen V/V. 8-bit gain setting byte also displayed, binary, hexadecimal decimal. Each time slider moved, software automatically sends latches required 8-bit data stream AD8320. power down reset device simply clicking appropriate buttons. software also offers volatile storage location that used store particular gain. This functions same memory pocket calculator.
Overshoot Printer Ports' Data Lines
data lines some printer ports have excessive overshoot. Overshoot used serial clock (Pin DSub-25 connector) cause communication problems. This overshoot eliminated applying mild filtering line evaluation board. This done putting small series resistor line, combined with capacitor ground. Pads provided (C9, component side evaluation board allow easy insertion these devices. Determining size these values will take some experimentation. Depending upon overshoot from printer port, this capacitor need large 0.01 while resistor typically range.
Figure Evaluation Board Silkscreen (Component Side)
REV.
-15-
AD8320
Figure Evaluation Board Layout (Component Side)
-16-
REV.
AD8320
Figure Evaluation Board Layout (Solder Side)
CENTRONICS
D-SUB (MALE) DATEN
SDATA
SIGNAL DATEN DATA DGND EVALUATION BOARD
D-SUB-25
36-PIN CENTRONICS 19-30,
Figure Interconnection Between AD8320EB Printer Port
REV.
-17-
AD8320
Figure Screen Display Windows-Based Control Software
-18-
REV.
AD8320
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
20-Lead Thermally Enhanced Power Small Outline Package (RP-20)
0.5118 (13.00) 0.4961 (12.60)
0.2992 (7.60) 0.2914 (7.40)
HEAT SINK
0.1890 (4.80) 0.4193 (10.65) 0.1791 (4.55) 0.3937 (10.00)
0.3340 (8.61) 0.3287 (8.35) 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0500 (1.27) 0.0040 (0.10) STANDOFF 0.0201 (0.51) SEATING 0.0500 (1.27) 0.0130 (0.33) PLANE 0.0057 (0.40) 0.0295 (0.75) 0.0098 (0.25)
REV.
-19-
-20-
C3167-8-1/98
PRINTED U.S.A.

Serial Digital Controlled Variable Gain Line Driver AD8320 REFERE

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