Radiation Tolerant SRAM SPACE Applications purpose this document

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ANM052
Radiation Tolerant SRAM SPACE Applications
purpose this document analyze selection criteria memory chips used Spacecraft computers. general trend implement more autonomous functions Spacecraft, making increased processor performances, requiring larger embedded flight software sizes larger storage board. This note provides introduction current organization European Spacecraft On-Board Data Handling systems identifies criticality Spacecraft computer based functions. recalls constraints memory planes linked Space environments, gives examples memory banks designs typical sizes. order introduce context Space projects, following figure represents logic flow diagram typical Phase /Phase Spacecraft, where most important trade-offs term Data Handling architecture components selection have performed. Both Hardware Software activities represented, strong interaction both designs necessary achieve most appropriate processing system. Design current Spacecraft board data handling subsystems. Starting from approved mission concept, Spacecraft designed meet number operational environmental constraints. preliminary On-Board Data Handling architecture defined, based experience gained industry, with parallel allocation hardware software functions. This phase work relies existing hardware, re-utilization standard functions typical software figures. software functions then detailed size more precisely necessary resources fulfil Spacecraft mission, interactive work subsystem level necessary match hardware software functions. Spacecraft design then reviewed system level check that will meet mission objectives, especially taking into account Space environment. Issues then identified (mass, reliability, thermal aspects.) corrective actions taken necessary each equipment subsystem. that concern banks, they have particular importance system level, since they contain most flight software functions. Single event upsets have been identified since early corrective hardware methods have been implemented avoid catastrophic effects. main effect remains some degradation Spacecraft availability, whose impacts mission have assessed. summarize, steps selection process memories Space applications, are: PRELIMINARY ARCHITECTURE SIZING COMPUTER RESOURCES ANALYSIS EFFECTS MISSION HARDENING STRATEGY
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MISSION INDUSTRY SPACECRAFT FUNCTIONS PROCESSING ARCHITECTURE Existing HARDWARE AVAILABLE COMPONENTS MARGINS RELIABILITY AVAILABILITY COMPUTER Function Allocation Preliminary SOFTWARE definition SOFTWARE functions FAULT Estimate COMPUTING POWER Estimate RAM/ROM SIZES Input Micro- Output processor memory memory Preliminary HARDWARE definition Estimate total RAM/ROM SIZES Estimate total COMPUTING POWER MISSION Impacts Microprocessor frequency ANALYSIS HARDENING STRATEGY DIMENSIONS SELECTION SOLUTION COST IMPACTS POWER Theoretical MICRO UPSET RATES Theoretical UPSET RATES HARDWARE SOFTWARE UPDATES
ORBIT PARAMETERS
ENVIRONMENT
REPRESENTATION MEMORY TRADE LOGIC DURING SPACECRAFT PHASE PHASE
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following figure shows most general architecture European Spacecraft:
GROUND CCSDS/PUS Communication Standards
Central Terminal Unit
OBDH
Intelligent Control Unit Remote Terminal Unit
MACS
1553
Central Terminal Unit interfaces with Telecommunication subsystem drives Spacecraft which terminals computers (ICU Intelligent Computer Units dedicated management instrument Spacecraft Attitude Orbit Control) acquisition Units (such RTU, remote Terminal Units). certain level standardization been achieved data transfer on-board between Ground Flight segments. On-Board, data transfer buses mainly On-Board Data Handling (OBDH) standard 1553 bus. specific Attitude Orbit Control subsystems (MACS bus) also used.
Communication systems spacecraft follow recommendations CCSDS (Consultative Committee Space Data Systems). This ensures certain level inter-operability between main International Space Organizations. This architecture considered stable, with number Space qualified ASICs supporting protocols. allocations functions Spacecraft also almost standardized.
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functions generally split according following hierarchy: Table
Location
Spacecraft
Type Computer
Central Computer
Typical Functions
Ground-Board interface Operational sequences storage execution Telemetry storage during visibility periods Interface with Central Computer Spacecraft Manoeuvres execution attitude control laws AOCS monitoring re-configuration Survival/safety mode attitude Interface with Central Computer Payload operational sequences storage execution Payload monitoring Scientific Telemetry storage Signal image processing Data compression Instrument equipment activation positioning control loops
Attitude Orbit Control Subsystem Computer
Payload
Paymoad Controller
Instrument processors
general trend, data storage becomes more decentralized, especially Payload controllers, change Telemetry system organization. previous systems, bandwidth allocation used fixed, telemetry system based cyclic acquisition scheme within Spacecraft. Table
Location
Spacecraft
Packet Telemetry systems nowadays allow dynamic bandwidth allocation, which implies storage requirements computers generating source packets. general trend European Spacecraft, availability Space qualified component Europe should show following type computers.
Type Computer
Central Computer
Typical Components
Processor 1750 (MAS 281, 31750.) Memory Kbytes Processor 1750 (MAS 281, 31750.) Memory Kbytes Processor 1750 (MAS 281, 31750.) Memory Kbytes Digital Signal Processors Motorola 68xxx
Attitude Orbit Control Subsystem Computer Payload Payload Computer
Instrument processors
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typical example such Spacecraft satellite, whose Data Handling Architecture should close following one: These current data, predict RISCs re-entry vehicles well Digital Signal Table
Microprocessor type
microcontroller microprocessor RISC
Processors Guidance, Navigation Control associated with image processing. following computer configurations considered typical space applications:
Selected chip
TEMIC-MHS 80C32 31750 TEMIC-MHS TSC691E
Memory size Kbytes
1024
what concerns memory type selection, designer select Hard SRAMs radiation tolerant SRAMs which available market.
following diagram represents availability various technologies, along several years.
Memory integration Technology SRAM
256K
SRAM
256K
SRAM
256K
Time
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OPTICAL MONITOR REFLECTION GRATING SPECTROMETER MACS Optical Monitor 1750 Kword 31750 Kword Kword 31750 Kword Kword AOCS Payload DATA UNIT DATA UNIT Service Module OBDH 1750 Kword Kword EPIC Data Handling Unit EPIC Data Handling Unit 1750 Kword Kword EDHU 1750 Kword Kword EDHU 1750 Kword Kword CONTROLLER 68000 Kword Kword CONTROLLER 68000 Kword Kword CONTROLLER 68000 Kword Kword EUROPEAN PHOTON IMAGING CAMERA RADIATION MONITOR POSSIBLE BOARD DATA HANDLING CONFIGURATION SPACECRAFT
DIGITAL PROCESSOR UNIT 56001+local RAM+ Program memory Megabytes SRAM
CENTRAL UNIT
1750 Kword Kword
ATTITUDE CONTROL UNIT 1750 Kword Kword
MACS
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1.1. Analysis single event upsets effects mission
Single event upsets cause malfunctions several sensitive functions: microprocessors affected flips microprocessor registers, with immediate effects during execution instruction. Memory flips programme code have similar effects. flips data area have effects longer term automatic detection correction performed. Table
Function
Instrument processors
flips Input/Output registers corrupt address data transmitted messages, which normally detected during protocol verifications. terms criticality, service interruption Spacecraft computers described follows, according computer class.
Effects
critical interruption instrument operation loss mission data critical interruption major instrument several instruments loss mission data Highly critical loss nominal AOCS possible loss Spacecraft safe mode
Corrective action
Reconfiguration processor possible need instrument recalibrations Reconfiguration processor
Prevention design
Protection EDAC programme code area recommended
Payload processor
watchdog protection EDAC programme data area recommended watchdog Software ROM, dumped executed with EDAC Hardware survival logic backup watchdog protection EDAC programme data area
AOCS processor
Interruption mission possible automatic protection sensitive instruments Interruption mission operations
Central processor
Critical interruption mission need enter safety mode
now, Spacecraft design have been efficient enough limit effects mission interruptions only. flips occurring microprocessors code create immediate crashes, which generally detected hardware watchdogs. There additional feature required SEU, since this function implemented monitor both hardware software behavior. watchdog effect generally computer restart. order avoid complete software reloading, flight software code often resident ROM, copied execution. This implementation offers advantage allowing executable code modifications during mission. implementation choice between Hard chips Radiation Tolerant components associated Error Detection Correction devices (EDACs) depends
several criteria which have weighted according each mission context. following criteria identified:
Reliability Mass Size Power consumption Speed Sensitivity heavy Error detection capability Availability Cost
following chapter details technical design aspects, which allow establish comparison these criteria between three implementations typical microcontroller microprocessor applications (from Kbytes memory size).
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1.2. Solution
embedded computer applications where high reliability autonomy indispensable, protection memory contents paramount importance. Such protection achieved using Error Detection Correction (EDAC) circuitry hardware design. EDACs integrated circuits connected data bus. characteristics EDAC detect correct single errors, detect double errors (present same data word) this expense called check bits added each data word minimum additional processing. TEMIC Static design separates cells that represent different dataword bits. This feature virtually eliminates risk impact provoke dual upsets, leaving only minute risk single upsets error that detected corrected EDAC.
Figure TEMIC Static Design
bytes
cells bits byte impact here does upset these cells
additional processing associated with EDAC protected solution initialization checkbit refresh procedure that performs read-write operations protected memory ("scrubbing"). initialization checkbit does introduce overhead since most spaceborne applications move their code from reset, automatically
initialize check same time. scrubbing performed during processor idle time necessary eliminate risk separate impacts generate dual upset same dataword. However, dual upset same data word should occur would still detected signalled EDAC.
1.3. EDAC System Configurations
"Correct-Always" system data passes through EDAC, where check bits generated each write operation read data always corrected. reduce additional amount circuitry necessary implement this type system, flow-through EDAC (separate data buses RAM) should selected.
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Figure "Correct-Always" system with flow-through EDAC
Address Address
Data
Flow Through EDAC
Check Bits
CHECKBIT
CODE DATA
Data Address
Read/Write/Control
"Bus-Watch" system write data EDAC, where check bits generated. Read data always checked EDAC, data errors signalled CPU. Flow-through EDACs well Figure "Bus-Watch" system
regular EDACs suitable this type system. address with error syndrome should latched allow correction.
Address
Check Bits Interrupt Waitstate EDAC Data
CHECKBIT CODE DATA
latch
Data Read/Write/Control
"Bus-Watch" system suitable very fast systems, implies more overhead error handling hardware software. With respect processor speeds used spaceborne systems, propagation delay
flow-through EDACs fast enough therefore "Correct-Always" solution been used examples below.
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1.4. Microcontroller Application
systems, error correction schemes become relatively expensive with respect check bits that have added virtually twice normal memory required. This example uses TEMIC 80C32, capable speeds MHz, together with TEMIC EDAC RAMs including bits additional Check RAM. timing diagram shows External Code Memory Read cycle (fetch) which more critical than Data memory read write cycles.
Table Power board space consumption protection application Kbytes)
Type Component
EDAC SMKS-29C516E SRAM 32Kx8RT SMDP-65656FV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 128Kx8RT: SMDI-65608EV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 32Kx8RH: Total Hard solution
Part count
Flatpack size (mm2)
1122 2046
ICCOP iccsb1 (mA)
0.02 0.02
RAMs operation, standby. EDAC RAMs operation. EDAC taking into account space board design rules
Figure TEMIC 80C32E with TEMIC 29C516E SMDP-65656FV-45 (Instr.Read)
tLLPL=25ns PSEN tLLIV<100ns Latched Address tGLQV=20ns tPLIV<65ns
EDAC16 Data
tLLPL 80C32E PSEN 0.20.53 tPLIV 80C32E PSEN valid instruction available tLLIV 80C32E valid instruction available tGLQV Output Enable Access time
t4=34ns
Dout
Corrected Data Read Interval
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1.5. Application with microprocessor 64kWords
example this application built around space qualified MA31750 microprocessor MHz, TEMIC-MHS EDAC RAMs including bits additional Check RAM.
Table Power board space consumption protection application KWords KBytes)
Type Component Part count
Flatpack size (mm2)
1502 1022 2888
ICCOP ICCSB1 (mA)
0.02 0.02 0.02
ICCOP ICCSB1 (mA)
0.02 0.02 0.02
EDAC: SMKS-29C516E SRAM 32Kx8RT: SMDP-65656FV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 128Kx8RT: SMDI-65608EV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 32Kx8RH: Total Hard solution
Three RAMs operation, three standby. EDAC Three RAMs operation. EDAC taking into account space board design rules
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1.6. wait state limits clock
Figure MA31750 9MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Read, wait state)
A0-A15
RD/WN Dout
tGLQV=20ns
t4=34ns
EDAC-16 Data MA31750 data valid required
Corrected Data
tGLQV Output Enable Access time EDAC "RAM data "user data out" propagation time
Figure MA31750 9MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Write, wait state)
A0-A15 t12=15ns
RD/WN EDAC Data Checkbits
t22=19ns
31750 data low.Z
t12+ 31750 data valid
EDAC write enable data active EDAC data active checkbits valid tDVWH data setup time
MA31750 D[0.16]
t12+=45ns
t3=26ns
tDVWH>20ns Write Interval w.s)
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Read Interval w.s)
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21.7. clock speed requires wait state
Timing analysis shows that wait state must inserted each memory access cycle with TEMIC-MHS RAMs H-65656FV-45. increase execution time wait state memory access cycle estimated order
Figure MA31750 16MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Read, wait state)
A0-A15
RD/WN tGLQV=20ns Dout
t4=34ns
EDAC-16 Data MA31750 data valid required
Corrected Data
tGLQV Output Enable Access time EDAC "RAM data "user data out" propagation time
Read Interval w.s)
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Read Interval w.s)
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Figure MA31750 16MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Write, wait state)
A0-A15 t12=15ns MA31750 D[0.16] RD/WN EDAC Data Checkbits
t12+=45ns
t22=19ns
t3=26ns
tDVWH>20ns Read Interval w.s)
31750 data low.Z t12+ 31750 data valid EDAC write enable data active
Read Interval w.s)
EDAC data active checkbits valid tDVWH data setup time
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1.8. Application with microprocessor extended memory
example this application built around space qualified MA31750 microprocessor MA31751 memory management unit (MMU) MHz, TEMIC-MHS EDAC TEMIC-MHS RAMs including 128Kx6 bits additional Check RAM.
Table Power board space consumption protection application (128 KWords KBytes)
Type Component
EDAC: SMKS-29C516E SRAM 32Kx8RT: SMDP-65656FV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 128Kx8RT: SMDI-65608EV-45 Total TEMIC-MHS solution EDAC: SMKS-29C516E SRAM 32Kx8RH: (45ns)
Part count
Flatpack size (mm2)
2642 1022 5414
-ICCOP ICCSB1 (mA)
0.02 0.02 0.02
Total Hard solution
Three RAMs operation, nine standby. EDAC Three RAMs operation. EDAC taking into account space board design rules
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1.9. clock requires wait states
clock speed, requires wait state write cycle wait states read cycle. increase execution time wait states estimated order 20%.
Figure MA31750/51 16MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Read, wait states)
A0-A15
RD/WN Dout
tAVQV=45ns
t4=34ns
EDAC Data MA31750 data valid required
Corrected Data
tAVQV Address Access time
Read Interval w.s)
Read Interval w.s)
EDAC "RAM data "user data out" propagation time
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Read Interval w.s)
ANM052
Figure MA31750 16MHz with TEMIC-MHS 29C516E SMDP-65656FV-45 (Write, wait states)
A0-A15
t12=15ns MA31750 D[0.16] RD/WN
t12+=45ns
tAVWH (1w.s.)>40ns tAVWH (2w.s.)>20ns
t22=19ns EDAC Data Checkbits
31750 data low.Z
t3=26ns
tDVWH (1w.s.)>20ns tAVWH (2w.s.)>20ns Read Interval w.s) Read Interval w.s)
t12+ 31750 data valid EDAC write enable data active EDAC data active checkbits valid tAVWH address setup time tDVWH data setup time
Read Interval w.s)
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1.10. Examples flip predictions typical computers
Theoretical flips memory plane based Kbits memory chips (M-65656F) following shielding RD10 attached annexes). Table
Orbit type flip prediction Heavy Ions
E-11
flip prediction Protons
4.9E-7
Total flip prediction
Earth Orbit Polar Orbit Deep Space Geostationary Orbit
Table Recalling computers detailed this document
Computer
Microprocessor type
microcontroller microprocessor
Selected chip
TEMIC 80C32 31750
Memory size Kbytes
flips probability considered follows inactive powered chips: Table
Computer Memory size Kilobits
2048
Polar orbit
days hours
Geosynchronous Orbit
days hours
12.2 days days
Those figures inactive chips, correspond probability mission interruptions absence corrective design. Earth Orbit missions which cross South Atlantic Anomalia (SAA), M-65656F used such need protection actually needed. applications Earth, Polar Geo-synchronous orbits, protective devices necessary limit impact spacecraft mission. EDAC correction device added, necessary memory size increased correction code implementation, EDAC activation probability increased.
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probability given hereunder Table
Computer Memory size Kilobits
2816
days days
Polar orbit
days hours
Geosynchronous Orbit
days hours
terms occurrence, there major difference, corrective design based memory scrubbing performed with slightly higher frequency.
1.11. Conclusion
previous analysis allows conclude that M-65656F used Space applications. most current applications earth Orbit, Polar Orbit Geo-synchronous Orbit, 31750 using KWords memory), TEMIC SRAM (M-65656F M-65608E) with EDAC (29C516E) appears valid solution from system point view, expense additional wait state. processing unit power happened actually issue early state project, should consider that system problem does exist, which likely solved level memory chip selection. microcontrollers polar Orbit Geo-synchronous Orbit, using EDAC means practically double memory size, which might have significant impact design. such applications, which critical, parts costs availability have considered.
1.12. Reference documents
This application note based study done THARSYS 1994. (RD1) (RD2) (RD3) (RD4) (RD5) (RD6) (RD7) (RD8) (RD9) (RD10) High Reliability Products, Military Aerospace Components Data Book, TEMIC Microcontrollers, Data Book, TEMIC, 1997 80C32/80C52, Data Sheet, TEMIC Radiation Hard, Hi-Rel ASIC Handbook, Plessey Semiconductor, 1993 Bits EDAC, Product Specification, Saab Ericsson Space, 1993 Detect/Correct Errors improve data reliability, Hegde (IDT),Electronic Design, 11/6/1992 Designing with IDT49C460 IDT39C60 Error Detection Correction Units, Application Note AN-24, Integrated Device Technology, Inc., 1989 High Performance Logic, Data Book, Integrated Device Technology, Inc., 1992 Radiation Hardened 32kx8 CMOS Static RAM, Data Sheet, Harris Semiconductor, 12/1992 Evaluation Heavy Ions Protons induced upset rates HM-65664E M-65656F TEMIC Matra static RAMs (HIREX Technical Note, HRX/93.276, 26/11/93).
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