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Analog Mixed-Signal Products
Analog Applications Journal
Fourth Quarter, 2003
Copyright 2003 Texas Instruments
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements.
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Contents
Introduction Data Acquisition
ADS82x with non-uniform sampling clock
growing number applications require ADCs operate from sampling clock with variable frequency, phase, duty cycle. This article shows that TI's ADS82x operate very well with non-uniform sampling clock.
Calculating noise figure third-order intercept ADCs
Noise figure (NF) third-order intercept point (IP3) common specifications analog-todigital converters (ADCs). This article shows calculate ADCs using known specifications signal-to-noise ratio; two-tone, third-order intermodulation distortion (IMD3); signal level input.
Evaluation criteria ADSL analog front end.
This article describes several important ADSL analog front evaluation criteria design limitation factors, including relationship between total signal-to-noise ratio transmission data speed; loop attenuation variation with discrete multitone signal frequency influence reach; echo return loss hybrid circuit; impact multitone power ratio.
Power Management
UCC28517 100-W power converter with 12-V, bias supply, Part
conclude review UCC28517 supply, this article covers design second 12-V, power stage used auxiliary bias supply.
Amplifiers: Amps
attenuators
Using attenuator produce unexpected results when standard inverting configuration used. This article describes methods improving stability when precision attenuation needed.
Calculating noise figure amps
Noise figure traditionally been used specification amps. Manufacturers long adopted input-referred voltage current noise. This article shows calculate noise figure amps using circuit configuration input-referred noise specifications. calculations detailed inverting non-inverting single-ended amplifiers fully differential amplifiers.
Index Articles Worldwide Technical Support
view past issues Analog Applications Journal, visit site www.ti.com/sc/analogapps
Analog Applications Journal 2003 www.ti.com/sc/analogapps Analog Mixed-Signal Products
Introduction
Introduction
Analog Applications Journal collection analog application articles designed give readers basic understanding products provide simple practical examples typical applications. Written only design engineers also engineering managers, technicians, system designers marketing sales personnel, book emphasizes general application concepts over lengthy mathematical analyses. These applications intended "how-to" instructions specific circuits examples devices could used solve specific design requirements. Readers will find tutorial information well practical engineering solutions components from following categories: Data Acquisition Power Management Amplifiers: Amps Where applicable, readers will also find software routines program structures. Finally, Analog Applications Journal includes helpful hints rules thumb guide readers preparing their design.
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Data Acquisition
ADS82x with non-uniform sampling clock
Hui-Qing (Email: liu_hui-qing@ti.com)
Applications Engineer, High-Speed Products
Introduction
Texas Instruments (TI) high-speed analog-to-digital converter (ADC) ADS82x family includes ADS825/822, ADS826/823, ADS828. These ADCs have 10-bit resolution with maximum sampling speed MHz, respectively. They widely used communications, video digitizing, test equipment, imaging, medical ultrasound imaging. some applications ADCs driven continuous sampling clock with constant frequency. However, other applications such medical ultrasound imaging where ADCs parallel with interleaved configuration, they must operate with sampling clock that
Figure ADS82x bench test system
HP8644 DG2020 HP8131A Output Analog Test Input Data Capture Clock ADS826 Sampling Clock Output
variable frequency, phase, duty cycle. other words, these ADCs must operate with non-uniform sampling clock. TI's ADS82x handle this? bench test shown good results, answer yes. This article presents measurement system fast Fourier transform (FFT) analysis method used along with test results only ADS826 EVM. However, these test results applicable other ADCs ADS82x family, since these ADCs have pipeline architecture designed with same basic features, such 10-bit resolution, internal external reference, single-ended differential analog input, input range selection, single power supply, power-down mode, power dissipation, three-state output, CMOS- TTL-output compatibility.
Test system
TLA714
10-bit
HP8644
Figure Pattern clocks ADS826 test
Sampling Clock
Sampling Clock
ADS826 bench test system includes pulse generator (HP8131A), data generator (DG2020), waveform generator (HP8644), Tektronix logic analyzer (TLA714) (see Figure This system used generate analog signal, pattern clock, data capture clock. analog signal, sine wave that varied frequency amplitude, input test signal ADS826; pattern clock, which varied frequency, phase, duty cycle, sampling clock ADS826. data capture clock flexible with proper frequency duty cycle TLA714 capture data from ADS826 perform analysis. clock source phase locked with test signal source 10-MHz reference output HP8644, signals generated from system synchronized. HP8131A used calibrate DG2020.
Pattern clocks
Sampling Clock
Three different pattern clocks, plotted Figure generated from this system. They used test non-uniform sampling performance
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ADS826. Sampling Clock (Case uniform clock with frequency duty cycle 50%. Sampling Clock (Case non-uniform clock with frequency (varied cycle cycle) alternating from with duty cycle 33.3 with 66.7% duty cycle. Sampling Clock (Case non-uniform clock with frequency varying (cycle cycle) from with duty cycle with duty cycle. These clocks simulated from real applications.
Data measurement analysis
TLA714 used collect output data from ADS826, performance device evaluated using analysis. this approach, sampling clock ADS826 input clock TLA714 need synchronized with analog input test signal. When signal synchronized, data ready measured. beginning, analog sine wave sampled ADS826 rising edge sampling clock, sample converted into digital form pipeline stage. Five sampling clocks later, digital number (straight offset binary code) sample output data ADS826 with additional small-signal propagation. digital data sent data ADS826 rising edge input sampling clock. stays clock period then updated next rising edge input sampling clock sample data. When data valid data bus, captured logic analyzer with synchronized clock. data then processed analyzed using analysis. three different sampling cases mentioned earlier evaluated here. Case sampling clock frequency ADS826 constant MHz; Case sampling clock frequency ADS826 constant regularly varied cycle-by-cycle basis; Case sampling clock period ADS826 regularly varied Sampling Clocks non-uniform sampling clocks, their phases change with time. This clearly demonstrated Sampling Clock where clock phase delayed after each 50-MHz clock cycles. Such sampling phase variation apparent
ADS826 input/output configuration
single-ended analog input circuit used this test shown Figure Here OPA642 with inverting gain used. This circuit mainly provides conditions ADS826. ac-coupled signal path with power amplifier with proper gain driving capability; another common-mode voltage ADS826 analog input bias. ADS826 configured with internal reference full-scale input range Vp-p. common-mode (CM) used here except bypassing. Based configuration, 2-Vp-p analog sine wave applied +IN, 2.35-V common-mode voltage added both ADS826 analog input. This common-mode voltage generated REFT, REFB, external power supply through balanced resistor network. input clock ADS826 from DG2020 three sampling clocks mentioned earlier. digital output ADS826 connected TLA714 through data driver such TI's SN74x family. digital configuration ADS826 straightforward therefore shown Figure Details about ADS826 digital output circuit found Reference
Figure Single-ended input circuit ADS826 bench test
OPA642
RSEL INT/EXT
1.62 1.62
REFB 1.62
1.62
REFT
ADS826
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Data Acquisition
from output data ADS826. Case ADS826 samples analog sine wave constantly outputs digitized samples MSPS. Cases analog sine wave sampled ADS826 variable speed that digitized samples sent non-uniform time intervals. This shown Figures 4-6. Further analysis non-uniform sampling performance ADS826 presented later under "Test results." Does ADS826 operate well with non-uniform sampling clock
Figure Non-uniform sampling time intervals
Input Sine Wave
Sampling Clock
Figure ADS826 non-uniform sampling performance analysis Case
Input Sine Wave
Sampling Clock Pipeline Delay Output
Clock MHz) Clock MHz)
Figure ADS826 non-uniform sampling performance analysis Case
Input Sine Wave Sampling Clock Pipeline Delay Output Data
Clock (7.14 MHz) Clock (7.14 MHz)
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does with uniform sampling clock? Yes, this explained downsampling technique analysis. analysis, sample size kept 4096; sampling frequency kept more than five times higher than signal frequency three cases. Case with Sampling Clock output data ADS826 used directly input because uniform samples; result specification data sheet. Cases with non-uniform sampling clock, output data ADS826 cannot used directly input non-uniform samples. perform analysis Cases need find uniform samples from non-uniform sampling data. implementation this idea shown Figure where ADS826 samples analog sine wave rising edge Sampling Clock sample locations sine wave have non-uniform time intervals. With downsampling techniques, however, these locations classified into uniform time-interval sets. example, using 50-MHz clock uniform time reference, find data (A1, A3.) data (B1, B3.) which data uniformly spaced. Furthermore, data results from fast-sampling Clock MHz), data results from slow-sampling Clock (33.3 MHz). data each uniformly time-spaced 10-MSPS sampling frequency, which downsamples original data. This frequency
Figure SFDR ADS826 with uniform non-uniform sampling clocks
Input Signal Frequency (MHz)
used clock frequency logic analyzer that used extract data from data ADS826. completed data acquisition from ADS826 with non-uniform sampling clock shown Figure where sample sine wave collected ADS826 rising edge input clock output after period five input clocks. input clock consists fast slow clocks, while ADS826 output data consists long short periods. Because five-clock delay, sample from fast input clock appears output data long period, sample from slow input clock appears output data short period. analysis, Clock MHz) used capture data while Clock with 20-ns clock delay) used capture data output results data sets represent dynamic performance ADS826 with non-uniform Sampling Clock shown later under "Test results." same principle applied Case which shown Figure this case frequency Clocks 7.14 MHz. With different sampling clock pattern, downsampling clock frequency will vary difficult determine. test results show that ADS826 functions well with non-uniform sampling clock long clock high pulse width least half period highest sampling clock specified data sheet; example, pulse width least ADS826 (maximum speed MHz). sampling clock speed also meet minimum limit data sheet.
Test results
Series 50-MHz sampling clock Series Data Case Series Data Case Series Data Case Series Data Case
Input analog signal frequencies three cases were tested, results shown Table Figure Table shows that there change signal-to-noise ratio (SNR) whether ADS826 driven uniform non-uniform sampling clock. Figure shows that there also significant difference spurious-free dynamic range (SFDR) performance between uniform non-uniform sampling. addition,
Table (dBFS) ADS826
SAMPLING CLOCK (MHz) Case Case Case (uniform) 33.3 mixed (non-uniform) 33.3 mixed (non-uniform) mixed (non-uniform) mixed (non-uniform) CLOCK (MHz) (FFT Clock (FFT Clock 7.14 (FFT Clock 7.14 (FFT Clock 1-MHz Signal Frequency (dBFS) 5-MHz 10-MHz Signal Signal Frequency Frequency 30-MHz Signal Frequency
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SFDR (dBFS)
Data Acquisition
Magnitude (dBFS)
non-uniform sampling, SFDR increases when sampling clock input signal amplitude decreases. test result shown Figures 8-10. Figure shows output Case performance ADS826 with 50-MHz sampling clock 1-MHz input sine wave maximum amplitude. dBFS, SFDR dBFS. output Case shown Figure which non-uniform samples downsampled 10-MHz clock. Figure shows output data Figure shows output data dBFS both data sets SFDR dBFS data dBFS data output Case shown Figure which non-uniform samples downsampled 7.143-MHz clock. dBFS both data sets SFDR dBFS data dBFS data
Figure output with 50-MHz uniform sampling (Case
Magnitude (dBFS)
-100 -120 Frequency (MHz)
Figure Case outputs with 10-MHz downsampling frequency
-100 -120 Frequency (MHz)
Conclusion
test results presented this article strongly support non-uniform sampling applications ADS82x family. test results show that same achieved with both uniform nonuniform sampling using ADS826. Good SFDR also achieved with both uniform non-uniform sampling. test data analysis conclude that ADS826 functions well with non-uniform sampling clock long clock high pulse width least half period highest sampling clock specified data sheet. test result proves that ADS82x family very stable solid bits resolution both uniform non-uniform highspeed sampling converting operations, making appropriate wide future applications.
Data
Magnitude (dBFS)
-100 -120 Frequency (MHz)
Data
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Data Acquisition
Figure Case outputs with 7.14-MHz downsampling frequency
Magnitude (dBFS)
-100 -120
Frequency (MHz)
Data
Magnitude (dBFS)
-100 -120
Frequency (MHz)
Data
References
more information related this article, download Acrobat Reader file www-s.ti.com/sc/techlit/ litnumber replace "litnumber" with Lit. materials listed below. Document Title Lit. "DEM-ADS82xE Evaluation Fixture," User Guide .sbau036 "10-Bit, 60MHz Sampling Analog-to-Digital Converter," Data Sheet .sbas070 Alan Oppenheim Ronald Schafer, Discrete-Time Signal Processing (Prentice-Hall, Inc., 1989).
Acknowledgments
Special thanks Bryan McKay Rosie Loaiza their support test board Stephan Baier article review.
Related sites
analog.ti.com www.ti.com/sc/device/partnumber Replace partnumber with ADS822, ADS823, ADS825, ADS826, ADS828 OPA642
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Data Acquisition
Calculating noise figure third-order intercept ADCs
James Karki (Email: j-karki@ti.com)
Member, Group Technical Staff, High-Performance Linear
Introduction
Figure ADS5410 spectral plot from Reference
Noise figure (NF) third-order intercept point (IP3) used radio receiver link budget analysis means quantify effects device noise nonlinearity sensitivity radio. Analog-to-digital converters (ADCs) used radio receivers convert signal from analog domain digital domain. typically -100 specified device, equiva-120 lent parameters given whereby they calculated. ADCs specify signal-to-noise ratio (SNR) two-tone, third-order intermodulation distortion (IMD3) under certain input signal clocking conditions. With this information, calculated. general, high desired. actual values required meet design goals depend architecture system.
Amplitude (dB)
MSPS 63.96 SINAD 63.3 SFDR 75.83 71.78
Frequency, (MHz)
ADCs
There couple ways about calculating input noise spectral density ADC, using specification easy. measure SNR, low-noise signal input ADC, output examined taking fast Fourier transform (FFT) spectral plot. Figure shows such plot from Reference ratio signal noise integrated over half sampling frequency (fS/2) SNR. Since noise is-to first-order approximation-independent signal level, higher input level better SNR, point. signal approaches full scale (FS), spurious behavior begins degrade SNR. input signal level below fullscale input dBFS) seems give good results commonly used. find input noise spectral density, divide signal level divided half sampling frequency (since calculated dividing signal noise integrated over fS/2): (dBm/Hz) dBFS (dBm) (dBc) fS/2 (dBHz). voltage-driven device, must choose input resistance find signal power with formula V2/R. Assuming that 2Vp-p full-scale input dBm. example calculate, consider following ADS5410, 12-bit ADC. Given that MSPS, 2Vp-p, 63.96, then (dBm/Hz) 63.96 76.02 dBHz -130.98 dBm/Hz.
Review noise figure
Noise figure (NF) decibel equivalent noise factor (F): (dB) 10log(F). Noise factor device power ratio input (SNRI) divided output (SNRO): SNRI SNRO
output signal (SO) equal input signal (SI) times gain: output noise equal noise delivered input (NI) from source plus input noise device (NA) times gain: Substituting into Equation simplifying, SNRO SNRI
Assuming that input terminated same impedance source, -174 dBm/Hz, where Boltzman's constant Kelvin). Once find input noise spectral density device, simple matter plug into Equation calculate
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Equation need linear equivalents -130.98 20045, (dB) 43.02 Looking result, that adding Equation makes very little difference since noise figure high. Therefore, using (dB) (dBm/Hz) (dBm/Hz) introduces little error. common practice transformer fully differential drive high-performance ADCs differentially. This gives opportunity higher input resistance. calculated based reduced log10(impedance ratio). example, impedance ratio (1:2 turns ratio) transformer, input resistance match drive amplifier. reduced log10(200/50) 1:16 impedance ratio transformer with 800- input resistance, lower.
that output have from constant multiple input plus constant offset (b). Expanding nonlinear transfer functions basic transistor circuits into power series typical quantify distortion products (see Reference example, transistors typically have exponential transfer function (i.e., collector current base emitter voltage), where input output. Expanding into power series around results Figure shows function along with estimates that progressively more terms power series. farther from more terms required estimate value properly. 0.25, linear term provides close estimate actual function, circuit linear. becomes larger, progressively more terms (quadratic, cubic, higher-order distortion terms) required estimate properly. input this circuit sinusoid-i.e., Asin(t) -then output Asin(t) A2sin2(t) A3sin3(t)
Review third-order intercept point (IP3)
nonlinearity transfer function electronics, distortion generated. With reference formula straight line, nonlinearity deviation
where etc. constant scaling factors. Using trigonometric identities cos(2t) sin2(t)
Figure Function power series estimates
y5(x)
y(x)
y4(x) y3(x)
y2(x)
y1(x)
0.25 0.75 1.25 1.75
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sin3(t)
sin(t) sin(3t)
shows that quadratic terms give rise second-order intermodulation distortion (IMD2). Expanding fourth term, K3[A1sin(1t) A2sin(2t)]3 K3[A1sin3(1t) 3A1A2sin2(1t)sin(2t) 3A1A2sin(1t)sin2(2t) A2sin3(2t)]. Using trigonometric identities sin(t) sin(3t) sin3(t)
2(1t)sin(2t) 2sin(2t) sin(21t sin(22t
shows that quadratic cubic terms give rise second- third-order harmonic distortion (HD2 HD3, respectively). Similarly, higher-order terms give rise higher-order harmonic distortion. input comprised tones-i.e., A1sin(1t) A2sin(2t)-then output K1[A1sin(1t) A2sin(2t)] K2[A1sin(1t) A2sin(2t)]2 K3[A1sin(1t) A2sin(2t)]3 where etc. constant scaling factors. Expanding third term, K2[A1sin(1t) A2sin(2t)]2 K2[A1sin2(1t) 2A1A2sin(1t)sin(2t) A2sin2(2t)]. Using trigonometric identities cos(2t) sin2(t) sin(1t)sin(2t) cos(1t cos(1t
shows that cubic terms give rise third-order intermodulation distortion (IMD3). Similarly, higher-order terms give rise higher-order harmonic intermodulation distortion. Table shows frequencies distortion products that will generated second- third-order nonlinearity, given two-tone input frequencies
Table Distortion product frequencies second- third-order nonlinearity
SECOND-ORDER FREQUENCIES THIRD-ORDER FREQUENCIES
Figure Input output two-tone intermodulation distortion
-1-dB Compression Point,
(dBm)
OIP2 (dBm) OIP3 (dBm)
(dBm)
POUT (dBm)
Fundamental
IMD3 IIP2 (dBm) (dBm) IIP3 (dBm)
question arises: this important? answer that radio specifications GSM, CDMA2000, WCDMA, like call sensitivity requirements with interfering signals spaced frequency domain such that their third-order intermodulation product will fall signal interest. third-order intermodulation point used quantify much distortion generated. Referring this antenna input provides easy method determine whether spec met. input output power tones applied device their intermodulation products graphed log-log scale shown Figure fundamental tones have slope second-order product slope third-order products have slope
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device will into compression before lines intersect. point where output power reduced from what expected called 1-dB compression point (P1). extending lines, second- thirdorder intercept points (IP2 IP3, respectively) found. they referred input, they called input intercept points (IIP2, IIP3); they referred output, they called output intercept points (OIP2, OIP3). Since interested intermodulation distortion relative carriers, should concern ourselves with some fictitious point that amplifier will never reach? answer that there mathematical relationship between two. Given intercept point, calculate intermodulation product input/output power. Given that slopes known, equations slopes written shown Figure
Subtracting arbitrary points each line rearranging gives Subtracting again results -(y1 3x3) 2(x3 x2).
IMD3 (dBc)
IIP3 (dBm)
From this seen that IIP3 (dBm) (dBm) IMD3 (dBc)
Once find IMD3 know input power, simple matter plug them into Equation calculate IIP3.
Figure Straight-line relationship between IMD3 fundamental
OIP3 (dBm)
(dBm)
POUT IMD3 (dBc)
IIP3 (dBm)
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Figure Two-tone spectral plot from Reference
Amplitude (dB)
-100 -120
MSPS fIN1 15.17 fIN2 15.89
Frequency, (MHz)
ADCs
testing, tones applied ADC, output examined taking spectral plot find two-tone IMD3. Figure shows such plot from Reference ratio each tones IMD3 product(s) two-tone IMD3 dBc. IMD3 depends signal level. high signal level results excessive distortion, signal level makes distortion hard detect presence noise other spurious components. input signal level below full-scale input dBFS) seems give good results commonly used. Since voltage-driven device, must choose input resistance find signal power with formula V2/R. Assuming that 2Vp-p full-scale input dBm. With input power IMD3, Equation used find IIP3. example calculate, consider following ADS5410, 12-bit ADC. Given that 2Vp-p, IMD3 dBc, then IIP3 41.5
log10(200/50) 1:16 impedance ratio transformer with 800- input resistance, IIP3 lower.
Conclusion
have examined typical noise distortion specifications they relate IP3. seen that required information calculate contained typical data sheet. point remember that voltagedriven device, whereas associated with power. Thus, order calculations proceed, impedance imposed input find corresponding power levels.
References
more information related this article, download Acrobat Reader file www-s.ti.com/sc/techlit/ litnumber replace "litnumber" with Lit. materials listed below. Document Title Lit. "12-Bit, MSPS CommsADC Analogto-Digital Converter," Data Sheet, .slas346 Piet Wambacq Willy Sansen, Distortion Analysis Analog Integrated Circuits (Kluwer Academic Publishers, 1998).
mentioned earlier, common practice transformer fully differential drive highperformance ADCs differentially. originally used shown example, then IIP3 reduced log10(impedance ratio). example, impedance ratio (1:2 turns ratio) transformer, input resistance match drive amplifier. IIP3 reduced
Related sites
analog.ti.com www.ti.com/sc/device/ADS5410
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Evaluation criteria ADSL analog front
John (Email: wu_john@ti.com), Senior Application Engineer, High-Speed Products, C.R. Teeple (Email: teeple_cr@ti.com), Strategic Market Manager, High-Speed Products assigned upstream. lowest-frequency subcarriers Introduction
latest ADSL standard proposed International Telecommunication Union (ITU), with draft recommendation G.992.3-ADSL2, next evolution secondgeneration ADSL. summary first-generation ADSL evaluation design criteria helpful understanding first-generation ADSL mass market designing specifications second-generation ADSL. AFE1302 customer premise equipment (CPE) modem practical ADSL analog front (AFE) design evaluation example. this design, AFE1302 chip reference design printed circuit board used ADSL modem card. maximum reach modem 18,000-ft (5.5-km) loop with downstream rate Kbps upstream rate Kbps. maximum transmitted power defined G.992 power spectral density (PSD) mask requirements. crosstalk from coexisting ADSL ISDN lines minimized limiting maximum strength transmitted ADSL signal power over twisted-pair long wires. addition, Electromagnetic Compatibility Society legislation requires that ADSL transmission system interfere with AM/FM radio reception. These requirements place limit strength transmitted ADSL signal power. This article discusses some evaluation design considerations addressing transmitted data speed, telephone twisted-pair loop attenuation, hybrid circuit, multitone power ratio (MTPR). zero allow voice same line, such plain telephone service (POTS). lowest-frequency subcarrier used upstream determined POTS/ADSL splitting filter. number upstream downstream subcarriers determined receive transmit filters. actual number subcarriers employed modulate data less than maximum determined during initialization sequence. transmitter designates subset maximum available subcarriers connection during channel analysis phase. process ADSL modulation actually modulates each subcarrier 2b(i) quadrature amplitude modulation (QAM). superscript b(i) denotes number bits subcarrier. Subcarriers with lower will assigned fewer bits small-number constellation. Subcarriers with higher will assigned more bits create large-number constellation. Suppose that subcarrier assigned bits; then size carrier constellation QAM. bits determined measured during channel analysis initialization procedure. initialization modem performed five steps: Handshake procedures, channel discovery, transceiver training, channel analysis, exchange. During exchange phase, each receiver communicates far-end transmitter number bits relative power levels used each tone subcarrier, well final data rate information. After successful initialization sequence, transceivers start communication with actual data. channel analysis phase used measure channel characteristics both directions transmission. other words, measures channel transfer function versus frequency response characteristic. downstream channel characteristics measured side, upstream channel characteristics measured central office (CO) side. During channel analysis phase, receiver estimates transmitted channel gain each subcarrier preparation computing total each subcarrier. Then each subcarrier assigned number bits will carry. bits assigned subcarriers within transmitting period (per symbol) determines transmitted data speed. number bits assigned subcarrier calculated b(i) log2[1 snr(i)
Transmitted data speed total signal-to-noise ratio
Transmitted data speed first consideration ADSL modem design evaluation. transmitted data speed function total signal-to-noise ratio (SNR). total telephone loop plus modem receive path SNR. discrete multitone (DMT) modulation standardized ADSL system telecommunication standardization sector ITU. DMT-based ADSL, each subcarrier tone spaced 4.312-kHz intervals. subcarrier assignment defined standard G.992. example, subcarrier assignment G.992.1 annex used frequency division multiplexing separate upstream downstream signals. subcarriers 31-255 (ITU G.992.1), subcarriers 31-127 (ITU G.992.2), reserved downstream. subcarriers 0-30-e.g., maximum total subcarriers-may
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Further, 2b(i) snr(i) 10log10[2b(i) 10log10[snr(i)] 10log10(g) 10log10() 10log10(m). Only 2b(i) following equation true: 10log10[2b(i)] (dB) (dB) (dB) (dB). Therefore, b(i) [SNR (dB) (dB) (dB) (dB)]/3 (bits).(2) Variable definitions preceding equations follows: b(i) number bits subcarrier. subcarrier index from total usable subcarrier number; maximum 256. snr(i) subcarrier; real value that represents ratio between received signal power received noise power that subcarrier. (dB) 10log10[snr(i)]. constant determined required error rate (BER). example, 9.55 10log10() (dB) 10-7. 10log10(g) (dB) gain provided ReedSolomon error correction coding make system robust against impulsive noise bursts. 10log10(m) (dB) margin represent amount increased noise relative noise power that system designed tolerate still meet target e-7, accounting coding (trellis coding Reed-Solomon forward error correction) gains included design. This margin prevent many bits from swapping changes. Normally used prevent online swapping. (dB), (dB), (dB) constants. added assigned b(i) (dB) increases subcarrier channel; this "one-bit-per-3-dB" rule. Assuming that (dB) (dB) (dB) typical b(i) (dB) versus tone number shown Figure transmitted data speed calculated [b(i)]/t where transmitted data speed transmission period. Example gain trellis Reed-Solomon coding included, attainable rate maximum data rate {[SNR (dB) (dB) (dB)]/3 dB}/t (bps) where number subcarriers. Example Additionally, attainable rate simplified follows: {[SNR(i) dB}/t (bps) duration symbol, data symbol rate (4000 data symbols/ second) average rate which symbols carrying data frames transmitted. However, order insert
Figure assignment loop relationship
Loop (dB) Assigned
Number Loop
Tone Number
synchronization symbol, symbol rate defined rate which symbols, including synchronization symbol, transmitted; that (69/68) 4000 4058.8 symbols/second. From equation given earlier, transmitted data speed determined total SNR. modem path noise covered this article. transmitted signal power loop noise specified recommended G.992 follows: G.992.1, downstream dBm/Hz, from 25.875 1104 kHz, total transmission power greater than 20.4 subcarriers used. G.992.2, downstream dBm/Hz, from 25.875 kHz, total transmission power greater than 16.2 subcarriers used. upstream normal transmit PSD, channel analysis signal (R-REVERB1) subsequent upstream signals, dBm/Hz, which equivalent -1.65-dBm total transmit power 4.3125-kHz subcarrier. maximum transmit should higher than dBM/Hz, aggregate transmit power greater than 12.5 subcarriers used. telephone loop noise assumed 31.62 nV/Hz -140 dBm/Hz. specified quiet line noise N(f) particular subcarrier G.992.3-ADSL2; level noise present telephone line when ADSL signals present line. practical evaluation result transmission channel capacity data speed AFE1302
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modem. evaluation based using subcarriers 36-127 downstream with total transmission power less than 15.99 during training phase less than 6.06 during SHOWTIME state. SHOWTIME state normal operation state after initialization training completed. Taking into account noise contributions, loop noise test results referred telephone line less than -148 dBm/Hz over receiver bandwidth AFE1302 modem. tested downstream rate reach Kbps with 18,000-ft (5.5-km) loop. test environments, loop simulator NSA400 26-AWG twisted-pair telephone wire without bridged tap, noise margin interleave depth with trellis coding.
Twisted-pair telephone-loop attenuation
reach ADSL system distance over telephone lines that transmit receive information. Reach performance parameter ADSL limited twisted-pair telephone-loop attenuation. Telephone-loop attenuation defined difference between total maximum transmitted power telephone line total received power other line. Loop attenuation mainly dictated wire diameters, loop length, transmitted signal frequency. most frequently used telephone twistedwire diameters 26-AWG wire 24-AWG wire. typical loop length varies from 6,000 18,000 (1.8 North America, Europe, Asia. ADSL signals cover bandwidth 25.875 1104 specified G.992. According POTS application statistics, typical voice signal loss through telephone loop mile (1.6 within voice bandwidth kHz. Because ADSL signal frequency much higher than POTS signal, because line attenuation increases signal frequency increases, loop attenuation greater within ADSL signal bandwidth.
transfer function twisted-pair telephone loop dominated skin effect: High-frequency currents tend flow only outer portion, skin, conductor, resulting increase attenuation higher frequencies. case twisted-pair loop, attenuation function approximately proportional f1/4 frequencies below kHz, approximately proportional f1/2 frequencies above kHz. experimental data Figure shows that loop attenuation increases from around 3300 over 3300 MHz. This means that 13,100-ft (4-km), 24-AWG twisted-pair telephone loop attenuation over kHz, over MHz. Over ADSL signal bandwidth, twisted-pair loop attenuation varies more than During channel analysis, CO-side receiver calculates average loop attenuation. Based channel analysis signal (R-REVERB1) using subcarriers 7-18, average upstream loop attenuation calculated difference between total transmitted power side total received power measured side. G.992.3-ADSL2, given loop length, loop attenuation defined LATN (dB) log[|H(f)|2/NSC] Variables this equation defined follows: number subcarriers. H(f) channel characteristic function subcarrier. LATN difference decibels between power received near that transmitted from over subcarriers; dynamic range from 102.2 example, assume that LATN 58.2 -140 dBm/Hz, transmitted signal power dBm/Hz, received signal power -88.2 dBm/Hz particular subcarrier. With Equation b(i) calculated bits, which means that bits data assigned that subcarrier. LATN increases 88.2 longer loop, then b(i) only bits because one-bit-per-3-dB rule. longer-reach loop higher subcarrier frequency result greater loop attenuation, which means that fewer data bits assigned subcarriers, lower data speed achieved.
Figure 24-AWG twisted-pair telephoneloop attenuation frequency
Loop Attenuation (dB)
Frequency (kHz) 1000 10000 3,300-ft (1-km) loop 6,500-ft (2-km) loop 9,800-ft (3-km) loop 13,100-ft (4-km) loop
Hybrid circuit
ADSL hybrid circuit three-port network used pass transmit signal from transmission port telephone-loop port pass receive signal from telephone loop port receive port. ADSL hybrid circuit also used eliminate transmit signal from receive signal receive path. allows full-duplex transceiver operation twisted-pair telephone loop. ADSL hybrid echo return loss amount attenuation between transmitted signal power reflected echo power receive path, normally
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Data Acquisition
expressed decibels. target evaluation design ADSL AFE. higher echo return loss, less transmitted signal power gets into receive path. Hecho |log(P echo where Hecho hybrid echo return loss, transtx mitted signal power, portion transmitted echo power that enters receive channel (also called reflected echo power receive path). actual twisted-pair loop impedance Z(f) frequency function telephone line. magnitude twisted-pair impedance about POTS bandwidth; ADSL signal bandwidth, about without bridged taps varies from with bridged taps. hybrid circuit used AFE1302 modem purely resistive basically electrical bridge circuit. When differential drive resistive network becomes balanced, amount hybrid echo minimized. DMT-based ADSL system, ADSL hybrid circuit receive path filter critical factors receiver performance. transmit path signal noise power need sharply attenuated hybrid echo path receive filter. They significantly improve modem reach downstream data speed. typical value 100- equivalent twisted-pair loop impedance, total 40-dB attenuation hybrid circuit receive high-pass filter minimum evaluation design requirement. 20-dB return loss easily achieved through hybrid circuit. hybrid plus third-order, filter on-board provide total echo loss more than That hybrid circuit attenuate transmitted power noise (see Figure
multitone power ratio
multitone power ratio (MTPR) important feature evaluation design DMT-based ADSL systems. Better MTPR performance both transmission receive paths results higher data rates ADSL system. MTPR ratio power subcarrier noise power another selected empty subcarrier. There data bits assigned selected empty subcarrier modulation. MTPR indicates degree which subcarrier signal corrupted distortion from other subcarrier signals. measurement evaluation this kind corruption different from that traditional single-tone distortion. Signal-to-noise distortion ratio (SINAD), spurious-free dynamic range (SFDR), single-tone harmonic distortion, two-tone intermodulation distortion (IMD), third-order intercept point (IP3), total harmonic distortion (THD) used only expressing single- two-tone signal integrity spectral properties. MTPR, other hand, indicates tested device-such line driver, receiver, line transformer, filter, filter, DAC/ADC-responds discrete multitone signal, which tones more. design tasks ADSL modem maintain fidelity discrete multitone signal. analog components used modem-such line transformer, common-mode choke, hybrid circuit, filter, filter, line driver receiver-must designed that they cause minimal corruption discrete multitone signal. subcarrier, minimum transmitter MTPR shall least specified G.992, least recommended G.992.3.
Figure Hybrid echo return loss plus filter attenuation frequency
Frequency (kHz) 1000
Attenuation (dB)
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Data Acquisition
Figure Transmitter path MTPR performance AFE1302
Output (-10 dB/div.)
MTPR
Frequency kHz/div.)
MTPR tested device measured dynamic range from peak power subcarrier peak distortion empty tone. example, test result shows that MTPR 65.82 achieved AFE1302 modem transmission path. test tool National Instruments PXI-1002 arbitrary waveform generator 5411. transmitter path defined path from interface output twisted-pair telephone line interface with 100- impedance (see Figure transmitted multitone signal from tones 6-29 with notch tones internal AFE1302's programmable gain amplifier gain external line driver gain tested result MTPR 65.82
hybrid echo return loss significantly increases received data speed reach. MTPR, kind corruption that differs from traditional single-tone distortion, another important criterion designing evaluating ADSL AFE.
References
more information related this article, download Acrobat Reader file www-s.ti.com/sc/techlit/ litnumber replace "litnumber" with Lit. materials listed below. Document Title Lit. "ITU-T Draft Recommendation G.992.3ADSL2," International Telecommunication Union, Geneva, Switzerland, April 2002. "ADSL Analog Front-End," Data Sheet .sbws014
Summary
This article discussed some evaluation design considerations ADSL AFE. most critical evaluation criterion ADSL transceiver data speed that limited total SNR. second issue frequency variation telephone-loop attenuation impact reach. This article further pointed that improvement
Related sites
analog.ti.com www.ti.com/sc/device/AFE1302
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Power Management
UCC28517 100-W power converter with 12-V, bias supply, Part
Michael O'Loughlin (Email: michael_oloughlin@ti.com)
Member, Applications Engineering Staff
Introduction
Power factor corrected (PFC) preregulators generally used offline ac/dc power converters with power level higher than meet line harmonic requirements such EN61000-3-2. typically done with boost converter ac/dc topology continuous input current that manipulated through average currentmode control achieve near-unity power factor (PF). However, high output voltage boost converter, second dc/dc converter generally needed step down output usable voltage. past this been accomplished with pulse-width modulators (PWMs). controlled regulated
power stage, while second used control step-down converter. UCC28517 controller reduces need PWMs combines both these functions into control-integrated circuit. UCC28517 operates second converter twice switching frequency stage, which reduces size boost magnetics ripple current boost capacitor. more information this device, please Reference This article reviews design second 12-V, power stage used auxiliary bias supply. review preregulator power stage found 3Q03 issue Analog Applications Journal.
Variable definitions
CDIODE COSS Dmax fopto_pole Gc(s) Gco(s) Gopto(s) H(s) Iop_min IRMS PCOND PCOSS PDIODE Soft-start interval Output efficiency Output efficiency Boost diode capacitance drain-to-source capacitance Duty cycle maximum Output capacitance equivalent resistance Voltage-loop crossover frequency Frequency where optoisolator gain from operating point Minimum switching frequency Output switching frequency Output switching frequency Control transfer function Control output transfer function Optoisolator gain transfer function Voltage divider gain Transformer magnetizing current Minimum optocoupler current Peak inductor current, peak diode current, peak switch current device current UCC28517 soft-start current Transformer primary magnetizing inductance Transformer turns ratio Primary turns Secondary turns Device conduction losses Power dissipated FET's drain-to-source capacitance Total loss boost diode PDIODE_CAP PFET_TR PGATE POUTA POUTB QGATE RDS(on) Rload RSENSE tblank Ts(f) Vboost Vdynamic VGATE VOUTA VOUTB VREF Vripple Vslope VVERR VVREF_TL431 Loss boost diode capacitance transition losses Power dissipated gate Output maximum power Output maximum power gate charge resistance Typical load impedance Current sense resistor Angular frequency (j2f) Amount leading-edge blanking time fall time rise time 1/fSB Voltage loop frequency response Same VOUTA Control voltage Oscillator peak Forward diode drop (0.6 Current sense voltage range Forward voltage diode Gate-drive voltage input voltage Boost output voltage (Vboost) Auxiliary output voltage Output peak-to-peak ripple voltage UCC28517 internal reference Output ripple voltage Voltage ramp peak added slope compensation Feedback error voltage TL431 (D13) internal reference
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Power Management
Table Design specifications
Output (VOUTA) Output (VOUTB) Output efficiency Output efficiency POUTA POUTB Output ripple (Vpp) Output ripple (Vripple) Output THD) Output switching frequency (fSA) Output switching frequency (fSB) MAXIMUM Vrms 12.6 TYPICAL MINIMUM Vrms 11.4
following design example generated using typical parameters rather than worst-case values. Please refer Table Figures design specifications component placement. variables defined sidebar page
Transformer turns ratio
following equation used calculate transformer turns ratio needed this power stage. Dmax VOUTA (0.9 Dmax VOUTB
12-V, auxiliary converter (OUTB)
high input voltage from boost converter, this design required dc/dc converter with step-down transformer achieve desired output voltage power requirements permitted discontinuousmode flyback topology, which uses fewer components than standard forward converter.
Figure power stage schematic
UCC28517 PWM/PFC controller user-selectable duty-cycle clamp. this design duty-cycle clamp Dmax 0.55. UCC28517 forward enable comparator that will allow forward converter operate with boost voltage less than nominal value. This allows cascaded step-down converter
G1756 AC_N PB66 0.33 PKLMT 10.0 3.92 TP11
AC_L
HFA08TB60 IRFP450
TP12 22.1
OUTA+
0.47
OUTA-
VREF
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Power Management
Figure dc/dc power stage schematic
PB2039 OUTA+ 44.2 OUTA- VREF GND2 38.3 OUTB+ OUTB-
Note: Star grounding technique must used
VERR
Figure Controller schematic
ISENSE2 VERR D_CLAMP TP10 VERR 9.09
3.92
PKLMT
PWRGND PKLMT CAOUT ISENSE1 MOUT VREF
VSCLAMP VSENSE VAOUT
UCC28517DW VREF 30.1 D_CLAMP 1.18
48.7
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Power Management
operate during loss line voltage. auxiliary winding turns added power UCC28517 control well. this design Pulse Engineering designed 22-turn transformer (part number PB2039).
POUTB VOUTB Dmax Vripple
Power switch (Q2) output diode (D8) selection
select properly, power budget generally these devices maintain desired efficiency goal. following equations were used estimate power loss switching devices. meet power budget this design, IRFBF20S 20CJQ045 dual diode from International Rectifier were chosen. POUTB VOUTB ESRC30
Dmax VOUTB
Dmax IRMS Dmax
IRMS
POUTB Dmax
RSENSE2
PCOND RDS(on PGATE QGATE VGATE PCOSS COSS VOUTB PFET VOUTB IRMS PGATE PCOSS PCOND PFET POUTB Dmax VOUTB CDIODE
VOUTB
dc/dc power converter designed peak-currentmode control. current sense resistor, which sized through following equations. VOUTA Dmax dynamic
Soft start
UCC28517 soft-start circuitry allow controlled ramp second stage's duty cycle during startup. following equation used calculate approximate capacitance needed achieve soft start roughly (t).
PDIODE
Slope compensation
Designing power converter that uses peak-current-mode control generally requires slope compensation remove instabilities control loop make design less susceptible noise. Resistors (Figure portion oscillator signal current sense signal slope compensation. Generally added slope required equal half down slope slope change output current. selecting first, calculate required value generate required slope compensation. slope R11( slope slope
PCOND IRMS Dmax
IRMS
PDIODE PCOND PDIODE
Output capacitor
output capacitor selection step-down converter based requirements energy storage, output ripple voltage, current, peak current.
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Power Management
Leading-edge blanking circuit
typical current sense signal converter using peak-current-mode control shown Figure shown, during time there leading current spike. This partly caused parasitic gate-to-source capacitance power stage switch voltage divider formed gate drive This leading-edge spike cause peak-currentmode signal terminate gate drive prematurely. remove this instability, leading-edge blanking circuit constructed. Electronic components R40, R42, form leading-edge blanking circuit. This circuit used clamp leading-edge current spikes. timing leading-edge blanking adjusted modifying size timing capacitor C10: blank 2(R40 R42)
Figure Typical current sense signal
Figure dc/dc converter control loop
VOUTA (Vboost)
VVREF_TL431
Gc(s)
Gco(s)
VOUTB
H(s)
Control loop dc/dc converter
Figure shows control block diagram control loop dc/dc converter. Gc(s) compensation network's transfer function (TF), Gopto(s) optoisolator gain Gco(s) control-to-output gain H(s) divider gain estimate frequency response each gain block, following equations used. fopto_pole frequency where optoisolator gain from operating point; VVREF_TL431 internal reference voltage TL431 shunt regulator. load represents typical load impedance design. H(s) VREF_TL431 VOUTB 2fopto pole
2fopto pole
VVERR
Figure shows circuitry that used voltage feedback loop. TL431 shunt regulator that function operational amplifier provide feedback control when this configuration.
Figure Voltage feedback loop
VOUTA (Vboost) VOUTB
Gopto(s
Gco(s)
VREF TL431 H11AV1 PGND2
Gc(s C15)
Gco(s)
VOUTB
Rload
Rload
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Initially resistor values divider gain, H(s), must selected. following equation used size these resistors, where VOUTB desired output voltage VVREF_TL431 internal reference TL431. R27(VOUTB VVREF_TL431 VVREF_TL431
Figure Optoisolator frequency response
Gain (dB)
Opto Gain Opto Phase
-120 -180
important bias TL431 optoisolator correctly proper operation. Resistors provide minimum bias currents TL431 optoisolator, respectively, selected with following equations. optoisolator configured have gain roughly optoisolator crossover frequency roughly kHz. Figure shows small signal frequency response optoisolator. ITL431_min
Frequency (Hz)
VREF VVERR(max)
desired crossover frequency. following equations used select R35, C14, Gc(s) obtain desired design goals. log(H(s)
Before attempting compensate control loop, Ts(f), must define some design goals closed-loop frequency response. Typically loop designed cross over frequency below one-sixth switching frequency (see Reference this design example have good transient response, design goal have loop gain crossover frequency (fc) roughly kHz, which less than one-sixth switching frequency (fSB). following equation describes frequency response system loop gain, Ts(f), decibels. Ts(f) Gc(s) Gco(s) H(s)
-(Gco(s)
Gopto(s)
H(s)
compensation network that used (Gc(s)) three poles zero. pole occurs origin, second pole caused limitations optoisolator. third pole one-half switching frequency attenuate high frequency gain. zero
Figure shows measured loop gain frequency response, Ts(f). frequency response characteristics Figure show that roughly equal with phase margin roughly 50°. important note that equations used compensate control loop selecting C14, C15, estimates values have adjusted appropriate compensation.
Figure Frequency loop response, Ts(f)
-108 -144 -180
Frequency (Hz)
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Phase (degrees)
Gain, Ts(f) (dB)
Phase Gain
Phase (degrees)
Power Management
Summary
this design example reviewed design 100-W ac/dc preregulator with auxiliary 12-V, bias supply. UCC2851x family combination controllers perfect offline applications that require auxiliary power supplies meet different system requirements. design performance this two-stage power converter shown Figures 9-12.
Figure Output output power
References
more information related this article, download Acrobat Reader file www-s.ti.com/sc/techlit/ litnumber replace "litnumber" with Lit. materials listed below. Document Title Lit. Laszlo Balogh, "Design Review: 140W, Multiple Output High Density DC/DC Converter," .slup117 Laszlo Balogh, "Unitrode UC3854A/B UC3855A/B Provide Power Limiting With Sinusoidal Input Current Front Ends," Unitrode Design Note .slua196 Lloyd Dixon, "Control Loop Cookbook," 5-17 .slup113 Lloyd Dixon, "Optimizing Design High Power Factor Switching Preregulator," 7-11-7-12 .slup093 James Noon, 250kHz, 500W Power Factor Correction Circuit Employing Zero Voltage Transitions," 1-11-1-14 .slup106 "Practical Considerations Current Mode Power Supplies," Unitrode Application Note .slua110 "Advanced PFC/PWM Combination Controllers," Data Sheet .slus517 "UCC28517 Prototype Reference Design Module," Reference Design .sluu117
Current
Output Power
Figure Output efficiency output power
Efficiency
Output Power
Figure Output output power
0.95
Related sites
analog.ti.com www.ti.com/sc/device/TL431 www.ti.com/sc/device/UCC28517
0.85
Output Power
Figure Output efficiency output power
Efficiency
Output Power
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Amplifiers: Amps
attenuators
Bruce Carter (Email: r-carter5@ti.com)
Advanced Linear Products, Applications
Introduction
Techniques make gain stages have been covered literature decades, most designers fairly competent designing inverting non-inverting gain stages. Those same designers, when faced with need attenuate signal, turn inverting circuit configuration because capable supporting "gains" that required make greater than (see Figure
Figure Incorrect method attenuation
Stable attenuators
make attenuator, circuit must constructed that keeps closed-loop gain Making large comparison advisable. possible, however, construct circuit which "fooled" into thinking operating slightly above unity gain. There ways this. first uses rather complex inverting attenuator; second uses much simpler non-inverting attenuator. discussion these methods follows.
Inverting attenuator
Figure shows inverting attenuator where Although looks superficially simple, actually more complex. makes very nice attenuation circuit termination resistor used, gain calculations designer needs take into account output impedance source part Figure "sees" gain because value plus parallel combination input signal, however, attenuated voltage divider comprised Overall "gain" singleended stage VOUT RBRF RBRG
This attenuation technique advisable, because makes loop gain move toward open-loop plot while simultaneously decreasing phase margin. This least stable configuration amp. Combine this with small values parasitic capacitance inverting input, almost guaranteed oscillate. author recently presented series seminars signal conditioning. Some attendees were attempting produce product which stage gain attendee particular programmable attenuator that completely stable gain exhibited overshoot and/or ringing gain 1/10, oscillated uncontrollably gain 1/100. seminar material stability quite eye-opener! This material available References through
would probably more useful designers expression were solved proper values resistors
Figure Inverting attenuator
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Amplifiers: Amps
generate desired attenuation. this more easily, some substitutions made: What this does, effect, twofold: guarantees that will never less than unity gain. then becomes also means that included circuit goes down value, will gain which seems wasteful, there technical reason will work. will never gain above, because limiting case with would gain course, making would make practical circuit. Very often, designers will want know value given attenuation. substitutions mentioned earlier made, solved follows:
discounted gain calculations. "gain" this stage familiar voltage divider expression VOUT
designer also this attenuation circuit when input termination resistor, output impedance source taken into account part also utility generate best possible match resistors non-inverting attenuator. Reference click "Single Output Amplifier Design Utilities," then "Voltage Divider Utility.")
Fully differential attenuators
Attenuators constructed from fully differential amps somewhat analogous terminated fully differential circuits, except that resistor that accomplishes attenuation does necessarily have termination resistor standard termination value.
Figure Fully differential attenuator operation
This relationship will yield proper values when values known. Data sheets highspeed amps frequently specify values Texas Instruments (TI) site includes utility calculate best resistor values automatically inverting attenuator. Reference click "Single Output Amplifier Design Utilities," then "Inverting Attenuator Calculator.") options included-one that allows designer select based device data sheet, another that calculates closest possible match resistors desired attenuation.
VOCM
VOCM
Non-inverting attenuator
much simpler attenuator, shown Figure employs unity-gain, non-inverting buffer. Because input impedance non-inverting high,
Consider circuit Figure this configuration, voltage divider formed action RA1, RA2, Remember that each signal return path other polarity signal. gain fully differential stage
VOUT RBRF RBRG RARB RARG
Figure Non-inverting attenuator
solve proper values resistors generate desired attenuation, same substitutions made that were made equation given earlier gain single-ended stage:
These substitutions have same twofold effect explained before: will never less than unity gain; and, included circuit goes down value, will gain these
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Amplifiers: Amps
substitutions made, value given attenuation solved follows:
References
more information related this article, download Acrobat Reader file www-s.ti.com/sc/techlit/ litnumber replace "litnumber" with Lit. materials listed below. Document Title Lit. "Single Supply Design Techniques," Application Note .sloa076 "Feedback Stability Theory," Application Note .sloa077 "Development Ideal Equations," Application Note .sloa078 "Engineering Design Utilities," Texas Instruments, www.ti.com/amplifier_utilities
before, this relationship will yield proper values when values known. Data sheets fully differential amps frequently specify values Fully differential attenuators designed using same utility mentioned before. Reference click "Single Output Amplifier Design Utilities" "Fully Differential Amplifier Design Utilities," then "Inverting Attenuator Calculator.")
Related sites
analog.ti.com www.ti.com/amplifier_utilities
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Amplifiers: Amps
Calculating noise figure amps
James Karki (Email: j-karki@ti.com)
Member, Group Technical Staff, High-Performance Linear
Introduction
Noise figure commonly used communications systems because provides simple method determine impact system noise sensitivity. Today, performance wide-band amps making them viable alternatives more traditional open-loop amplifiers like monolithic microwave integrated circuits (MMICs) discrete transistors communications design. Recognizing need specify wideband amps engineering terminology, some manufacturers provide noise figure, they seem exception rather than rule. manufacturers typically specify noise performance giving inputreferred voltage current noise. noise figure depends these parameters, circuit topology, value external components. have this information, noise figure calculated.
Figure Non-inverting noise analysis diagram
Review noise figure
Noise figure (NF) decibel equivalent noise factor (F): (dB) 10log(F). Noise factor device power ratio signalto-noise ratio (SNR) input (SNRI) divided output (SNRO): SNRI SNRO Assuming that input terminated same impedance source, -174 dBm/Hz, where Boltzman's constant Kelvin). Once find input noise spectral density device, simple matter plug into Equation calculate
amps
amps specify input-referred voltage current noise. Using these parameters, adding noise external resistors, calculating total input-referred noise based circuit topology, calculate input spectral density Equation this discussion, terms amp" "amplifier" mean different things. amp" refers only active device itself, whereas "amplifier" includes associated passive resistors that make work usable amplifier stage. other words, amplifier everything shown Figures except only components within dashed triangles. this way, plane marked input amplifier. This point which noise sources must referred that Equation used.
output signal (SO) equal input signal (SI) times gain: output noise equal noise delivered input (NI) from source plus input noise device (NA) times gain: Substituting into Equation simplifying, SNRO SNRI
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Amplifiers: Amps
noise from source input noise amplifier referred same point. Because impedance same, expressing ratio between voltage ratio squared equivalent power ratio. voltagedriven device, using voltage-squared terms makes calculations easier. following discussion, voltage-squared terms used amps negative feedback control gain amplifier. result that voltage across input terminals driven zero. This often referred "virtual short." used following analysis* referred "amplifier action," since by-product doing amplifier. Superposition used throughout analysis, wherein sources except under consideration defeated-voltage sources shorted current sources opened.
Figure Inverting noise analysis diagram
Non-inverting amplifier
three basic circuits, easiest find input-referred noise non-inverting amplifier, will discussed first. Figure shows noise analysis diagram non-inverting amplifier with noise sources identified. source resistance generates noise voltage equal 4kTRS. noise voltage delivered amplifier input from source divided resistors Therefore, 4kTRS typically used terminate input that which case kTRS. amplifier's voltage noise combination eni, ini, with associated impedances These referred
Figure Fully differential noise analysis diagram
*The virtual-short concept simplifies analysis. Much more work required obtain same results other means such nodal analysis.
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Amplifiers: Amps
input their respective scaling factors summed find i.e.,
c1e2 c2i2 c3i2 c4eT c5eG c6eF
where through scaling factors. amp's input voltage noise eni. appears directly amplifier's input scaling factor unity, that c1eni eni. amp's non-inverting input current noise ini. develops voltage through parallel combination which appears directly amplifier's input, that amp's inverting input current noise iii. develops voltage through parallel combination amp's inverting input. amplifier action, this voltage appears amplifier's input, that RFRG
Figure shows noise analysis diagram inverting amplifier with noise sources identified. find input-referred noise, easiest some cases find output noise then divide signal gain amplifier. noise voltage delivered input from source divided resistors parallel with Therefore, 4kTRS RS(RM
typically selected that which case kTRS. amplifier's input-referred voltage noise combination eni, ini, with associated impedances These referred input their respective scaling factors summed find i.e.,
c1e2 c4eT c5eG c6eF c7e2
noise voltage term associated with equal 4kTRT. divided resistors that
c4eT
where through scaling factors. amp's input voltage noise, eni, amp's non-inverting input appears amplifier output function amplifier noise gain,
4kTRT
then c4eT kTRT. noise voltage term associated with equal 4kTRG. This noise divided resistors applied amp's inverting input. Again amplifier action, noise from appears amplifier's input, that
then referred back amplifier input function signal gain, /RG. Thus, c1e2 amp's non-inverting input current noise ini. develops voltage through that appears directly amplifier's input, that RSRM hard calculate amp's inverting input current noise, iii. Basically, amplifier action, inverting node ground that current drawn through input resistor noise current flows through producing voltage output equal iiiRF. Referring amplifier's input results c3iii iii(RG)2. noise voltage term associated with equal 4kTRT. Just like eni, appears output function
**The gain actually -RF/RG; since squared, minus sign ignored this analysis.
c5eG
4kTRG
noise voltage term associated with equal 4kTRF appears amplifier's output. Dividing signal gain gives c6eF 4kTRF With terms Equation quantified, take find along with Equation find
Inverting amplifier
Finding input-referred noise inverting amplifier more cumbersome than finding that noninverting amplifier. main problem that signal gain amplifier noise gain different.
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Amplifiers: Amps
amplifier noise gain then referred back amplifier input function signal gain, that c4eT kTRT noise voltage term associated with equal 4kTRG. divided resistors parallel with route amplifier's input, that c5eG 4kTRG RSRM noise voltage term associated with equal 4kTRF appears directly amplifier's output. Dividing signal gain gives
c6eF
where through scaling factors. this analysis assumed that input resistors equal that feedback resistors equal. amp's input voltage noise, eni, amp's input appears amplifier output function amplifier noise gain, 2(RS
then referred back amplifier input function signal gain, RF/RG. Thus, c1e2 2(RS
4kTRF
noise source associated with input termination matching resistor equal 4kTRM. divided resistors parallel with that c7e2 4kTRM
With terms Equation quantified, take find along with Equation find
Since input resistors equal feedback resistors equal, amp's non-inverting input current noise, ini, inverting input current noise, iii, have same scaling factors. amplifier action, input nodes grounds that current drawn through input resistors noise current flows through producing voltage output equal iniRF iiiRF. Referring amplifier's input results c2ini ini(RG)2 c3i2 i2(RG)2. noise voltage term associated with each equal 4kTRG. divided resistors onehalf parallel with that c4eG 4kTRG 2(RS
Fully differential amplifier
Fully differential amplifiers very similar inverting amplifiers, analysis follows very closely. Figure shows noise analysis diagram. source resistance generates thermal noise equal 4kTRS. noise voltage delivered input from source divided resistors parallel with 2RG. Therefore, 4kTRS typically selected that which case kTRS. amplifier's input-referred voltage noise combination eni, ini, with associated impedances These referred input their respective scaling factors summed find i.e., c1e2
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noise voltage term associated with each equal 4kTRF appears directly amplifier's output. Dividing signal gain gives c5eF 4kTRF noise source associated with input termination matching resistor equal 4kTRM. divided resistors parallel with 2RG, that 2RSRG c6e2 4kTRM 2RSRG before, with terms Equation quantified, calculated used with Equation find noise factor.
c4eG
c5eF
c6e2
2003
Analog Applications Journal
Amplifiers: Amps
Table Comparison calculated measured noise figure
THS3202 THS3202 THS4501 CONFIGURATION Non-inverting Inverting Fully differential (nV) 1.65 1.65 (pA) 13.5 13.5 (pA) 49.9 49.9 49.9 56.2 CALCULATED (dB) 11.6 13.6 30.1 MEASURED (dB) 11.5 13.0 30.6
Conclusion
input-referred voltage noise current noise, along with circuit configuration component values, used calculate noise figure. This tedious task best. Setting spreadsheet each topology where component values specs entered recommended. this way, various scenarios quickly tested. Verification testing circuit with noise figure analyzer always suggested. example well theory outlined this article matches test results, noise figure three
amplifiers configured previously detailed were measured with Agilent N8973A noise figure analyzer. Table shows that results good, with input current voltage noise specifications given typical values.
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Appendix-Summary noise terms amplifiers
Signal input noise (NI) terms
AMPLIFIER CONFIGURATION NOISE SOURCE NOISE CONTRIBUTION
Non-inverting
Source thermal noise
4kTRS
Inverting
Source thermal noise
4kTRS RS(RM 4kTRS
Fully differential
Source thermal noise
Analog Applications Journal 2003 www.ti.com/sc/analogapps Analog Mixed-Signal Products
Amplifiers: Amps
Appendix-Summary noise terms amplifiers (Continued)
Device input noise (NA) terms
AMPLIFIER CONFIGURATION NOISE SOURCE NOISE CONTRIBUTION
input-referred voltage noise non-inverting input-referred current noise
inverting input-referred current noise Non-inverting Termination resistor thermal noise voltage
4kTRT 4kTRG 4kTRF
Gain resistor thermal noise voltage
Feedback resistor thermal noise voltage
input-referred voltage noise
non-inverting input-referred current noise
(RG)2
inverting input-referred current noise
Inverting
Non-inverting bias matching resistor thermal noise voltage
4kTRT 4kTRG 4kTRF
Gain resistor thermal noise voltage
Feedback resistor thermal noise voltage
Inverting termination matching resistor thermal noise voltage
4kTRM
Analog Mixed-Signal Products www.ti.com/sc/analogapps 2003 Analog Applications Journal
Amplifiers: Amps
Appendix-Summary noise terms amplifiers (Continued)
Device input noise (NA) terms (Continued)
AMPLIFIER CONFIGURATION NOISE SOURCE NOISE CONTRIBUTION
input-referred voltage noise
2(RS (RG)2 (RG)2
non-inverting input-referred current noise inverting input-referred current noise
Fully differential
Gain resistor thermal noise voltage
4kTRG 2(RS 4kTRF
Feedback resistor thermal noise voltage
Termination matching resistor thermal noise voltage
2RSRG 4kTRM 2RSRG
Analog Applications Journal 2003 www.ti.com/sc/analogapps Analog Mixed-Signal Products
Index Articles
Index Articles
Title Issue Page
Data Acquisition
Aspects data acquisition system design .August 1999 Low-power data acquisition sub-system using TLV1572 .August 1999 Evaluating operational amplifiers input amplifiers A-to-D converters .August 1999 Precision voltage references .November 1999 Techniques sampling high-speed graphics with lower-speed converters .November 1999 methodology interfacing serial A-to-D converters DSPs .February 2000 operation SAR-ADC based charge redistribution .February 2000 design performance precision voltage reference circuit 14-bit 16-bit A-to-D D-to-A converters .May 2000 Introduction phase-locked loop system modeling .May 2000 development environment includes data converter plug-ins (PDF .August 2000 Higher data throughput analog-to-digital converters (PDF .August 2000 Efficiently interfacing serial data converters high-speed DSPs (PDF .August 2000 Smallest DSP-compatible provides simplest interface (PDF .November 2000 Hardware auto-identification software auto-configuration TLV320AIC10 Codec "plug-and-play" algorithm (PDF .November 2000 Using quad octal ADCs mode (PDF .November 2000 Building simple data acquisition system using TMS320C31 (PDF .February 2001 Using synchronous communication with data converters interfacing MSP430F149 TLV5616 (PDF .February 2001 conversion graphics component video signals, Part Hardware (PDF .February 2001 conversion graphics component video signals, Part Software control .July 2001 Intelligent sensor system maximizes battery life: Interfacing MSP430F123 Flash MCU, ADS7822, TPS60311 .First Quarter, 2002 SHDSL AFE1230 application .Second Quarter, 2002 Synchronizing non-FIFO variations THS1206 .Second Quarter, 2002 Adjusting voltage reference provide gain .Third Quarter, 2002 MSC1210 debugging strategies high-precision smart sensors .Third Quarter, 2002 Using direct data transfer maximize data acquisition throughput .Third Quarter, 2002 Interfacing amps analog-to-digital converters .Fourth Quarter, 2002 ADS82x with non-uniform sampling clock .Fourth Quarter, 2003 Calculating noise figure third-order intercept ADCs .Fourth Quarter, 2003 Evaluation criteria ADSL analog front .Fourth Quarter, 2003
Power Management
Stability analysis low-dropout linear regulators with PMOS pass element .August 1999 Extended output voltage adjustment using TPS5210 .August 1999 Migrating from TL770x TLC770x .August 1999 TPS5602 powering TI's .November 1999 Synchronous buck regulator design using TPS5211 high-frequency hysteretic controller .November 1999 Understanding stable range equivalent series resistance regulator .November 1999 Power supply solutions DSPs using synchronous buck converters .February 2000 Powering Celeron-type microprocessors using TI's TPS5210 TPS5211 controllers .February 2000 Simple design ultra-low-ripple DC/DC boost converter with TPS60100 charge pump .May 2000 Low-cost, minimum-size solution powering future-generation CeleronTM-type processors with peak currents .May 2000
Analog Mixed-Signal Products www.ti.com/sc/analogapps 2003 Analog Applications Journal
Index Articles
Title
Issue
Page
Power Management (Continued)
Advantages using PMOS-type low-dropout linear regulators battery applications (PDF .August 2000 Optimal output filter design microprocessor power supply (PDF .August 2000 Understanding load-transient response LDOs (PDF .November 2000 Comparison different power supplies portable solutions working from single-cell battery (PDF .November 2000 Optimal design interleaved synchronous buck converter under high-slew-rate, load-current transient conditions (PDF .February 2001 -48-V/+48-V hot-swap applications (PDF .February 2001 Power supply solution termination .July 2001 Runtime power control DSPs using TPS62000 buck converter .July 2001 Power control design realizing InfiniBandSM benefits .First Quarter, 2002 Comparing magnetic piezoelectric transformer approaches CCFL applications .First Quarter, 2002 wall adapter input power? .First Quarter, 2002 SWIFT Designer power supply design program .Second Quarter, 2002 Optimizing switching frequency ADSL power supplies .Second Quarter, 2002 Powering electronics from port .Second Quarter, 2002 Using UCC3580-1 controller highly efficient 3.3-V/100-W isolated supply design .Fourth Quarter, 2002 Power conservation options with dynamic voltage scaling portable designs .Fourth Quarter, 2002 Understanding piezoelectric transformers CCFL backlight applications .Fourth Quarter, 2002 Load-sharing techniques: Paralleling power modules with overcurrent protection .First Quarter, 2003 Using TPS61042 white-light driver boost converter .First Quarter, 2003 Auto-Trackvoltage sequencing simplifies simultaneous power-up power-down .Third Quarter, 2003 Soft-start circuits linear regulators .Third Quarter, 2003 UCC28517 100-W power converter with 12-V, bias supply, Part .Third Quarter, 2003 UCC28517 100-W power converter with 12-V, bias supply, Part .Fourth Quarter, 2003
Interface (Data Transmission)
TIA/EIA-568A Category cables low-voltage differential signaling (LVDS) .August 1999 Keep LVDS input levels .November 1999 Skew definition jitter analysis .February 2000 LVDS receivers solve problems non-LVDS applications .February 2000 LVDS: ribbon cable connection .May 2000 Performance LVDS with different cables (PDF .August 2000 statistical survey common-mode noise (PDF .November 2000 Active Fail-Safe feature SN65LVDS32A (PDF .November 2000 SN65LVDS33/34 ECL-to-LVTTL converter .July 2001 Power consumption LVPECL LVDS .First Quarter, 2002
Amplifiers: Audio
Reducing output filter Class-D amplifier .August 1999 Power supply decoupling audio signal filtering Class-D audio power amplifier .August 1999 layout TPA005D1x TPA032D0x Class-D APAs .February 2000 audio circuit collection, Part (PDF .November 2000 1.6- 3.6-volt speaker driver reference design (PDF .February 2001 Notebook computer upgrade path audio power amplifiers (PDF .February 2001 audio circuit collection, Part (PDF .February 2001 audio circuit collection, Part .July 2001 Audio power amplifier measurements .July 2001 Audio power amplifier measurements, Part .First Quarter, 2002
Analog Applications Journal 2003 www.ti.com/sc/analogapps Analog Mixed-Signal Products
Index Articles
Title
Issue
Page
Amplifiers: Amps
Single-supply design .November 1999 Reducing crosstalk .November 1999 Matching operational amplifier bandwidth with applications .February 2000 Sensor analog interface design .May 2000 Using decompensated improved performance .May 2000 Design sine wave oscillators (PDF .August 2000 Fully differential amplifiers (PDF .August 2000 component design (PDF .August 2000 Reducing design costs: From schematic capture layout (PDF .August 2000 Thermistor temperature transducer-to-ADC application (PDF .November 2000 Analysis fully differential amplifiers (PDF .November 2000 Fully differential amplifiers applications: Line termination, driving high-speed ADCs, differential transmission lines (PDF .February 2001 Pressure transducer-to-ADC application (PDF .February 2001 Frequency response errors voltage feedback amps (PDF .February 2001 Designing distortion with high-speed amps .July 2001 Fully differential amplifier design high-speed data acquisition systems .Second Quarter, 2002 Worst-case design circuits .Second Quarter, 2002 Using high-speed amps high-performance design, Part .Second Quarter, 2002 Using high-speed amps high-performance design, Part .Third Quarter, 2002 FilterProlow-pass design tool .Third Quarter, 2002 Active output impedance ADSL line drivers .Fourth Quarter, 2002 amplifiers with amps .First Quarter, 2003 Analyzing feedback loops containing secondary amplifiers .First Quarter, 2003 Video switcher using high-speed amps .Third Quarter, 2003 Expanding usability current-feedback amplifiers .Third Quarter, 2003 attenuators .Fourth Quarter, 2003 Calculating noise figure amps .Fourth Quarter, 2003
General Interest
Synthesis characterization nickel manganite from different carboxylate precursors thermistor sensors (PDF .February 2001 Analog design tools .Second Quarter, 2002
Analog Mixed-Signal Products www.ti.com/sc/analogapps 2003 Analog Applications Journal
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