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No. AN9511

Harris Data Acquisition

Harris Semiconductor
No. AN9511
August 1995
Harris Data Acquisition
Author: Bob Huckabee
Using the HI5710 Evaluation Board
Description
HI5710 Theory of Operation
The HI5710 is a 10 bit CMOS A / D converter designed in a 1.4µm CMOS process. As illustrated in the functional block diagram, Figure 2, the HI5710 is a 2-step A / D converter featuring a 5-bit upper comparator group and a 5-bit lower comparator group along with error correction and output latches. This design requires fewer comparators than typical flash converters thereby lowering the power dissipation. An internal calibration mode is used to improve linearity. The calibration mode is controlled by the user. The operation of the part is depicted in the timing diagram of Figure 3. There is a 3 cycle clock delay from the analog input sampling point to the corresponding digital output data.
Layout and Power Supplies
The HI5710 evaluation board is a four layer board with a layout optimized for the best performance for the ADC. The two internal layers are power and ground with the analog and digital planes separated. The ground planes are connected
Evaluation Board Block Diagram
CLOCK CLK OUT
1 / 16 2.5V REF 2.0V +2 4.0V JP1 VRT 2.0V JP2 VRB CLK CAL RESET
HI5710
10 AC INPUT JP4 VIN JP3 DC INPUT DOUT
10 DATA OUT
FIGURE 1.
Copyright
Application Note 9511 Functional Block Diagram
VIN 39 S / H AMP + COURSE CORRECTION AND LATCH x8 12 D9 (MSB) 11 D8 10 D7 9 D6
VRT 29
VRT 30 DAC COURSE COMPARATOR AND ENCODE FINE COMPARATOR AND ENCODE
5 4 FINE LATCH 3 2
CALIBRATION UNIT
1 D0 (LSB) 21 MINV 20 LINV 19 TESTMODE
VRB 34 VRB 35 CLK 22 CE 23 OE 24 TIMING GEN
41 CAL 17 SEL 15 RESET
FIGURE 2. HI5710 FUNCTIONAL BLOCK DIAGRAM
Timing Diagrams
tPW1 tPW0
1.65V CLOCK tSD N+1 ANALOG INPUT N N+3 N+4 DATA OUTPUT N-3 N-2 N-1 N N+2
1.65V
FIGURE 3. HI5710 TIMING DIAGRAM
Application Note 9511 Timing Diagrams (Continued)
TABLE 1. OUTPUT DATA FORMAT TESTMODE 1 1 1 1 0 0 0 0 NOTES: 1. This table shows the output state for the combination of TESTMODE, LINV, and MINV states. 2. N: Non-Inverted Output. 3. I: Inverted Output.
10ns OR MORE 10ns OR MORE CLK
10ns OR MORE 7 CLOCK
FIGURE 4. CALIBRATION TIMING DIAGRAM
Calibration Block Diagram
CLOCK 1 / 16 VDD D Q CAL
10 BIT COUNTER CLR CLR
FIGURE 5. CALIBRATION BLOCK DIAGRAM
Application Note 9511
at one point under the ADC. Figures 10 through 17 include a schematic of the board, board layout, and various board layers. In order to optimize performance of the HI5710 at power up, AVDD and DVDD are driven from separate supplies. The supplies to the board should be driven by individual clean linear regulated supplies. They can be hooked up with external 16 gauge wires to the holes marked +5VD, +5VA, +12V, -12V, DGND, and AGND on the prototype area. Do not tie the supply grounds together back at the supplies as this will create a ground loop and create additional noise. The analog and digital supplies should be connected together to prevent the chance of latch up. If only one +5V supply is desired for the analog and digital power then connect the +5VA and +5VD supplies together and connect DGND to the supply ground, letting AGND float. No real difference in room temperature performance has been observed when using either supply connection. The digital supply can run from 3.3V to 5V. At 3.3V, the digital outputs of the HI5710 generate less radiated noise, but have less drive capability. The digital outputs will only swing to DVDD. The evaluation board uses HC CMOS logic to allow the user to vary the digital supply without having to change the logic devices. The operating conditions for the evaluation board power supplies are listed below.
TABLE 2. POWER SUPPLY REQUIREMENTS POWER SUPPLY +5VD +5VA +12V -12V TYP CURRENT 27mA 30mA 18mA 12.5mA
options, AC or DC coupled. Use VIN1 (J2) for a DC coupled input. This input uses U1 to gain up the input and provide a DC offset (P2) to center the input between the top and bottom reference voltages.
RT - VRB can be AC coupled to the HI5710 through the VIN2 (J1) BNC and applied to the HI5710. P1 provides the necessary DC bias to center the input between the top and bottom reference voltages.
Calibration
The HI5710 has a built-in calibration circuit to minimize linearity error. The RESET and CAL inputs should be timed required for both the RESET and CAL inputs an thethey must stay low for at least one clock period. A negative pulse on the RESET input should occur before the CAL input sees a falling edge. This sets up the initial calibration value. The calibration starts on the rising edge of the clock after the falling edge of the CAL pulse and requires 300 pulses to complete the calibration. The RESET input serves to minimize the calibration time, but it is not mandatory that it be used. The RESET input must remain at a high state when not in use. The calibration, when executed without the RESET pulse, requires 600 calibration pulses. One calibration cycle is completed in 11 clock cycles. Seven clock cycles after the calibration pulse, the calibration circuit takes exclusive possession of the lower comparators, D0 through D4, for four clock cycles. During this time, the outputs are latched with the previous data (cycle seven data). The upper 5 bits, D5 through D9, will operate as usual during the calibration if the SEL input is held high, making the HI5710 a 5 bit A / D converter during the last four clock cycles of the calibration. If the SEL input is low, the upper 5 bits are latched with the previous data (cycle seven data) during the last four cycles of the calibration as are the lower 5 bits.
MIN +4.75V +4.75V +8.0V -15.0V
TYP +5.0V +5.0V +12.0V -12.0V
MAX +5.25V +5.25V +15.0V -8.0V
Reference Circuit
Analog Input
The analog input to the HI5710 can be configured in various ways depending on the input signal and the required level of performance. Due to the low input capacitance an input buffer is not necessary, but the input should be driven from a low impedance source. The evaluation board has two input
Another possible method for composite video applications would be to use the horizontal sync to initiate one pulse to the CAL input. For a 20MHz clock the calibration time is only 550ns, therefore no data is lost during the calibration while the digital outputs are latched. See Figure 4 in the HI5710 datasheet.
Application Note 9511 Chip Enable Input
The HI5710 has a chip enable / disable input, CE, that puts the part into a low power standby mode when pulled high. The supply current drops from 30mA to less than 1mA during standby. The CE input on the evaluation board is tied to ground through a 50 resistor. This keeps the part enabled and allows the users to test the CE pin by connecting a pulse generator to the CE BNC (J4) input. MINV and LINV inputs. This feature can be used for in-circuit testing of the digital bus.
Increased Accuracy
Further calibration of the ADC can be done when using the external reference and input buffer circuit. First, a precision voltage equal to the ideal VIN-FS + 0.5 LSB is applied at the HI5710 VIN input through JP3. P3 is then adjusted until the 0 to 1 transition occurs on the digital output. Finally, a voltage equal to the ideal VIN+FS - 1.5 LSB is applied. P4 is then adjusted until the 1022 to 1023 transition occurs on the digital output.
Output Enable Input
The output enable, OE, input when held low enables the digital outputs. When held high, the digital outputs are 3-stated, see Figure 6. The OE input on the evaluation board is tied to ground through a 50 resistor. This keeps the output enabled and allows the users to test the OE pin by connecting a pulse generator to the OE BNC (J5) input. Typical enable / disable times are listed in Table 3.
TABLE 3. OUTPUT ENABLE / DISABLE TIMES PART HI5710 tPZL 15ns tPLZ 25ns tPZH 15ns tPHZ 25ns
Input Clock Driver and Timing
TABLE 4. EVALUATION BOARD TIMING PARAMETER tOD DESCRIPTION HI5710 Data Delay 74HC04 Prop Delay 74HC541 Prop Delay MIN TYP 18ns MAX 30ns
Digital Outputs
The digital outputs are CMOS outputs. The LINV input will invert outputs D0 through D8 and MINV will invert output D9 (MSB). This allows the user to set the output for a number of different digital formats. The digital supply can run from +3.3V to +5.0V. The digital output will generate less radiated noise using +3.3V, but the outputs will have less drive capability. The digital outputs will only swing to DVDD, therefore exercise care if interfacing to +5V logic when using a +3.3V supply. The output can also be set to a fixed, defined state, see Table 1. By setting the TESTMODE pin low, the outputs go to a defined digital pattern. This pattern is varied by the
tPD1, tPD2
tPLZ tPHZ
DATA OUTPUT
ACTIVE
HIGH IMPEDANCE
FIGURE 6. ENABLE / DISABLE TIMING
Application Note 9511
CLOCK INPUT (J3) tPD1 HI5710 CLOCK INPUT tOD
D0-D9 OUTPUT
DATA tPD2
CLK OUT AT CONN1 (74HC04) tPD3
DOUT0-DOUT9 (74HC541)
FIGURE 7. INPUT-TO-OUTPUT TIMING
HI5710 Characterization
Acknowledgments
Thanks to Gary Smith for his assistance.
References
AN8906, Noise Aspects of Applying Advanced CMOS Semiconductors. AN9102, Noise Aspect of Applying Advance CMOS Semiconductors. AN9214.2, Using Harris High Speed A / D Converters. AN9313.1, Circuit Considerations in Imaging Applications. Michael O. Felix, "Differential Phase and Gain Measurements in Digitized Video Signals", SMPTE Journal, 85:76-79, February 1976. Frederick A. Williams and Richard K. Olsen, "Quantization Effects on Differential Phase and Gain Measurements", SMPTE, Nov. 1982. W. D. Bartlett, "Quantization Effects when Differential Gain", IMTC, 366-368, May 1992.
Testing
Application Note 9511
PHASE HP8662A LOCK HP8662A HP8662A
PULSE GENERATOR
BAND-PASS FILTER
PULSE GENERATOR
VIDEO GENERATOR
VIN CLK HI5710 EVALUATION BOARD HI5710 DIG OUT 10 HI5710 EVALUATION BOARD CLK
VIN HI5710 DIG OUT 10
DAC DAC DAS LOGIC ANALYZER GPIB OSCILLOSCOPE PC OSCILLOSCOPE VM700A ANALYZER
FIGURE 8. COHERENT TEST SYSTEM
FIGURE 9. VIDEO TEST SYSTEM
TABLE 5. FACTORY BOARD SETTING JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 P1 P2 P3 P4 VRT, Set to use external reference. VRB. Set to use external reference. AC Coupled Input. Jumper not installed. DC Coupled Input. Jumper Installed. MINV: Jumper set to Logic Low. Normal Output. LINV: Jumper set to Logic Low. Normal Output. TESTMODE: Jumper set to Logic High. Normal Outputs. SEL: Jumper set to High. Normal Data Output. Set to give 3.0V at JP4. Set to give 3.0V at JP3. Set to give 2.0V at jumper pin J2. Set to give 4.0V at jumper pin J1.
Application Note 9511 Schematic
+5VA U3 2 4 VIN GND REF03 VOUT TRIM 6 GAIN 5 P3 10K C4 0.1 3 2 +12V 8 U2A 1 + R5 20 4.0V JP1 C8 1.0 C3 0.1
CA158A 4 -12V C6 0.01
R8 5K +12V 5 6 + 8 U2B R6 20 2.0V JP2 C9 1.0 C2 0.1
CA158A C7 0.01
P2 10K
4 -12V C4 0.1 3 2 + +12V 7 U1 R9 6 JP3 JP4 R3 24 5K
HA5020 J2 VIN1 R10 88.7 J1 VIN2 R4 51 C5 + 10µF 681 C10 NU 1K -12V R11 4 R12
R1 1K P1 10K
FIGURE 10. SCHEMATIC
Schematic
13 12 CD74HC04 2 CLK CD74HC04 VRT VRB 1 19 G1 G2 74HC541 29 V 30 RT VRT 22 U6 U11 CLK OUT 2 4 6 CONN1
CLOCK
R13 51
2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
J4 +5VD JP5 +5VD JP6 +5VD +5VA +5VA JP7 U11
CHIP ENABLE VIN +5VA +5VA +5VA +5VA 41 CAL 17 SEL 15 RESET DVDD DVDD +5VD JP8 7 45
R14 51 21 MINV 20 LINV 19 TESTMODE
34 V 35 RB VRB 23 CE 24 OE 39 VIN
J5 42 TS 18 AVDD 25 AVDD 26 AVDD
OUTPUT ENABLE
R15 51
Application Note 9511
14 TIN 6 DVSS 16 DVSS 48 DVSS HI5710 Q Q 12 5 3 U8A 74HC00 1 2 MIN HI: MSB IS INVERTED LO: MSB IS NORMAL LIN HI: D0 - D8 ARE INVERTED LO: D0 - D8 ARE NORMAL
C11 100pF
40 37 27 28 36 43 44 NC TSTR AVSS AVSS AVSS AVSS AVSS 2 3 4 5 6 7 8 9 1 19
REXT / CEXT
+5VD 10 U5B +5VD 4 U5A 12 9 D PR Q 2 13 5 CLK D PR Q 3 8 CLK CL Q 6 74HC74 CL Q 13 74HC74 1 +5VD +5VD 74HC541
R17 4.75K
9 A 10 B 11 CLR 74HC221
C12 0.1
+5VD 10 U7B +5VD 4 U7A 12 9 D PR Q 2 13 PR Q 5 CLK D 3 8 CLK CL Q 6 74HC74 CL Q 13 74HC74 1 +5VD
R18 4.75K
REXT / CEXT 1 13 A Q 2 B 4 3 Q CLR 74HC221
TESTMODE HI: D0 - D9 NORMAL LO: D0 - D9 TO DEFINED STATE SEL HI: DATA NORMAL LO: D5 - D9 LATCHED
FIGURE 11. SCHEMATIC
Application Note 9511 Schematic
FB2 +5VD + C15 10µF DGND C29 1.0 U6 C18 0.1 U6 C30 0.1 U4 C19 0.1 U5 C20 0.1 U7 C21 0.1 U8 C31 0.1 U9 C32 0.1 U10 C33 0.1 +5VD
FB1 +5VA + C16 10µF AGND +12V + C13 10µF AGND + C14 10µF -12V C23 0.1 U1 C22 0.1 C26 1.0
U6 C17 0.1 U2 C24 0.1 C25 0.1
U6 C27 0.1
+5VA AGND AND DGND ARE CONNECTED AT A SINGLE POINT UNDER THE HI5710
ALL UNUSED INPUTS ON U8 AND U10 ARE GROUNDED
FIGURE 12. SCHEMATIC TABLE 6. PARTS LIST ITEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 QUANTITY 1 12 7 5 2 2 1 1 2 2 4 4 5 4 3 1 4 2 3 1 1 1 2 1 1 CONN1 C1, C4, C12, C19, C20, C21, C22, C23, C24, C25, C31, C32 C2, C3, C17, C18, C27, C30, C33 C5, C13, C14, C15, C16 C6, C7 C8, C9 C10 C11 C26, C29 FB1, FB2 JP1, JP2, JP3, JP4 JP5, JP6, JP7, JP8 J1, J2, J3, J4, J5 P1, P2, P3, P4 R1, R2, R12 R3 R4, R13, R14, R15 R5, R6 R7, R8, R9 R10 R11 R16 R17, R18 R19 SW2 REFERENCE 2x13 Pin Header 0.1µF 0.1µF Chip Cap 0805 10µF 0.01µF 1.0µF Chip Cap 1206 Not Used 100pF 1.0µF Ferrite Bead 1x2 Pin Header 1x3 Pin Header BNC 10K 1K 24 51 20 5K 88.7 681 3K 4.75K 15K SPST Push Button Switch, Momentary PART
Application Note 9511
TABLE 6. PARTS LIST (Continued) ITEM 26 27 28 29 30 31 32 33 34 35 QUANTITY 1 1 1 2 2 1 1 1 1 1 U1 U2 U3 U4, U11 U7, U5 U6 U8 U9 U10 SW1 REFERENCE HA5020 CA158A REF03 74HC541 74HC74 HI5710 74HC00 74HC221 74HC04 Not Used PART
FIGURE 13. SILKSCREEN
Application Note 9511
FIGURE 14. COMPONENT SIDE
FIGURE 15. SOLDER SIDE
Application Note 9511
FIGURE 16. GROUND PLANE
FIGURE 17. POWER PLANE