Harris Data Acquisition Author: Huckabee Using HI5710 Evalua

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Harris Data Acquisition Author: Huckabee Using HI5710 Evalua

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AN9511
Harris Data Acquisition
Author: Huckabee
Using HI5710 Evaluation Board
Description
HI5710 evaluation board designed help ease evaluation HI5710 (10-bit, MSPS) analog-to-digital converter (ADC). board includes clock driver circuitry, external reference voltage generator, data output buffer, calibration circuit, coupled analog inputs. HI5710 requires external reference voltage sources, VRT. typically 2.0V 4.0V respectively. Both chip enable, output enable, pins provided reduce power consumption flexibility. digital outputs inverted inputs LINV MINV, where LINV controls outputs through MINV controls output (MSB). This allows outputs straight binary, inverted binary, two's complement inverted two's complement. HI5710 also includes test mode, controlled TESTMODE input pin, where output data bits held known fixed logic levels facilitate in-circuit testing, Table
HI5710 Theory Operation
HI5710 CMOS converter designed 1.4µm CMOS process. illustrated functional block diagram, Figure HI5710 2-step converter featuring 5-bit upper comparator group 5-bit lower comparator group along with error correction output latches. This design requires fewer comparators than typical flash converters thereby lowering power dissipation. internal calibration mode used improve linearity. calibration mode controlled user. operation part depicted timing diagram Figure There cycle clock delay from analog input sampling point corresponding digital output data.
Layout Power Supplies
HI5710 evaluation board four layer board with layout optimized best performance ADC. internal layers power ground with analog digital planes separated. ground planes connected
Evaluation Board Block Diagram
CLOCK
1/16 2.5V 2.0V 4.0V 2.0V RESET
HI5710
INPUT INPUT DOUT
DATA
-12V
+12V
+5VA
+5VD
FIGURE
Copyright
Harris Corporation 1995
Application Note 9511 Functional Block Diagram
COURSE CORRECTION LATCH (MSB)
COURSE COMPARATOR ENCODE FINE COMPARATOR ENCODE
FINE LATCH
CALIBRATION UNIT
(LSB) MINV LINV TESTMODE
TIMING
RESET
FIGURE HI5710 FUNCTIONAL BLOCK DIAGRAM
Timing Diagrams
tPW1 tPW0
1.65V CLOCK ANALOG INPUT DATA OUTPUT
1.65V
1.65V (DVDD 3.3V) 2.5V (DVDD 5.0V)
INDICATES POINT WHICH ANALOG DATA SAMPLED
FIGURE HI5710 TIMING DIAGRAM
Application Note 9511 Timing Diagrams (Continued)
TABLE OUTPUT DATA FORMAT TESTMODE NOTES: This table shows output state combination TESTMODE, LINV, MINV states. Non-Inverted Output. Inverted Output.
10ns MORE 10ns MORE
LINV
MINV
10ns MORE CLOCK
RESET CLOCK MORE CLOCK MORE (SEL (SEL
FIGURE CALIBRATION TIMING DIAGRAM
Calibration Block Diagram
CLOCK 1/16
COUNTER
FIGURE CALIBRATION BLOCK DIAGRAM
Application Note 9511
point under ADC. Figures through include schematic board, board layout, various board layers. order optimize performance HI5710 power AVDD DVDD driven from separate supplies. supplies board should driven individual clean linear regulated supplies. They hooked with external gauge wires holes marked +5VD, +5VA, +12V, -12V, DGND, AGND prototype area. supply grounds together back supplies this will create ground loop create additional noise. analog digital supplies should connected together prevent chance latch only supply desired analog digital power then connect +5VA +5VD supplies together connect DGND supply ground, letting AGND float. real difference room temperature performance been observed when using either supply connection. digital supply from 3.3V 3.3V, digital outputs HI5710 generate less radiated noise, have less drive capability. digital outputs will only swing DVDD. evaluation board uses CMOS logic allow user vary digital supply without having change logic devices. operating conditions evaluation board power supplies listed below.
TABLE POWER SUPPLY REQUIREMENTS POWER SUPPLY +5VD +5VA +12V -12V CURRENT 27mA 30mA 18mA 12.5mA
options, coupled. VIN1 (J2) coupled input. This input uses gain input provide offset (P2) center input between bottom reference voltages.
coupled HI5710 through VIN2 (J1) applied HI5710. provides necessary bias center input between bottom reference voltages.
Calibration
HI5710 built-in calibration circuit minimize linearity error. RESET inputs should timed required both RESET inputs thethey must stay least clock period. negative pulse RESET input should occur before input sees falling edge. This sets initial calibration value. calibration starts rising edge clock after falling edge pulse requires pulses complete calibration. RESET input serves minimize calibration time, mandatory that used. RESET input must remain high state when use. calibration, when executed without RESET pulse, requires calibration pulses. calibration cycle completed clock cycles. Seven clock cycles after calibration pulse, calibration circuit takes exclusive possession lower comparators, through four clock cycles. During this time, outputs latched with previous data (cycle seven data). upper bits, through will operate usual during calibration input held high, making HI5710 converter during last four clock cycles calibration. input low, upper bits latched with previous data (cycle seven data) during last four cycles calibration lower bits.
+4.75V +4.75V +8.0V -15.0V
+5.0V +5.0V +12.0V -12.0V
+5.25V +5.25V +15.0V -8.0V
calibrate HI5710 evaluation board press SW2, momentary push button switch, after powering board. This will allow divided clock pass through following discussion refer board schematic. NAND gate (U8) until monostable multivibrator (U9) HI5710 requires reference voltages: VRB. times out. actual designs, this probably good evaluation board provides required external design copy, since monostables noise sensitive. references applie theto part setting jumpers When supplies turned multivibrator usually (installed factory). REF03 reference (U3) triggered this design. observe HI5710 uncaligenerates 2.5V which buffered amps (U2). brated state, remove high 2.0V ±2mV adjusting then adjusted before powering board. reference voltage +4.0V ±2mV. HI5710 Figure illustrates another possible circuit generate best performance when these voltages. calibration pulses.
Reference Circuit
Analog Input
analog input HI5710 configured various ways depending input signal required level performance. input capacitance input buffer necessary, input should driven from impedance source. evaluation board input
Another possible method composite video applications would horizontal sync initiate pulse input. 20MHz clock calibration time only 550ns, therefore data lost during calibration while digital outputs latched. Figure HI5710 datasheet.
Application Note 9511 Chip Enable Input
HI5710 chip enable/disable input, that puts part into power standby mode when pulled high. supply current drops from 30mA less than during standby. input evaluation board tied ground through resistor. This keeps part enabled allows users test connecting pulse generator (J4) input. MINV LINV inputs. This feature used in-circuit testing digital bus.
Increased Accuracy
Further calibration done when using external reference input buffer circuit. First, precision voltage equal ideal VIN-FS applied HI5710 input through JP3. then adjusted until transition occurs digital output. Finally, voltage equal ideal VIN+FS applied. then adjusted until 1022 1023 transition occurs digital output.
Output Enable Input
output enable, input when held enables digital outputs. When held high, digital outputs 3-stated, Figure input evaluation board tied ground through resistor. This keeps output enabled allows users test connecting pulse generator (J5) input. Typical enable/disable times listed Table
TABLE OUTPUT ENABLE/DISABLE TIMES PART HI5710 tPZL 15ns tPLZ 25ns tPZH 15ns tPHZ 25ns
Input Clock Driver Timing
clock input evaluation board requires CMOS logic levels. Note that threshold level will change with digital supply voltage. (75HC04) will buffer clock input drive HI5710. optimum performance HI5710 duty cycle clock should kept ±5%. (74HC541) buffers digital outputs. Figure shows timing evaluation board. data corresponding particular sample will available output HI5710 after required data latency cycles) plus output delay. Table lists values that expected various timing delays. Refer appropriate datasheets additional timing information.
TABLE EVALUATION BOARD TIMING PARAMETER DESCRIPTION HI5710 Data Delay 74HC04 Prop Delay 74HC541 Prop Delay 18ns 30ns
Digital Outputs
digital outputs CMOS outputs. LINV input will invert outputs through MINV will invert output (MSB). This allows user output number different digital formats. digital supply from +3.3V +5.0V. digital output will generate less radiated noise using +3.3V, outputs will have less drive capability. digital outputs will only swing DVDD, therefore exercise care interfacing logic when using +3.3V supply. output also fixed, defined state, Table setting TESTMODE low, outputs defined digital pattern. This pattern varied
tPD1, tPD2
17ns
tPD3
23ns
1.65V (DVDD 3.3V) 2.5V (DVDD 5.0V) DATA ENABLE (OE)
tPLZ tPHZ
tPZL tPZH 1.65V (DVDD 3.3V) 2.5V (DVDD 5.0V)
DATA OUTPUT
ACTIVE
HIGH IMPEDANCE
FIGURE ENABLE/DISABLE TIMING
Application Note 9511
CLOCK INPUT (J3) tPD1 HI5710 CLOCK INPUT
D0-D9 OUTPUT
DATA tPD2
DATA
CONN1 (74HC04) tPD3
DOUT0-DOUT9 (74HC541)
DATA
DATA
FIGURE INPUT-TO-OUTPUT TIMING
HI5710 Characterization
Various tests used characterize performance HI5710. integral nonlinearity (INL) differential nonlinearity (DNL) specs considered measure frequency characteristics converter. These parameters evaluated factory using histogram approach with frequency ramp input. Further dynamic testing used evaluate HI5710 performance input starts approach nyquist Among these tests Signal-to-Noise Ratio (SNR), Signalto-Noise Distortion (SINAD), Total Harmonic Distortion (THD). Coherent testing recommended order avoid inaccuracies windowing. Coherent sampling governed following relationship: Where frequency input tone, sampling frequency, number samples, number cycles over which samples taken. making integer prime samples assured being nonrepetitive. Figure shows test system used dynamic testing HI5710. clock (CLK) analog input (VIN) signal sources derived from phase noise HP8662A generators that phase locked each other ensure coherence.The output generator that drives analog input evaluation board first passed through bandpass filter improve spectral purity signal. data captured logic analyzer then transferred over GPIB software perform Fast Fourier Transform (FFT) required data analysis. Bandwidth accurate used bandwidth testing. input sine wave peak-to-peak amplitude equal reference voltage. analog input frequencies 1kHz beat frequency generated output DAC. Full power bandwidth frequency which amplitude digitally reconstructed output down from frequency value. Settling Time HI5710 well suited applications. settles 34ns LSBs 35ns response 6MHz input pulse with rise time 12MHz clock rate. application, waiting 35ns after rising edge falling edge) data acquired will settled with LSB. Video Testing characterize HI5710 NTSC video performance test setup Figure used. 12-bit reconstruction used evaluate differential gain differential phase.
Acknowledgments
Thanks Gary Smith assistance.
References
AN8906, Noise Aspects Applying Advanced CMOS Semiconductors. AN9102, Noise Aspect Applying Advance CMOS Semiconductors. AN9214.2, Using Harris High Speed Converters. AN9313.1, Circuit Considerations Imaging Applications. Michael Felix, "Differential Phase Gain Measurements Digitized Video Signals", SMPTE Journal, 85:76-79,February 1976. Frederick Williams Richard Olsen, "Quantization Effects Differential Phase Gain Measurements", SMPTE, Nov. 1982. Bartlett, "Quantization Effects when Differential Gain", IMTC, 366-368, 1992.
Testing
Application Note 9511
PHASE HP8662A LOCK HP8662A HP8662A
PULSE GENERATOR
BAND-PASS FILTER
PULSE GENERATOR
VIDEO GENERATOR
HI5710 EVALUATION BOARD HI5710 HI5710 EVALUATION BOARD
HI5710
LOGIC ANALYZER GPIB OSCILLOSCOPE OSCILLOSCOPE VM700A ANALYZER
FIGURE COHERENT TEST SYSTEM
FIGURE VIDEO TEST SYSTEM
TABLE FACTORY BOARD SETTING VRT, external reference. VRB. external reference. Coupled Input. Jumper installed. Coupled Input. Jumper Installed. MINV: Jumper Logic Low. Normal Output. LINV: Jumper Logic Low. Normal Output. TESTMODE: Jumper Logic High. Normal Outputs. SEL: Jumper High. Normal Data Output. give 3.0V JP4. give 3.0V JP3. give 2.0V jumper give 4.0V jumper
Application Note 9511 Schematic
+5VA REF03 VOUT TRIM GAIN +12V 4.0V
CA158A -12V 0.01
+12V 2.0V
CA158A 0.01
-12V +12V
HA5020 VIN1 88.7 VIN2 10µF -12V
+5VA
FIGURE SCHEMATIC
Schematic
CD74HC04 CD74HC04 74HC541 CONN1
U10B
CLOCK
U10A
DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
+5VD +5VD +5VD +5VA +5VA
CHIP ENABLE +5VA +5VA +5VA +5VA RESET DVDD DVDD +5VD
MINV LINV TESTMODE
DGND
AVDD AVDD AVDD
OUTPUT ENABLE
Application Note 9511
DVSS DVSS DVSS HI5710 74HC00 INVERTED NORMAL INVERTED NORMAL
+5VD
100pF
TSTR AVSS AVSS AVSS AVSS AVSS
CEXT
REXT/CEXT
+5VD +5VD 74HC74 74HC74 +5VD +5VD 74HC541
4.75K
74HC221
+5VD
+5VD
+5VD
CEXT
+5VD +5VD 74HC74 74HC74 +5VD
4.75K
REXT/CEXT 74HC221
+5VD
+5VD
TESTMODE NORMAL DEFINED STATE DATA NORMAL LATCHED
FIGURE SCHEMATIC
Application Note 9511 Schematic
+5VD 10µF DGND +5VD
+5VA 10µF AGND +12V 10µF AGND 10µF -12V
+5VA AGND DGND CONNECTED SINGLE POINT UNDER HI5710
+12V
-12V
UNUSED INPUTS GROUNDED
FIGURE SCHEMATIC TABLE PARTS LIST ITEM QUANTITY CONN1 C12, C19, C20, C21, C22, C23, C24, C25, C31, C17, C18, C27, C30, C13, C14, C15, C26, FB1, JP1, JP2, JP3, JP5, JP6, JP7, R13, R14, R17, REFERENCE 2x13 Header 0.1µF 0.1µF Chip 0805 10µF 0.01µF 1.0µF Chip 1206 Used 100pF 1.0µF Ferrite Bead Header Header 88.7 4.75K SPST Push Button Switch, Momentary PART
Application Note 9511
TABLE PARTS LIST (Continued) ITEM QUANTITY REFERENCE HA5020 CA158A REF03 74HC541 74HC74 HI5710 74HC00 74HC221 74HC04 Used PART
FIGURE SILKSCREEN
Application Note 9511
FIGURE COMPONENT SIDE
FIGURE SOLDER SIDE
Application Note 9511
FIGURE GROUND PLANE
+5VA
FIGURE POWER PLANE

Harris Data Acquisition Author: Huckabee Using HI5710 Evalua

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