OCX160's RapidConfigure (RC) interface offers high-speed method progra
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OCX160 RapidConfigureInterface FPGA
OCX160's RapidConfigure (RC) interface offers high-speed method programming Buffers (IOBs) configuring crosspoint switch connections. parallel interface allows commands sent OCX160 much faster than JTAG interface used. interface consists data control signals. Figure shows interface signals. Refer OCX160 Data Sheet more detailed description RapidConfigure interface. This document describes design FPGA provide interface between parallel printer port OCX160 RapidConfigure Interface.
RCA[6:0]
OCX160 Rapid Configure Interface
RCB[6:0]
RCO[4:0]
RCI[3:0] RC_EN# UPDATE# RC_CLK#
Figure
RapidConfigure Interface Signals
2002
AN500755
OCX160 RapidConfigure Interface FPGA
FPGA Architecture
FPGA divided into several modules that control different aspects design. Figure shows block diagram data paths within FPGA. There major interfaces that must considered:
Enhanced Parallel Port (EPP) interface, which connects FPGA host RapidConfigure (RC) interface, which connects FPGA OCX160.
Interface
UPDATE#
Interface
EPP_BLOCK
EPP_DATA
EPP_AS EPP_DS
WR_DATA Handles Data buffering strobe signals.
RCLOAD DATA
RCLOAD_FIFO_WR
RCLOAD FIFO
512x32 FIFO used storing RapidConfigure commands prior their being sent OCX160.
RCLOAD_RDEN RCREAD_WREN RC_ERROR
RCLOAD DATA
RCLOAD EMPTY2 RCLOAD_FIFO_RD
RD_DATA
RCLOAD_CLR
REG_BLOCK
EPP_LATCH EPP_DRIVE
RCLOAD_FIFO_FULL RCLOAD_FIFO_EMPTY
RC_IF
Controls RapidConfigure interface OCX160 interfaces both FIFOs.
Contains control status registers. Controls interface RCLOAD RCREAD FIFOs.
DREG_RD
RC_EN#
EPP_WAIT EPP_WR_N
EPP_SM
State Machine generate Address Data Read Write Strobes.
RCREAD DATA
RCREAD_FIFO_RD RCREAD_CLR RCREAD_FIFO_FULL RCREAD_FIFO_EMPTY
RCREAD FIFO
DREG_WR AREG_RD AREG_WR EPP_ERROR
512x32 FIFO used RCREAD_FULL2 storing data RCREAD_FIFO_WR received from OCX160 during RapidConfigure RCREAD DATA readback commands.
Figure
FPGA Block Diagram
EPP_BLOCK EPP_SM modules handle interfacing host through parallel port. interface consists 8-bit bi-directional data four control signals. control signals Address Data Strobe signals. These signals driven host signal beginning cycle. Address Strobe asserted, address read write cycle starting; Data Strobe asserted, data cycle starting. EPP_WR_N signal driven host indicate operation read write cycle. FPGA samples state EPP_WR_N signal beginning every cycle. EPP_WR_N held during write operation high during read operation. last control signal, EPP_WAIT, handshaking signal driven FPGA. EPP_BLOCK module performs main functions:
Buffering Address Data Strobe signals synchronizing them FPGA clock. Controlling 3-STATE buffers data bus.
AN500755
2002
OCX160 RapidConfigure Interface FPGA
FPGA only drives data during portion read cycle. control signal EPP_DRIVE driven EPP_SM block. EPP_LATCH signal control signal from EPP_SM block that instructs EPP_BLOCK latch data into FPGA during write cycle. EPP_BLOCK transfers write data onto WR_DATA bus, which connected REG_BLOCK module. read cycle data pulled from RD_DATA bus, which driven REG_BLOCK. EPP_SM module state machine that decodes cycles generates internal read write strobes REG_BLOCK. also generates EPP_WAIT handshake signal that driven back host monitors state strobe signals EPP_WR_N signal determine which type cycle under way, then generates appropriate strobe signal REG_BLOCK module. example, Data Strobe asserted EPP_WR_N low, then Data write cycle starting. this case EPP_SM module would assert DREG_WR strobe signal REG_BLOCK module. EPP_SM module asserts EPP_ERROR signal REG_BLOCK when detects that error occurred during cycle. detected errors relate protocol. example, strobe signal high when should error signal will asserted. REG_BLOCK module contains registers that control aspects FPGA's operation. also contains status registers that read host verify state FPGA FIFOs. Address Register contained within REG_BLOCK module. Address Register pointer that used Data cycles. When Data read write cycle executed, REG_BLOCK decodes value stored Address Register determine which register read write. Address Register, like other registers within REG_BLOCK, 8-bits wide allows addressing 8-bit data registers. accesses Address Register Address Strobe signal opposed Data Strobe) allows reading writing just other register. FIFO Control register manages interfaces between REG_BLOCK module RCLOAD RCREAD FIFOs. contains bits that enable disable both reads from writes FIFOs. also clear contents FIFOs. Global Status register allows host receive information about status different parts FPGA. Bits within Global Status register indicate status FIFOs, whether they empty full. also contains error that EPP_SM module. error occurs during cycle, error set. Reset register allows host reset different portions EVB. reset connected output FPGA, which connected OCX160's reset circuit. Setting this will reset OCX160. Another reset allows FPGA reset default state.
2002
AN500755
OCX160 RapidConfigure Interface FPGA
RCLOAD RCREAD FIFOs also appear registers host However, REG_BLOCK module must handle accesses FIFOs differently than accesses other registers. FIFOs both 32-bits wide words deep. Since interface only 8bits wide, four reads writes required complete transaction from FIFOs. REG_BLOCK module keeps track writes RCLOAD FIFO reads from RCREAD FIFO, assembles data properly that loaded/read to/from FIFOs without errors. only requirement that four consecutive operations must performed when accessing FIFOs. Therefore, four consecutive writes RCLOAD FIFO address required write complete 32-bit word data into RCLOAD FIFO. fewer than four accesses performed, EPP_SM module will assert EPP_ERROR REG_BLOCK module informing host error. RC_IF module interfaces OCX160. reads RapidConfigure commands from RCLOAD FIFO then drives them onto interface. Readback command sent OCX160, FPGA waits OCX160 respond with read data. latches data from OCX160 writes word data into RCREAD FIFO. RC_IF module controlled registers within REG_BLOCK module. instance, RCLOAD_RDEN (Read Enable) signal must asserted REG_BLOCK module order RC_IF module able generate read strobes RCLOAD FIFO. When RCLOAD_RDEN signal asserted, RC_IF module allowed fetch commands from RCLOAD FIFO, thereby filling FIFO with commands. When RCLOAD_RDEN signal asserted host writing appropriate FIFO Control register), RC_IF module will read commands RCLOAD FIFO until FIFO empty. When Readback operation performed, read data from OCX160 written RCREAD FIFO. RCREAD FIFO will eventually fill host fails read data out. Once FIFO full, additional read data from OCX160 will lost. same true with respect RCLOAD FIFO other direction. instance, reads from RCLOAD FIFO disabled (RCLOAD_RDEN de-asserted), more than commands loaded into RCLOAD FIFO, additional commands will lost.
FPGA Device Requirements
Fairchild Semiconductor implementation OCX160 FPGA uses Altera 10K50E-1 device. This part chosen reasons. high performance series parts required order exercise RapidConfigure interface high speeds. Altera FPGAs also contain embedded elements that configured dual port FIFOs. These ready-made logic blocks easy implement meet design requirements perfectly. FPGA design utilizes approximately routing resources 10K50E with optimizations. able RapidConfigure interface clock speeds MHz. design been targeted other device, that does mean that 10K50E only option.
AN500755
2002
OCX160 RapidConfigure Interface FPGA
Summary
FPGA simple efficient build interface between microprocessor OCX160 RapidConfigure Interface. high performance FPGAs allow RapidConfigure Interface much higher speeds than could achieved using microcontroller's general purpose pins. Plus, FPGA's built-in FIFOs provide means store string commands prior sending them device. FPGA with embedded block could also used build simple PCI-to-RapidConfigure bridge function. flexibility FPGAs make them excellent choice when designing with OCX160 using RapidConfigure Interface.
Related Documents
OCX160 Datasheet OCX160 Register Programming Manual OCX160 Starter Manual OCX160 Layout Guidelines Application Note OCXPro Software User's Guide
2002
AN500755
OCX160 RapidConfigure Interface FPGA
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuity specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATIONS. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
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AN500755
2002
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