Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Ad

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Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F AN-0123
Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F
INTRODUCTION IEEE Std. 1149.1 (JTAG) defines standard Test Access Port (TAP), protocol commands built test both chip board level. board designed with boundary scan components typically consists scan chain which daisy-chain (TDO TDI) components board. While single scan chain solution might adequate testing board production single-board system, adequate when multi-board system requires interconnects between boards tested after system integration. number methods available accessing system level boundary scan nets. Traditional methods included using multi-channel tester physically access each board, using single tester connection with each board's traces daisy chained together multiplexing pins running each board. alternative approach implement addressable test access controller such SCANPSC110. SCANPSC110 eliminates shortcomings traditional methods while also providing capability partition single board level scan chain into smaller chains. While possible separate cables each board during production test, becomes unwieldy quickly number boards increase. Furthermore multiple port solution practical with embedded test. Even though daisy chaining multiple boards together simple, several drawbacks exist. example, ATPG software multiple-board system views system were board. system scales upward, number
Fairchild Semiconductor Application Note 1023 February 1996
NETS become large will number length serial test vectors required. When board missing empty backplane, fault occurs boundary scan infrastructure boards, entire system becomes untestable. multiplexed scheme works well partitioning system giving board test access through single test port. But, does scale well backplane, there provision backplane interconnect testing. Backplane interconnect testing required ability park board Pause-DR/IR states (See Section Figure Scan Databook explanation states) while accessing another board. also requires means performing system wide updates scan commands data. PSC110F solution provides simple means tying independent scan chains from multi-board systems together selectively accessing them. six-bit addressing scheme allows bridges single backplane. Test vectors generated testing individual boards used testing boards after system integration well embedded test field. partitioning achieved using PSC110F will automatically isolate faults down board level with diagnostics. multiple local scan ports (LSP) allow additional partitioning scan chains within board. Backplane interconnect testing enabled through PARKPAUSE command broadcast addressing feature. ATPG software easily implemented available through multiple venders.
AN012144-1
FIGURE Single Board Boundary Scan Implementation
1998 Fairchild Semiconductor Corporation
AN012144
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AN012144-2
FIGURE SCANPSC110F Multidrop Configuration SCANPSC110F APPLICATION EXAMPLE more information this application example, refer AN-1037 "Embedded IEEE 1149.1 Test Application Example." Consider system with multidrop backplane. general there slots. Some slots populated with cards, others empty. There many different card types that used with this backplane, there multiple cards same type used within this backplane given configuration. backplane architecture this example quite simple. Each slots receive same multidrop backplane signals. There active components backplane. However, there passive pull-up resistors hold backplane signals high when 3-stated. system test bus, (TDO_BP, TDI_BP, TMS_BP, TCK_BP, TRST_BP* (Asynchronous active input)), also connected each slot multidrop configuration. Each card PSC110F connected system test bus, boundary scan interface (IEEE 1149.1 compliant drivers, latches, transceivers such SCAN18540T, SCAN18373T, SCAN182245T) connected system backplane. SYSTEM WIDE INFRASTRUCTURE TEST Infrastructure testing always first test that must performed. system level, infrastructure test consists verification determination backplane configuration then testing connectivity, identity functionality components that make output scan chains which interface with PSC110F LSP's. VERIFICATION DETERMINATION BACKPLANE CONFIGURATION This test sweeps entire address range PSC110F reads captured value from instruction register selected PSC110F. PSC110F instruction register will capture value "XXXXXX01", where "XXXXXX" represents assigned address slot inputs. value scanned back matches outgoing address, PSC110F been selected. scanned back value "11111111"would indicate that there PSC110F outgoing address, such case empty slot. These results used ways: exact system configuration known test time, which often case production, results address range sweep compared known configuration. PSC110F found address where there should have been one, PSC110F found address where there should have been one, tester will report failure. system configuration unknown test time, results from address range sweep compared database containing possible boards determine what board types present current configuration system. Later when interconnect testing cards backplane performed, this predetermined configuration used select proper tests specific configuration. LOCAL SCAN PORT INSTRUCTION TEST After system configuration verified determined, test circuitry each card must tested. This done addressing each PSC110F unparking each LSP's, scanning back value captured Instruction Registers each component local chains. captured value "01" least significant bits represents functioning boundary scan component. some cases remaining bits Instruction Register capture used encode pseudo code (e.g., components like Fairchild's SCAN18XXXT, SCAN18XXXA), used test correct component placement. Optionally, device identification register checked each boundary scan component cards check correct component placement. 18-bit SCAN Test Access Logic SCAN18XXXA family includes optional register, some earlier boundary scan components were equipped with register.
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BOARD LEVEL INTERCONNECT TESTING SCANPSC110F individual boards cards have already been tested during production. Re-testing after system integration optional, makes good check. case embedded test that will used power self test periodic field testing, running go/no-go board level tests will enable built-in diagnostics down board level. PSC110F Selection Configuration Select PSC110F scanning address into PSC110F Instruction Register. Configure Mode Register appropriate local serial port network configuration board test. board only scan chain connected LSP1, default configuration will appropriate. there multiple chains connected multiple LSPs board with interconnects running between components different chains, appropriate unpark multiple LSPs form what looks like larger chain. network configuration performed Scanning MODESEL command into selected PSC110F's Instruction Register. Scanning appropriate value into Mode register selected PSC110F. Unpark scanning UNPARK command into instruction register selected PSC110F. Once PSC110F selected LSPs unparked, connection made between tester target scan chains. remainder board test consists same commands test data that would used testing board without PSC110F with exception: data PSC110F Instruction Register, Bypass data register, bits, must added serial vectors. remaining steps board test are: Scan SAMPLE/PRELOAD command into target devices BYPASS command PSC110F. Scan first test vector into boundary registers target devices.
Scan EXTEST command into target devices BYPASS command PSC110F. Scan next vector into target devices; captured results from previous vector shifted this vector shifted This step repeated until test vectors this board have been exercised. Scan GOTOWAIT command into PSC110F instruction registers return PSC110F Wait-For-Address state where next card addressed. BACKPLANE INTERCONNECT TESTING Testing backplane similar testing NETS within board with exception. nodes backplane NETS terminate components that connected different PSC110F. (See Figure example order test lines multidrop backplane, say, with cards, each card connected test PSC110F. PSC110F provides address information. PSC110F's LSPs (local scan ports) connected backplane driver, such Fairchild's SCAN Test Access Logic, SCAN182245A. These drivers, turn, connected backplane itself, thereby provide scan test operations backplane interconnect testing. Boundary scan ATPG software generates patterns with assumption that output cells components connected will updated simultaneously. This assumption allows node drive during pattern another node drive same during pattern update happen simultaneously nodes, there could significant periods contention between multiple outputs NET. Therefore, Update-IR EXTEST command Update-DRs between patterns vectors (while EXTEST active command) must performed simultaneously boards using broadcast address order select PSC110Fs backplane. general, shifting operations must done addressing PSC110F time.
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AN012144-3
FIGURE Backplane Interconnect Test Flow
AN012144-4
PSC110F local scan ports. port connected backplane drivers. other partition resident board.
FIGURE Testing Backplane Interconnects
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detailed description flow backplane interconnect test follows. Reset PSC110F: This performed forcing TRST clocking TCK_BP five times while holding TMS_BP high. Configure/Preload: Preload boundary scan registers components connected backplane signals each card with first test pattern, shift EXTEST command into Instruction Registers components that interface with backplane signals. Select PSC110F scanning address into PSC110F Instruction Register. Configure Mode Register unpark that interfaces backplane logic. This necessary LSP1 used (default configuration). Unpark scanning UNPARK command into Instruction Register selected PSC110F. Scan SAMPLE/PRELOAD command into target devices PARKPAUSE command PSC110F. Scan first test vector into boundary registers target devices. state sequence should from Shift-DR Exit1-DR through Pause-DR state, after shifting test vector, avoid parking Pause-DR state (see PARKPAUSE command SCANPSC110F data sheet). Shift EXTEST command into target devices GOTOWAIT command PSC110F. state sequence should from Shift-IR Exit1-IR Update-IR, after shifting commands, that active will parked Pause-IR state. Repeat each board involved with backplane test. Execute EXTEST Command: EXTEST command updated backplane components simultaneously avoid significant periods contention that would result from executing EXTEST command board time. Select PSC110F scanning broadcast address into PSC110F Instruction Registers. Scan UNPARK command into Instruction Register selected PSC110F. will actually unparked until backplane sequenced back into Pause-IR state, while UNPARK command active. Scan PARKPAUSE command into PSC110F instruction register. state sequence should from Shift-IR Exit1-IR through Pause-IR
state, after shifting PARKPAUSE command. will unpark upon entering Pause-IR state. EXTEST command previously been shifted into Instruction Registers target devices will become active insruction once unparked sequenced through Update-IR state. Capture logic values inputs target devices park Pause-DR state sequencing backplane TAP's through Capture-DR Exit1-DR Update-DR. Scan GOTOWAIT command into PSC110F Instruction Registers. Shift Test Data: Test results from previous pattern shifted while next pattern shifted into boundary registers components each board system. Ater data shifted, parked Pause-DR state that boundary register contains data, updated value output cell. Select PSC110F scanning address into PSC110F Instruction Register. Scan PARKPAUSE command into Instruction Register selected PSC110F. (The PARKPAUSE command used unpark well park LSP). Sequence backplane TAPs into Pause-DR state order unpark LSP. From Pause-DR state, transition Exit2-DR Shift-IR, where next test vector shifted into target devices, then Exit1-DR Update-DR. will reparked PAUSE-DR state when transitioning from Exit1-DR Update-DR, because PARKPAUSE command still active. Scan GOTOWAIT command into PSC110F Instruction Registers. Repeat each board involved backplane test.
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AN-0123 Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Addressable JTAG Port, SCANPSC110F
Drive/Capture: PSC110F selected their LSPs that interface backplane components unparked sequenced through Update-DR Capture-DR states. Select PSC110F scanning broadcast address into PSC110F Instruction Registers. Scan PARKPAUSE command into Instruction Register selected PSC110F. Sequence backplane TAPs Pause-DR state order unpark LSP. Sequence from Pause-DR state through Update-DR through Capture-DR Exit1-DR Update-DR. This will execute next vector repark Pause-DR state. Scan GOTOWAIT command into PSC110F Instruction Registers. Shift Test Results from Last Vector: test results from last vector shifted while shifting safe dummy vector, that 3-states bus. Select PSC110F scanning address into PSC110F Instruction Register.
Scan PARKPAUSE command into Instruction Register selected PSC110F. (The PARKPAUSE command used unpark well park LSP). Sequence backplane TAPs Pause-DR state order unpark LSP. From Pause-DR state, transition Exit2-DR Shift-IR, where results last test vector shifted out, Exit1-DR Update-DR. will reparked Pause-DR state when transitioning from Exit1-DR Update-DR, because PARKPAUSE command still active. Scan GOTOWAIT command into PSC110F Instruction Registers. Reset Test Logic: This performed clocking TCK_BP eight times while holding TMS_BP high. takes three clocks reset PSC110F from Run-Test/Idle state five more reset target components from Pause-DR state. general, takes five TCK's each level test hierarchy.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Europe Fax: 80-530 Email: europe.support@nsc.com Deutsch Tel: 141-35-0 English Tel: 793-85-68-56 Italy Tel: 5631
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Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.

Structural System Test IEEE Std. 1149.1 with Hierarchical Multidrop Ad

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