Vers. Bendels following Application note intended give some hints usin

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Vers. Bendels following Application note intended give some hints usin

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Notes using Converter FFMC8L/LC Microcontrollers Fujitsu Mikroelektronik GmbH
Vers. Bendels following Application note intended give some hints using converter FFMC8L/LC Microcontrollers. Figure shows basic diagram converter block.
P50/ ADST
(Main Clock 2^8) (Software Trigger) (AD-bit)
ADCK
Trigger selector
(CPU Clock)
Control Block
ADC1 ADC2
IRQx
AVcc AVss
Comp
IBUS
Data Sens Value Register
IBUS
analog input signal (AN0.ANx) passed analog multiplexer sample hold stage finally comparator. Analog digital conversion done comparing selected input signal with signal derived from converter using successive approximation approach. This means, once conversion started triggered, control block will first sample selected input channel keep voltage level stable sample hold stage. following conversion process, control logic will start setting Data register, which coupled converter. control logic check comparator, sampled voltage higher lower. lower, Data register cleared again, otherwise remains set. This process continues with succeeding bits Data register. When finished, converted value read from data register.
converter block also configured operate called Sense Mode which compare value written software into data register. this case, converter will simply determine input signal higher lower than compare vale. Note that converter block dedicated AVCC, AVSS inputs better noise performance. AVCC must equal higher than voltage applied between AVSS defines voltage range which converted.
Control Block contains registers configuring controlling converter operation. From software point view, there various options operate converter, like specifying conversion started, conversion determined, there some peculiarities take care about. following figure shows converter control registers MB89630 series. Some bits might differ other series, basic operation same.
ADC1
ANS3 ANS2 ANS1 ANS0 ADMV SIFM
Sofware Trigger Input Channel Selector Detect Higher Lower Voltage Sens Mode Conversion Progress flag Interrupt Flag: Conversion Terminated Sens Mode Detection
ADC2
ADCK ADIE ADMD TEST
(Production Test bit) Hardware Software Trigger Sens Mode Mode selection Interrupt Enable Hardware Trigger Selection (Input High Speed Main Clock)
Triggering Starting conversion Assuming input channel selected input multiplexer, there ways different ways actually start conversion. Software Trigger: Software Trigger selected setting EXT-bit conversion started setting bit. This will reset automatically. Hardware Trigger (High Speed Main Clock) Hardware Trigger selector Main Clock (ADCK Hardware Trigger active (EXT then converter started periodically clock derived from main clock oscillator. Note: this case, also main-clock gear function must select highest highest mainclock speed, otherwise this trigger method will work. Hardware Trigger (External Input P50/ADST) Hardware Trigger selector ADST Input (ADCK=1), Hardware Trigger active (EXT then converter started whenever there rising edge this input other controller series, instead this external input signal, possible on-chip timer start converter.
Detecting conversion Polling ADMV Probably simplest detecting conversion poll ADMV bit. conversion started either above mentioned methods, ADMV long conversion progress. Once becomes Data register read out. Polling ADI-bit could used similar ADMV-bit, explicitly cleared before conversion started. Once conversion finished this becomes reset software, this would remain even conversion started.) ADI-bit actually used generate interrupts, recommended utilize polling ADMV-bit method.
Interrupt Service Routine Call converter configured generate interrupts once conversion finished (ADIE assuming interrupt controller initialized (Interrupt Level Register) interrupts globally enabled (SETI instruction), then associated interrupt service routine (ISR) will called conversion. Especially conversion triggered using 1b), recommended that even interrupt service routine, ADMV tested waited become practice shown that this case, seems called before conversion completely finnished Then Data register read out. must cleared bevore leaving ISR.
Additional Notes Attempts read Data register before conversion finished will result erroneous data. Note that conversion started automatically periodic basis, polling software especially must able respond before conversion triggered next time, otherwise would read irrelevant data.
Sense Mode Operation sense mode operates similar above described converter with some differences: initialization task, compare-value written into Sense Value Register (which actually same Data register) specify compare voltage level. SIFM-bit specifies Sense Operation shall detect (set flag) selected analog input voltage higher than compare value, shall detect lower. Note that ADMV-bit function sense mode operation. sense mode activated triggerd same described converter mode. each trigger (and only each trigger), compare operation executed ADI-flag will condition specified SIFM met. Note that, condition time input voltage changed mean time such that condition would meet now, will require another trigger actually ADI-flag. Thus, sense mode mainly useful periodic hardware trigger modes 1c).
Using Sense Mode Power Down Mode Probably most interesting application Sense Mode voltage supervisory function which still active power down mode. Sense Mode detects special condition, will generate interrupt wake core take care about Well, requirement that converter Sense Mode triggered periodic base actually able detect condition. Thus, "Hardware Trigger High Speed Main Clock" method used only possible power down mode would (high speed) Main-Sleep mode. other power down modes this clock stops. alternative "Hardware Trigger (External Input)" method, which would also work SubSleep mode. other controller series, eg.g. MB89160, instead this external input, 16-bit timer used generate trigger signal. course, then also depends this timer, which power down modes operate.
Examples Some example programs have been developed (initially used figure these details mentioned above), based MB89630-EVAKIT extension board. program "ADC.c" demonstrates case mentioned 1a), .2a). program "ADCI.c" demonstrates case mentioned 1b). program "ADCE.c" demonstrates case mentioned 1c). finally "SENS.c" demonstrates sense mode based

Vers. Bendels following Application note intended give some hints usin

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