CMOS Single Chip 8-bit Microcontroller Description TEMIC's 8

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CMOS Single Chip 8-bit Microcontroller Description TEMIC's 8

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80C32/80C52
CMOS Single Chip 8-bit Microcontroller
Description
TEMIC's 80C52 80C32 high performance CMOS versions 8052/8032 NMOS single chip fully static design TEMIC 80C52/80C32 allows reduce system power consumption bringing clock frequency down value, even without loss data. 80C52 retains features 8052 bytes bytes lines three timers 6-source, 2-level interrupt structure full duplex serial port on-chip oscillator clock circuits. addition, 80C52 software-selectable
80C32 Romless version 80C52 80C32/80C52-L16 power version Freq 0-16 80C32/80C52-12 80C32/80C52-16 80C32/80C52-20 80C32/80C52-25 80C32/80C52-30
modes reduced activity further reduction power consumption. idle mode frozen while RAM, timers, serial port interrupt system continue function. power down mode saved other functions inoperative. 80C32 identical 80C52 except that on-chip ROM. TEMIC's 80C52/80C32 manufactured using SCMOS process which allows them from with TEMIC's 80C52 80C32 also available with
80C32/80C52-36 80C32-40 MHz* 80C32-42 MHz* 80C32-44 MHz*
70°C temperature range. other speed temperature range availability please consult your sales office.
Features
Power control modes bytes Kbytes (80C52) programmable lines Three timer/counters program memory space data memory space Fully static design 0.8µ CMOS process Boolean processor interrupt sources Programmable serial port Temperature range commercial, industrial, automotive, military
Optional
Secret Encryption Secret Identification number
MATRA Rev. Fev.
80C32/80C52
Interface
Figure Block Diagram
MATRA Rev. Fev.
80C32/80C52
Figure Configuration
P1.1/T2EX
P0.0/A0
P0.1/A1
P0.2/A2
P1.5 P1.6 P1.7 RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.3/A3
P1.0/T2
P1.4
P1.3
P1.2
P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7
80C32/80C52
PSEN P2.7/A14 P2.6/A13 P2.5/A12
XTAL2
XTAL1
/T2EX A1/P01 A2/P02 A3/P03 A0/P00
RxD/P30 TxD/P31 INT0/P32 INT1/P33 T0/P34 T1/P35
80C32/80C52
PSEN /A15 /A14 /A13
XTAL2
WR/P36
RD/P37
XTAL1
/A11
/A10
Flat Pack
Diagrams reference only. Package sizes scale.
/A12
P2.3/A10
P2.4/A11
P2.0/A7
P2.1/A8
WR/P3.6
RD/P3.7
P2.2/A9
MATRA Rev. Fev.
80C32/80C52
Description
5.1.
Circuit ground potential. Memory that addresses (MOVX @DPTR). this application, uses strong internal pullups when emitting 1's. During accesses external Data Memory that addresses (MOVX @Ri), Port emits contents Special Function Register. also receives high-order address bits control signals during program verification 80C52. Port sink/source three inputs. drive CMOS inputs without external pullups.
5.2.
Supply voltage during normal, Idle, Power Down operation.
5.3. Port
Port open drain bi-directional port. Port pins that have written them float, that state used high-impedance inputs. Port also multiplexed low-order address data during accesses external Program Data Memory. this application uses strong internal pullups when emitting 1's. Port also outputs code bytes during program verification 80C52. External pullups required during program verification. Port sink eight inputs.
5.6. Port
Port bi-directional port with internal pullups. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally being pulled will source current (ILL, data sheet) because pullups. also serves functions various special features TEMIC Family, listed below.
Port
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Alternate Function
(serial input port) (serial output port) INT0 (external interrupt INT1 (external interrupt (Timer external input) (Timer external input) (external Data Memory write strobe) (external Data Memory read strobe)
5.4. Port
Port bi-directional port with internal pullups. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally being pulled will source current (IIL, data sheet) because internal pullups. Port also receives low-order address byte during program verification. 80C52, Port sink/ source three inputs. drive CMOS inputs without external pullups. inputs PORT also used timer/counter P1.0 [T2] External clock input timer/counter P1.1 [T2EX] trigger input timer/counter reloaded captured causing timer/counter interrupt.
Port sink/source three inputs. drive CMOS inputs without external pullups.
5.7.
high level this machine cycles while oscillator running resets device. internal pull-down resistor permits Power-On reset using only capacitor connected VCC. soon Reset applied (Vin), PORT tied one. This operation achieved asynchronously even oscillator does start-up.
5.5. Port
Port bi-directional port with internal pullups. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally being pulled will source current (ILL, data sheet) because internal pullups. Port emits high-order address byte during fetches from external Program Memory during accesses external Data
5.8.
Address Latch Enable output latching byte address during accesses external memory. activated though this purpose constant rate oscillator frequency except during external data memory access which time pulse skipped. sink/source inputs. drive CMOS inputs without external pullup.
MATRA Rev. Fev.
80C32/80C52
5.9. PSEN
Program Store Enable output read strobe external Program Memory. PSEN activated twice each machine cycle during fetches from external Program Memory. (However, when executing external Program Memory, activations PSEN skipped during each access external Data Memory). PSEN activated during fetches from internal Program Memory. PSEN sink/source inputs. drive CMOS inputs without external pullup. FFFH). When held low, executes only external Program Memory. must floated.
5.11. XTAL1
Input inverting amplifier that forms oscillator. Receives external oscillator signal when external oscillator used.
5.12. XTAL2
Output inverting amplifier that forms oscillator. This should floated when external oscillator used.
5.10.
When held high, executes internal Program Memory (unless Program Counter exceeds
Idle Power Down Operation
Figure shows internal Idle Power Down clock configuration. illustrated, Power Down operation stops oscillator. Idle mode operation allows interrupt, serial port, timer blocks continue function, while clock gated off. These special modes activated software Special Function Register, PCON. hardware address 87H. PCON addressable. Figure Idle Power Down Hardware.
Symbol
SMOD
Position
PCON.7
Name Function
Double Baud rate bit. When baud rate doubled when serial port being used either modes (Reserved) (Reserved) (Reserved) General-purpose flag bit. General-purpose flag bit. Power Down bit. Setting this activates power down operation. Idle mode bit. Setting this activates idle mode operation.
PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0
written same time. takes, precedence. reset value PCON (000X0000).
6.1. Idle Mode
instruction that sets PCON.0 last instruction executed before Idle mode activated. Once Idle mode status preserved entirety Stack Pointer, Program Counter, Program Status Word, Accumulator, other registers maintain their data during idle. Table describes status external pins during Idle mode.
PCON Power Control Register
(MSB) SMOD (LSB)
MATRA Rev. Fev.
80C32/80C52
There three ways terminate Idle mode. Activation enabled interrupt will cause PCON.0 cleared hardware, terminating Idle mode. interrupt serviced, following RETI, next instruction executed will following instruction that wrote PCON.0. flag bits used determine whether interrupt received during normal execution during Idle mode. example, instruction that writes PCON.0 also clear both flag bits. When Idle mode terminated enabled interrupt, service routine examine status flag bits. second terminating Idle mode with hardware reset. Since oscillator still running, hardware reset needs active only machine cycles oscillator periods) complete reset operation.
6.2. Power Down Mode
instruction that sets PCON.1 last executed prior entering power down. Once power down, oscillator stopped. contents onchip Special Function Register saved during power down mode. hardware reset initiates Special Fucntion Register. Power Down mode, lowered minimize circuit power consumption. Care must taken ensure voltage reduced until power down mode entered, that voltage restored before hardware reset applied which freezes oscillator. Reset should released until oscillator restarted stabilized. Table describes status external pins while power down mode. should noted that power down mode activated while external program memory, port data that held Special Function Register restored Port data port held high during power down mode strong pullup, shown Figure
Table Status external pins during idle power down modes.
Mode
Idle Idle Power Down Power Down
Program Memory
Internal External Internal External
PSEN
PORT0
Port Data Floating Port Data Floating
PORT1
Port Data Port Data Port Data Port Data
PORT2
Port Data Address Port Data Port Data
PORT3
Port Data Port Data Port Data Port Data
6.3. Stop Clock Mode
static design, TEMIC 80C32/C52 clock speed reduced until without data loss memory registers. This mode allows step step utilization, permits reduce system power consumption bringing clock frequency down value. MHz, power consumption same Power Down Mode.
Figure Buffers 80C52 (Ports
6.4. Ports
buffers Ports implemented shown figure
MATRA Rev. Fev.
80C32/80C52
When port latch contains pFETS figure while nFET turned When port latch makes 0-to-1 transition, nFET turns off. strong pFET, turns oscillator periods, pulling output high very rapidly. output line drawn high, pFET turns through inverter supply source current. This inverter form latch which holds supported When Port used address port, access external program data memory, address that contains will have strong pullup turned entire duration external memory access. When Ports used input, user should aware that external circuit must sink current during logical 1-to-0 transition. maximum sink current specified under D.C. Specifications. When input goes below approximately turns save current. Note, when returning logical only internal pullup that This will result slow rise time user's circuit does force input line high. Figure Crystal Oscillator.
drive device from external clock source, XTAL1 should driven while XTAL2 left unconnected shown figure There requirements duty cycle external clock signal, since input internal clocking circuitry through divide-by-two flip-flop, minimum maximum high times specified Data Sheet must observed. Figure External Drive Configuration.
6.5. Oscillator Characteristics
XTAL1 XTAL2 input output respectively, inverting amplifier which configured on-chip oscillator, shown figure Either quartz crystal ceramic resonator used.
Hardware Description
Same 80C51, plus third timer/counter that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured into registers RCAP2L RCAP2H, respectively, (RCAP2L RCAP2H Special Function Register 80C52). addition, transition T2EX causes EXF2 T2CON set, EXF2, like TF2, generate interrupt. Table Timer Operating Modes.
RCLK TCLK
7.1. Timer/Event Counter
Timer timer/counter like Timers operate either timer event counter. This selected C/T2 Special Function Register T2CON (Figure three operating modes "capture", "autoload" "baud rate generator", which selected bits T2CON shown Table capture mode there options which selected EXEN2 T2CON; EXEN2 then Timer timer counter which upon overflowing sets TF2, Timer overflow bit, which used generate interrupt. EXEN2 then Timer still does above, with added feature
CP/RL2
MODE
auto-reload capture baud rate generator (off)
MATRA Rev. Fev.
80C32/80C52
capture mode illustrated Figure Figure Timer Capture Mode. with value registers RCAP2L RCAP2H, which preset software. EXEN2 then Timer still does above, with added feature that 1-to-0 transition external input T2EX will also trigger reload EXF2. auto-reload mode illustrated Figure Figure Timer Auto-Reload Mode.
auto-reload mode there again options, which selected EXEN2 T2CON.If EXEN2 then when Timer rolls over does only also causes Timer register reloaded
(MSB) EXF2 RCLK TCLK EXEN2 C/T2 (LSB) CP/RL2
baud rate generator mode selected RCLK and/or TCLK
Symbol
EXF2
Position
T2CON.7 T2CON.6
Name Significance
Timer overflow flag Timer overflow must cleared software. will when either RCLK TCLK Timer external flag when either capture reload caused negative transition T2EX EXEN2 When Timer interrupt enabled, EXF2 will cause vector Timer interrupt routine. EXF2 must cleared software. Receive clock flag. When set, causes serial port Timer2 overflow pulses receive clock modes RCLK causes Timer overflow used receive clock. Transmit clock flag. When set, causes serial port Timer overflow pulses transmit clock modes TCLK causes Timer overflows used transmit clock. Timer external enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/stop control Timer logic starts timer. Timer counter select. (Timer Internal timer (OSC/12) External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur negative transitions T2EX EXEN When cleared, auto reloads will occur either with Timer overflows negative transition T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
RCLK
T2CON.5
TCLK
T2CON.4
EXEN2
T2CON.3
C/T2 CP/RL2
T2CON.2 T2CON.1 T2CON.0
MATRA Rev. Fev.
80C32/80C52
7.2. 80C52 with Secret
TEMIC offers 80C52 with encrypted secret option secure code contained 80C52 microcontrollers. clear reading program contained made impossible encryption through several random keys implemented during manufacturing process. keys used such encryption selected randomwise definitely different from microcontroller another. This encryption activated during following phases Everytime byte addressed during verify content, byte encryption array selected. MOVC instructions executed from external program memory disabled when fetching code bytes from internal memory. sampled latched reset, thus state modification disabled. further information please refer application note (ANM053) available upon request.
7.3. 80C52 with Secret
TEMIC offers special 64-bit identifier called "SECRET TAG" microcontroller chip. Secret option available both ROMless masked microcontrollers. Secret feature allows serialization each microcontroller identification specific equipment. unique number device implemented chip during manufacturing process. serial number 64-bit binary value which contained addressable Special Function Registers (SFR) area. This Secret option read-out software routine thus enables user individual identity check device. This routine implemented inside microcontroller memory case masked version which kept secret (and then value Secret also) using Encryption. further information, please refer application note (ANM031) available upon request.
MATRA Rev. Fev.
80C32/80C52
8.Electrical Characteristics
8.1. Absolute Maximum Ratings*
Ambiant Temperature Under Bias commercial industrial Storage Temperature Voltage -0.5 Voltage -0.5 Power Dissipation This value based maximum allowable temperature thermal resistance package
Notice
Stresses above those listed under Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Table Parameters 70°C -40°C 85°C
Symbol
VIH1 Input Voltage Input High Voltage (Except XTAL RST) Input High Voltage (for XTAL RST) Output Voltage (Port
Parameter
0.45 0.45
Unit
Test Conditions
(note (note 0.45 0.45 (note
VOL1
Output Voltage (Port ALE, PSEN)
Output High Voltage Port
VOH1
Output High Voltage (Port ALE, PSEN)
RRST
Logical Input Current (Ports Input leakage Current Logical Transition Current (Ports Power Down Current Pulldown Resistor Capacitance Buffer Power Supply Current Freq idle Freq idle Freq 1.25 Freq (MHz) idle 0.36 Freq (MHz)
KOhm
MHz, 25_C
MATRA Rev. Fev.
80C32/80C52
8.2. Absolute Maximum Ratings*
Ambient Temperature Under Bias Automotive +125 Storage Temperature Voltage -0.5 Voltage -0.5 Power Dissipation This value based maximum allowable temperature thermal resistance package
Notice
Stresses above those listed under Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Table Parameters -40°C 125°C
Symbol
VIH1 Input Voltage Input High Voltage (Except XTAL RST) Input High Voltage (for XTAL RST) Output Voltage (Port
Parameter
0.45 0.45
Unit
Test Conditions
(note (note 0.45 0.45 (note
VOL1
Output Voltage (Port ALE, PSEN)
Output High Voltage Port
VOH1
Output High Voltage (Port ALE, PSEN)
RRST
Logical Input Current (Ports Input leakage Current Logical Transition Current (Ports Power Down Current Pulldown Resistor Capacitance Buffer Power Supply Current Freq idle Freq idle Freq 1.25 Freq (MHz) idle 0.36 Freq (MHz)
KOhm
MHz, 25_C
MATRA Rev. Fev.
80C32/80C52
8.3. Absolute Maximum Ratings*
Ambient Temperature Under Bias Military +125 Storage Temperature Voltage -0.5 Voltage -0.5 Power Dissipation This value based maximum allowable temperature thermal resistance package
Notice
Stresses above those listed under Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Table Parameters -55°C 125°C
Symbol
VIH1 VOL1 Input Voltage Input High Voltage (Except XTAL RST) Input High Voltage (for XTAL RST) Output Voltage (Port Output Voltage (Port ALE, PSEN) Output High Voltage (Port 0.75 VOH1 Output High Voltage (Port External Mode, ALE, PEN) 0.75 RRST Logical Input Current (Ports Input leakage Current Logical Transition Current (Ports Power Down Current Pulldown Resistor Capacitance Buffer Power Supply Current Freq idle Freq idle Freq 1.25 Freq (MHz) idle 0.36 Freq (MHz)
Parameter
0.45 0.45
Unit
Test Conditions
(note (note 0.45 0.45 (note
MHz, 25_C
MATRA Rev. Fev.
80C32/80C52
8.4. Absolute Maximum Ratings*
Ambient Temperature Under Bias Commercial Industrial Storage Temperature Voltage -0.5 Voltage -0.5 Power Dissipation This value based maximum allowable temperature thermal resistance package
Notice
Stresses above those listed under Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Table Characteristics 70°C -40°C 85°C
Symbol
VIH2 VIH1 VOL1 VOH1 RRST
Parameter
Input Voltage Input High Voltage (Except XTAL RST) Input High Voltage Reset Input High Voltage XTAL1 Power Down Voltage Mode Output Voltage (Ports Output Voltage Port ALE, PSEN Output High Voltage Ports Output High Voltage (Port External Mode), ALE, PSEN Logical Input Current Ports Input Leakage Current Logical Transition Current (Ports Power Down Current Pulldown Resistor Capacitance Buffer
0.45 0.45
Unit
Test Conditions
(note (note 0.45 0.45 (note
MHz, 25_C
Table Maximum (mA)
Operating (Note
FREQUENCY/Vcc Freq (Vcc
IDLE (Note
(mA) 1.25 Freq (MHz) Idle (mA) 0.36 Freq (MHz)
MATRA Rev. Fev.
80C32/80C52
Note measured with output pins disconnected XTAL1 driven with TCLCH, TCHCL XTAL2 N.C. Port VCC. would slighty higher crystal oscillator used. Idle measured with output pins disconnected XTAL1 driven with TCLCH, TCHCL XTAL2 Port VSS. Power Down measured with output pins disconnected PORT XTAL2 N.C. VSS. Note Capacitance loading Ports cause spurious noise pulses superimposed VOLS Ports noise external capacitance discharging into Port Port pins when these pins make transitions during operations. worst cases (capacitive loading pF), noise pulse line exceed 0.45 exceed 0,45 with maxi peak Schmitt Trigger necessary. Figure Test Condition, Active Mode. other pins disconnected. Figure Test Condition, Idle Mode. other pins disconnected.
Figure Test Condition, Power Down Mode. other pins disconnected.
Figure Clock Signal Waveform Tests Active Idle Modes. TCLCH TCHCL
MATRA Rev. Fev.
80C32/80C52
8.5. Explanation Symbol
Each timing symbol characters. first character always (stands time). other characters, depending their positions, stand name signal logical status that signal. following list characters what they stand for.
Address. Clock. Input data. Logic level HIGH Instruction (program memory contents). Logic level LOW, ALE. PSEN.
Example TAVLL Time Address Valid low. TLLPL Time PSEN low.
Output data. READ signal. Time. Valid. WRITE signal. longer valid logic level. Float.
MATRA Rev. Fev.
80C32/80C52
8.6. Parameters
70°C +70°C -40° 85°C -55° 125°C
(Load Capacitance PORT PSEN Load Capacitance other outputs
Table External Program Memory Characteristics (values
Symbol
TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ
Parameter
Pulse Width Address valid Address Hold After valid instr PSEN PSEN pulse Width PSEN valid instr Input instr Hold After PSEN Input instr Float After PSEN PSEN Address Valid Address Valid instr PSEN Address Float
Figure External Program Memory Read Cycle
TAVIV
MATRA Rev. Fev.
80C32/80C52
Table External Data Memory Characteristics (values
Symbol
TRLRH TWLWH TLLAX TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH
Parameter
pulse Width pulse Width Address Hold After Valid Data Data hold after Data float after Valid Data Address Valid Data Address Data valid transition Data Setup transition Data Hold after Address Float high high
Figure External Data Memory Write Cycle
TAVWL
TQVWX
MATRA Rev. Fev.
80C32/80C52
Figure External Data Memory Read Cycle
Table Serial Port Timing Shift Register Mode (values
Symbol
TXLXL TQVXH TXHQX TXHDX TXHDV
Parameter
Serial Port Clock Cycle Time Output Data Setup Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge Input Data Valid
Figure Shift Register Timing Waveforms
MATRA Rev. Fev.
80C32/80C52
Table External Clock Drive Characteristics (XTAL1)
Symbol
FCLCL TCLCL TCHCX TCLCX TCLCH TCHCL
Parameter
Oscillator Frequency Oscillator period High Time Time Rise Time Fall Time
Unit
22.7
Figure External Clock Drive Waveforms
Figure Testing Input/Output Waveforms
inputs during testing driven logic 0.45 logic "0". Timing measurements made logic logic "0". Figure Float Waveforms
timing purposes port longer floating when change from load voltage occurs begins float when change from loaded VOH/VOL level occurs. Iol/IoH
MATRA Rev. Fev.
80C32/80C52
Figure Clock Waveforms
This diagram indicates when signals clocked internally. time takes signals propagate pins, however, ranges from This propagation delay dependent variables such temperature loading. Propagation also varies from output output component. Typically though 25°C fully loaded) propagation delays approximately other signals typically Propagation delays incorporated specifications.
MATRA Rev. Fev.
80C32/80C52
Ordering Information
80C52C
Temperature Range blank Commercial Industrial Automotive Military
Part Number 80C52 80C32 External 80C52C Secret version 80C52T Secret version 80C32E Radiation Tolerant 80C52E Radiation Tolerant
-L16
Package Type PDIL PLCC PQFP (Foot print 13.9 PQFP (Foot print 12.3 VQFP (1.4 TQFP (1.0 CDIL Customer Code CQFP Side Brazed (.6) Leaded
version version version version version version version version version Power (Vcc 2.7-5.5 Freq 0-16 MHz)
Only 80C31 commercial range.
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
MATRA Rev. Fev.
80C32/80C52
Temp. range Packages
L-16
Speed (MHz)
16,00 20,00 25,00 30,00 36,00
process 80C32/52
process 80C32E
flows
flows
Space flows
MATRA Rev. Fev.

CMOS Single Chip 8-bit Microcontroller Description TEMIC's 8

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