16-Bit Flow-Through EDAC Error Detection Correction unit 29C516E
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29C516E
16-Bit Flow-Through EDAC Error Detection Correction unit
29C516E TEMIC EDAC very power flow-through 16-bit Error Detection Correction unit (EDAC) with user data buses. EDAC used high integrity system monitoring correction data values coming from memory space. During processor write cycle, each memory location (16-bit width), EDAC calculated checkword 8-bit width) added. When performing read operation from memory, 29C516E verifies entire checkword data combination. detects correct 100% single-bit errors detects double-bit errors. When 29C516E uses 6-checkbit, detect error single 4-bit memory chip. 8-check-bit option gives additional capability detect errors single 8-bit memory chip. errors signaled master system (via error Flags) order allow processor make required action. 29C516E operates possible modes: corrected detected mode. corrected mode, single-bit error complemented (corrected). Then, available entire data placed output port Correctable Error Flag set. case double-bit errors more), corrupted data placed output port Uncorrectable Error Flag set. Note that when there more than errors, then some patterns appear possible correctable errors. Therefore, environment produces this type error, EDAC must used detect provide automatic correction. Data syndrome analysis must done. 29C516E acts data buffer µP-memory interfacing. flow-through EDAC placed data path, between processor memory protected. This component able serve different users memory space. forms interface between 22/24-bit (16+6/16+8) memory data 16-bit processor data busses with high drive capability (-12.8 mA). data ports used create dual port front memory space. User-1(2) transfer data from/to memory from/to User-2(1), by-passing memory. During read write memory cycles processed User-1(2), User-2(1) have possibility listen transferred data.
Features
Very Power CMOS 16-Bit operation with Check Bits Fast Error Detection (max.) Fast Error Correction (max.) Corrects Single-Bit Errors Detects Double-Bit Errors Detects some Multi-Bit Errors Detects Chip Errors (x1, Format)
Correctable Uncorrectable Error Flags User Data Buses User User Transfer Listening operation High Drive Capability Buses -12.8 Compatible Single ±10% Power Supply Multilayer Quad Flat Pack (Flat leaded leaded).
MATRA Rev. Mar.
29C516E
Interface
3.1. Functional Diagram
Figure 1.Functional Diagram
CORRECT SYNCHK MEM1 RD/WR1
CHECK GENERATOR
BUFFER
MC[0.7]
U1D[0.15] U2/U1 TRANS U2D[0.15]
BUFFER
CONTROLLER
BUFFER
29C516E
RD/WR2 MEM2
BUFFER
MD[0.15]
CERR NCERR
SYNDROME DECODER
SYNDROME GENERATOR
3.2. Block Diagram
Figure 2.Block Diagram
CORRECT SYNCHK U1/U2 TRANS U1D[0.15] MC[0.7] MEM1 RD/WR1 MD[0.15] U2D[0.15] MEM2 RD/WR2
29C516E
CERR NCERR
MATRA Rev. Mar.
29C516E
3.3. Configuration multilayer quad Flat-pack (flat leaded)
Figure 3.Pin Configuration
index corner MEM2 U2D[15] U2D[14] U2D[13] U2D[12] U2D[11] U2D[10] U2D[9] U2D[8] U2D[7] U2D[6] U2D[5] U2D[4] U2D[3] U2D[2] U2D[1] U2D[0] NCERR CERR U1D[15]
RD/WR2 CORRECT SYNCHK TRANS U2/U1 MC[7] MC[6] MC[5] MC[4] MC[3] MC[2] MC[1] MC[0]
MQFPF100 MQFPL100 (Top view)
MD[15] MD[14] MD[13] MD[12] MD[11] MD[10] MD[9] MD[8] MD[7] MD[6] MD[5] MD[4] MD[3] MD[2] MD[1] MD[0] MEM1 RD/WR1 U1D[0]
MATRA Rev. Mar.
U1D[14] U1D[13] U1D[12] U1D[11] U1D[10] U1D[9] U1D[8] U1D[7] U1D[6] U1D[5] U1D[4] U1D[3] U1D[2] U1D[1]
29C516E
3.4. Description
Table
Name Description Active Description
Buses U1D[0.15] U2D[0.15] D[0.15] C[0.7] Error Flags CERR NCERR Correctable Error Uncorrectable Error 53,49.47,45.42,40.37,35.33,28 23.20,18.15,13.10,8.5 59.62,64.67,69.72,74.77 83.86,88.91 I/O* I/O* I/O* I/O* High High High High User Data User Data Memory Data Memory Check-bit
General Control Signals CORRECT SYNCHK TRANS U2/U1 High High When active, EDAC CORRECT mode. low, EDAC DETECT mode. Selects Syndrome bits (high byte) Check-bits (low byte) driven selected User Data Bus. When active, EDAC uses check-bits. low, EDAC uses check-bits memory read. Selects Data pathto used. high, EDAC access memory, low, EDAC access transfert buffer. Selects master User User master responsible applying RD/WRx, MEMx, signals correct way.
User Control Signals RD/WRT MEM1 User Read/Write signal User Output Enable User Memory Select
User Control Signals RD/WR2 MEM2 Power (Buffers) VCCB GNDB Power (Core) VCCC GNDC Core supply nominal) Core reference 9,19,32,41,54,63,73,87 4,14,24,36,46,58,68,78,92 Buffers supply nominal) Buffers nominal reference User Read/Write signal User Output Enable User Memory Select
Pull-up buffers
MATRA Rev. Mar.
29C516E
Check-Bit Generation
Check-bit Generator produces check-bits (whatever value) from incoming User Data Word UxD[0.15] according Table Example: create check-bit Data Word XORed together. memory devices 8-bit wide used, bits (MD[0.15] MC[0.7]) stored give error detection. memory devices 1-bit 4-bit wide used, bits (MD[0.15] MC[0.5]) stored give error detection.
Table Check Generation (indicates used XOR/NXOR)
MC[.] PARITY Even(XOR) Even(XOR) Odd(NXOR) Odd(NXOR) UxD[.]
Even(XOR) Even(XOR) Even(XOR) Odd(NXOR)
Syndrome Generation
syndrome Generator produces syndrome-bits (whatever value) from incoming Memory Data Word MD[0.15] associated Check-bits MC[0.7] MC[0.5]) according Table Syndrome-bit SY[x] generated Check-bit MC[x] with generation Chek-bit MD[.]. Example: create syndrome-bit first Data Word (MD[14,13,10,4,3,2,1,0]) NXORed. Then, result XORed with associated Check-bit (MC[3]) Check-byte read same time Data Word checked. memory uses devices, then bits should physically divided follows: MC[0.7], MD[0.7] MD[8.15] organization, bits should divided MC[0.2]+MC[6], MC[3.5]+MC[7], MD[0.3], MD[4.7], MD[8.11] MD[12.15].
Table Syndrome Generation (indicates buses used XOR/NXOR)
SY[.] PARITY EVEN(XOR) EVEN(XOR) ODD(NXOR) ODD(NXOR) MD[.] MC[.]
EVEN(XOR) EVEN(XOR)
EVEN(XOR) ODD(NXOR)
MATRA Rev. Mar.
29C516E
Syndrome Decoding
syndrome decoder generates error flags /CERR (Correctable ERRor) /NCERR (Non-Correctable ERRor). correctable error occurs, 29C516E EDAC provides corrected data user. inputs syndrome bits from syndrome generator, data bits from memory control signal N22. signal controls bits shall decode from entire memory word.
Table 6-Bit Syndrome Word Bit-In-Error (N22="1")
Syndrome SY[.] N.E.D MD10 MD12 MD13 MD14 MD11 MD15
Note
N.E.D Errors Detected Memory Data Bit-In-Error Memory Check Bit-In-Error Double-Bit-In-Error Detected Multi-Bit-In-Error Detected
MATRA Rev. Mar.
29C516E
Table 8-Bit Syndrome Word Bit-In-Error (N22 "0")
Syndrome
N.E.D MD10 MD14 MD12 MD15 MD13 MD11
Note
N.E.D Errors Detected Memory Data Bit-In-Error Memory Check Bit-In-Error Double-Bit-In-Error Detected Multi-Bit-In-Error Detected
6-Bit Syndrome Word
This feature available when driven high level.
7.1. Errors
there errors read Data Check-Bit, syndrome byte "00". EDAC flags inactive. Error SY=00
7.2. Single Bit-Error
single bit-error Memory Data word read (MD[.]) causes three syndrome bits one. code formed indicates which Memory Data word incorrect. example, MD[2] were incorrect, syndrome byte would have bits one. syndrome decoder 29C516E EDAC decodes information syndrome byte only sets error flag CERR. correct mode (CORRECT active), inverts (and MATRA Rev. Mar. hence corrects) relevant error Memory Data word provides expected Data word EDAC controller. there error Memory Check-bit (MC[.]), only syndrome one. this case, syndrome decoder sets correctable error flag CERR, NCERR does change. does correct Check-bit because these bits used system.
29C516E
Table Single Bit-Error
MD[.] SY(hexa) [15] [14] [13] [12] [11] [10]
MC[.] SY(hexa)
7.3. Double-Bit Error
errors occurs, there will either bits syndrome byte. syndrome value generated double-bit error does take place syndrome value generated single-bit error. Then, only correctable error flag NCERR will activated indicate that errors present cannot corrected. Example: MD[4] MC[2] incorrect, syndrome bits [0], [1], (SY=0Fh NCERR CERR remains high level.
7.4. Triple-Bit Error
Triple-Bit Error When three errors detected, error flag warning system. generated syndrome have listed value single-bit error. device must detect mode prevent false correction occurring. Example: MD[0], MD[14] MC[1] corrupted, syndrome value "25h This decoded 29C516E EDAC being correctable error MD[12]. CERR flag correction would take place device correct mode. This would cause more errors.
7.5. 4-bit Wide Memory Error
check-bit code used provide error detection errors occurring following groups: MD[15.12], MD[11.8], MD[7.4], MD[3.0], MC[5.3] MC[2.0]. 29C516E EDAC flag number errors 4-bit wide memory chip. special attention must taken, muti-bit error located into defined groups provide syndrome byte single-bit error. Example: MD[3], MD[2], MD[1] MD[0] error, syndrome code
8-Bit Syndrome Word
This feature available when driven level.
8.1. Errors
there errors read Data Check-Bit, syndrome byte "00". EDAC flags inactive. Error SY=00
8.2. Single Bit-Error
Single Bit-Error single bit-error Memory Data word read (MD[.]) causes three syndrome bits one. code formed indicates which Memory Data word incorrect. example, MD[10] were incorrect, syndrome byte would have bits one. syndrome decoder 29C516E EDAC decodes information syndrome byte only sets error flag CERR. correct mode (CORRECT active), inverts (and hence corrects) relevant error Memory Data word provides expected Data word EDAC controller. there error Memory Check-bit (MC[.]), only syndrome one. this case, syndrome decoder sets correctable error flag CERR, NCERR does change. does correct Check-bit because these bits used system. MATRA Rev. Mar.
29C516E
Table Single Error
MD[.] SY(hexa) [15] [14] [13] [12] [11] [10]
MC[.] SY(hexa)
8.3. Double-Bit Error
errors occur, there will bits syndrome byte. syndrome value generated double-bit error does take place syndrome value generated single-bit error. Then, only correctable error flag NCERR will activated indicate that errors present cannot corrected. Example: MD[5] MC[7] incorrect, syndrome bits [0], [2], (SY=55h NCERR CERR remains high level.
8.4. Triple-Bit Error
When three errors detected, error flag warning system. generated syndrome have listed value single-bit error. device must detect mode prevent false correction occurrence. Example: MD[0], MD[9] MC[0] corrupted, syndrome value "1Ah This decoded 29C516E EDAC being correctable error MD[10]. CERR flag correction would take place device correct mode. This would cause more errors.
8.5. 4-bit Wide Memory Error
check-bit code used provide error detection errors occur following groups: MD[15.12], MD[11.8], MD[7.4], MD[3.0], MC[7.4] MC[3.0]. 29C516E EDAC flag number errors 4-bit wide memory chip. special attention must taken, multi-bit error located into defined groups provide syndrome byte single-bit error. Example: MD[11], MD[10], MD[9] MD[8] error, syndrome code
8.6. 8-bit Wide Memory Error
check-bit code used provide error detection errors occurring following groups: MD[15.8], MD[7.0] MC[7.0]. 29C516E EDAC flag number errors 8-bit wide memory chip. special attention must taken, muti-bit error located into defined groups provide syndrome byte single-bit error. Example: MD[13], MD[12], MD[10] MD[9] error, syndrome code "40h check-bit coding, syndrome code should have been "00h Error Detected" value.) Note that syndrome code also code MC[6] error.
Transactions
Transactions Three types transactions done:
9.1. Memory Read
TRANS driven high level select access memory. external arbiter drives U2/U1 dispatches commands RD/WRx, MEMx ENx. transaction managed master user listened second user.
MATRA Rev. Mar.
29C516E
Table
CORRECT SYNCHK RD/WR1 RD/WR2 TRANS NCERR MEM1 MEM2 CERR U2/U1
Function
UD1[0.15] MD[0.15] UD1[0.15] {corrected MD[0.15]} UD1[0.15] {corrupted MD[0.15]} UD1[0.15] MD[0.15] UD1[0.15] {MC[0.7] Syndrome} UD1[0.15]
UD2[0.15] {expected UD1[0.15]} (User listening) UD2[0.15] MD[0.15] UD2[0.15] {corrected MD[0.15]} UD2[0.15] {corrupted MD[0.15]} UD2[0.15] MD[0.15] UD2[0.15] {MC[0.7] Syndrome} UD2[0.15]
UD1[0.15] {expected UD2[0.15]} (User listening)
don't care
9.2. Memory Write
TRANS driven high level select access memory. external arbiter drives U2/U1 dispatches commands RD/WRx, Table
RD/WR1 TRANS RD/WR2 MEM1 MEM2
MEMx ENx. transaction managed master user listened second user.
U2/U1
Function
MD[0.15] UD1[0.15] MC[0.7] {check-bits generated from UD1[0.15]} MD[0.15] MC[0.7] UD2[0.15] UD1[0.15] (User listening) MD[0.15] UD2[0.15] MC[0.7] {check-bits generated from UD2[0.15]} MD[0.15] MC[0.7] UD1[0.15] UD2[0.15] (User listening)
don't care CERR NCERR valid CORRECT SYNCHK active
MATRA Rev. Mar.
29C516E
9.3. User User Transfer
TRANS driven level select this mode. external arbiter drives U2/U1 Table
RD/WR1 TRANS RD/WR2 MEM2 MEM1
Function
dispatches unidirectional commands RD/WRx, MEMx ENx.
U2/U1
UD1[0.15] UD2[0.15] UD1[0.15] UD2[0.15] UD1[0.15] UD2[0.15] UD2[0.15] UD1[0.15] UD2[0.15] UD1[0.15] UD2[0.15] UD1[0.15]
don't care CERR NCERR valid CORRECT SYNCHK active
MATRA Rev. Mar.
29C516E
Signal Timing
10.1. Memory Write
Figure 4.Memory Write Timing Diagram
U2/U1 MD[0.15] MC[0.7] UD2[0.15]
1.5TRANS
Memory Data Word
Generated Check-bits
RD/WR2 MEM2 Propagation Delays Output Enable Disable Times Value Value
Figure 5.Transfer Write Timing Diagram
U2/U1 UD2[0.15] UD1[0.15] TRANS RD/WR1 MEM1 Propagation Delays Output Enable Disable Times Value Value
MATRA Rev. Mar.
29C516E
10.2. Memory Read
Figure 6.Memory Read Timing Diagram
CERR NCERR MD[0.15] MC[0.7] CORRECT Memory Data Word Memory Check-bits Corrected Data Valid Error Flag Valid Error Flag
UD1[0.15] TRANS RD/WR2 MEM2 Propagation Delays
Value
Value
Output Enable Disable Times
Value
MATRA Rev. Mar.
29C516E
10.3. Transfer Read
Figure 7.Transfer Read Timing Diagram
U2/U1
UD2[0.15] UD1[0.15] TRANS RD/WR2 MEM2 Propagation Delays
Value
Output Enable Disable Times
Value
Electrical Characteristics
11.1. Absolute Maximum Ratings
Table
Parameter Value
Supply voltage, Input voltage range Input current power Input current signal Continuous output current, Soldering lead temperature from case Storage temperature Maximum package power dissipation
MATRA Rev. Mar.
29C516E
11.2. Operating Conditions
Table
Parameter Unit
Supply voltage, Operating temperature range
Volt
11.3. Static Electrical Characteristics
Table
Parameter Condition Unit
VOH1 VOL1 VOH2 VOL2 IILP IIHP IOZLP IOZHP ICCSB
High level input voltage level input voltage High level output voltage level output voltage High level output voltage level output voltage level input current level input current, (Pull-up Input) High level input current High level input current, (Pull-down Input) Output leakage current Output leakage current, (Pull-up Input) Output leakage current, (Pull-down Input) Input capacitance capacitance Standby supply current 12.8 12.8 Outputs disable, (Gnd<Vout<Vcc) Outputs disable, (Vout=Gnd) Outputs disable, (Vout=Vcc)
Vcc-0.1
MATRA Rev. Mar.
29C516E
Ordering information
Temperature Range Package Device 29C516E Speed Flow
31ns version Military Space MQFPF100 MQFPL100 EDAC16 tolerant Blanck: TEMIC Military flow /883: class ESA/SCC 9000 level ESA/SCC 9000 level P883: MIL-STD-883 PIND Test Hxxx: Customer specification
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. Mar.
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