ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS Microco
|
|
|
Top Searches for this datasheet
CORE
ADRESSING MODES PERIPHERALS SOFTWARE TOOLS HARDWARE TOOLS
Microcontroller Training CORE
ST72 CORE General Description
CORE BUILT AROUND 8-bit Arithmetic Logic Unit (ALU) internal registers Accumulator (A), index registers, Program Counter (PC), Stack Pointer (SP) Code Condition register (CC) controller block INTERFACES WITH on-chip oscillator reset block address data buses access memories peripherals interrupt controller
Microcontroller Training CORE
ST72 CORE Block Diagram
OSCin OSCILLATOR OSCout TEST/VPP CONTROL RESET
Internal CLOCK
Watchdog
-BIT DATA
Accu Index Index
ADDRESS
Program memory
Microcontroller Training CORE
ST72 CORE Internal Registers
ACCUMULATOR 8-BIT GENERAL PURPOSE REGISTER USED HOLD Operands Results arithmetic logic operation REGISTERS 8-BIT REGISTERS USED Create effective addresses Store temporary data automatically stacked. needed, must done using PUSH instructions Instructions using faster than ones using
Microcontroller Training CORE
ST72 CORE Internal Registers
PROGRAM COUNTER 16-BIT REGISTER USED STORE ADDRESS NEXT INSTRUCTION EXECUTED CPU. RESULT, ADDRESS PROGRAM MEMORY STACK POINTER 16-BIT REGISTER. FIXED HARDWARE CODE CONDITION 5-BIT REGISTER
NAME Half carry Interrupt mask Negative Zero Carry/Borrow DESCRIPTION when carry occurs during instructions disabled interrupt result last operation negative result last operation zero affected when carry borrow occur some inst. executed
Microcontroller Training CORE
CORE Internal Registers
ACCUMULATOR
RESET VALUES
INDEX REGISTER
RESET VALUES
INDEX REGISTER
RESET VALUES
PROGRAM COUNTER
RESET VALUES RESET VECTOR FFFEh-FFFFh Fixed RESET VALUES
STACK POINTER
CONDITION CODE REGISTER
Microcontroller Training CORE
ST72CORE Stack manipulation
PURPOSE Save context during subroutine calls interrupts Save temporary user's data (PUSH instructions) CASE OVERFLOW (LOWER LIMIT EXCEEDED) stay unchanged Previous value overwritten lost Stack overflow indicated return from subroutines interrupt
Microcontroller Training CORE
Lower Address
Higher Address
Push call subroutines interrupt
CORE Stack manipulation
CALL Interrupt subroutine event
$0140
PUSH
IRET
$017F
Stack size position device dependent ST72251 bytes ($0140 $017F) ST72311 ST725xx bytes ($0100 $01FF)
Microcontroller Training CORE
CORE memory space
MEMORY MADE DIFFERENT BLOCKS Peripherals hardware register Short Ports, TIM, PWMB, WDG,SPI, Addressing I2C, EEPROM Mode first page Location Stack from bytes (device dependent) EEPROM Program memory Interrupt Reset vectors
PERIPHERALS HARDWARE REGISTERS Bytes Bytes STACK Bytes
$0100 $0140 $0180
RESERVED $E000 ROM/EPROM 8KBytes INTERRUPTS RESET VECTORS $FFF2
$FFFF
Microcontroller Training CORE
CORE Clock System
SYSTEM CLOCK PROVIDED EITHER crystal ceramic resonator external clock source
ST72XX OSCin OSCout ST72XX OSCin OSCout External Clock Coscin Coscout
Crystal
Rsmax (16MHz Xtal) Coscin Coscout
Microcontroller Training CORE
External Clock
56pF 56pF 47pF 47pF 22pF 22pF
CORE Clock System
Maximum OSCILLATOR
OSCin OSCout OSCin MISCELLANEOUS REGISTER
Prescaler
Peripherals
Rp=10M
COSCin
COSCout
Prescaler ST72251 ST72311 ST725xx
Microcontroller Training CORE
CORE Reset diagram
WAYS RESET MICRO external Reset Purpose allow generate external reset Condition reset pull Power Reset Purpose ensure proper start power Remark configure reset state until power supply rises sufficient level Digital Watchdog Purpose guarantee safety case software trouble Condition internal reset when register refreshed (the timer reaches end-of-count condition)
Microcontroller Training CORE
CORE Reset diagram
POWER-ON RESET DETECTS RISING EDGE DURING POWER
Power supply Reset state
4096 cycles
Oscillator
Must below 0.8V order initialize sequence
Microcontroller Training CORE
CORE Reset diagram
OSCILLATOR SIGNAL COUNTER
Internal Reset
NRESET (ACTIVE LOW)
RESET
300k
POWER RESET WATCHDOG RESET
Microcontroller Training CORE
INTERRUPTS Overview
EXCEPT SOFTWARE INTERRUPT, INTERRUPTS MASKED SETTING WHEN INTERRUPT OCCURS context saved stack (CC, other interrupts masked (the H/W) interrupt vector loaded Program Counter WHEN RETURN FROM INTERRUPT EXECUTED original context automatically restored (CC, Interrupts enabled reset) PRIORITY BETWEEN INTERRUPTS GIVEN INTERRUPT ADDRESS VECTOR
Microcontroller Training CORE
INTERRUPTS ST72251 Interrupt mapping
INTERRUPT Reset Trap (instruction) External Interrupt External Interrupt Timer INTERRUPTS Reset Software Port Port Port Transfer Complete Mode Fault Input Capture1 Output Compare Input Capture1 Output Compare Timer Overflow Input Capture1 Output Compare Input Capture1 Output Compare Timer Overflow Byte Transmission finished Error STOP Detection REGISTER Status Timer Status FLAG NAME SPIF MODF ICF1_1 OCF1_1 ICF2_1 OCF2_1 TOF_1 ICF1_2 OCF1_2 ICF2_2 OCF2_2 TOF_2 BERR SSTOP INTERRUPT SOURCE VECTOR ADDRESS FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF4h-FFF5h FFF2h-FFF3h
Timer
Timer Status
FFEEh-FFEFh
Status
FFE4h-FFE5h
Microcontroller Training CORE
INTERRUPTS Peripheral management
Periph Status Register Periph Control Register Condition Code Register
Interrupt flag Interrupt Enable
Interrupt generation
Microcontroller Training CORE
Context switch takes clock cycles
INTERRUPT Peripheral management
EXAMPLE .Main BSET Control_reg, #IT_enable Enable Periph interrupt Clear register interrupt enabled .Int_routine BRES Status_reg, #IT_flag IRET
Avoid process same interrupt forever Return from interrupt
Microcontroller Training CORE
WATCHDOG Overview
PURPOSE DETECT OCCURENCE SOFTWARE FAULT. MUST REGULARLY REFRESHED PROGRAM WDCR, #$FF Reload DIFFERENT WATCHDOG SELECTED OPTION MASK Hardware Watchdog automatically activated upon reset Software watchdog activated software (bit Once activated, cannot disabled ACTIVATED, WATCHDOG USED 7-BIT TIMER
Microcontroller Training CORE
WATCHDOG Overview
RESET WATCHDOG HALT instruction generates reset watchdog activated Watchdog used generate software reset (bit WDCR, #$80 Reset WDCR 12288 12288 clock cycles 1.54 Fcpu 8MHz WDCR 12288 786432 clock cycles 98.30 Fcpu 8MHz
Microcontroller Training CORE
WATCHDOG Block diagram
Reset Activation active set)
WDGF
Watchdog Status Register
WDGA
7-bit Down Counter
Watchdog Control Register
Fcpu
Clock Divider ÷12288
Microcontroller Training CORE
CONSUMPTION MODES Overview
MAXIMUM CONSUMPTION WITH FOSC REACH LOWEST POWER CONSUMPTION Switch unused peripherals Configure I/Os input without pull-up pull-down resistors lowest oscillator frequency possible Slow mode, Wait mode better Halt mode DATA RETENTION VOLTAGE HALT MODE
Microcontroller Training CORE
CONSUMPTION MODES Slow mode
GOAL REDUCE CONSUMPTION REDUCING CLOCK SPEED ENTER CONFIGURING MISCELLANEOUS REGISTER CAUSES CLOCK SLOW DOWN ST72251 Fosc divided rather than ST72311 ST725xx Fosc divided rather than EXIT CONFIGURING MISCELLANEOUS REGISTER
Microcontroller Training CORE
CONSUMPTION MODES Wait mode
GOAL REDUCE CONSUMPTION WHILE MONITORING EXTERNAL EVENTS ENTER EXECUTION INSTRUCTION CAUSES MICRO SOFTWARE FROZEN Program execution stopped Memory registers remain unchanged oscillator still provides clock peripherals EXIT Reset (Watchdog, reset pin) Internal interrupts (timer timer A/D, etc) External interrupts (I/O ports)
Microcontroller Training CORE
CONSUMPTION MODES Halt mode
GOAL REDUCE CONSUMPTION LOWEST VALUE ENTER EXECUTION HALT INSTRUCTION CAUSES MICRO FROZEN Program execution stopped Memory registers remain unchanged oscillator stopped EXIT External Reset External interrupts (I/O ports)
Microcontroller Training CORE
PROGRAMMING TIPS Consumption Modes
DURING WAIT MODE HALT MODE, (INTERRUPT BIT) REGISTER AUTOMATICALLY RESET ENABLE INTERRUPT TYPICAL CONSUMPTION (FOR ST72251) mode (Vdd=5V, Fcpu=8MHz) Slow mode (Vdd=5V, Fcpu=8MHz) Wait mode (Vdd=5V, Fcpu=8MHz) Halt mode (Vdd=5V)
Microcontroller Training CORE
PROGRAMMING TIPS Consumption Modes
AFTER EXITING FROM CONSUMPTION MODE, MICRO WAITS 4096 CLOCK CYCLE (STABILIZATION TIME) BEFORE BEING OPERATIONAL SOURCE THAT ALLOWS EXIT FROM HALT MODE
Reset
ST72251 ST72311 ST725xx
Wfi-Halt Wfi-Halt Wfi-Halt
Timer
Timer
E2prom
Wfi-Halt Wfi-Halt Wfi-Halt
Microcontroller Training CORE
Other recent searches
WP103IDT - WP103IDT WP103IDT Datasheet
US1A - US1A US1A Datasheet
US1M - US1M US1M Datasheet
REJ03B0014-0400 - REJ03B0014-0400 REJ03B0014-0400 Datasheet
74VHC126 - 74VHC126 74VHC126 Datasheet
1639330000 - 1639330000 1639330000 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
