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Interfacing the MC68HC11 to the HCTL-2020 Application Brief M-023

This application brief describes two interfaces for the HCTL-2020 to the MC68HC11. One is a port interface and the other is a bus interface.

Interfacing the MC68HC11 to the HCTL-2020 Application Brief M-023
Introduction
This application brief describes two interfaces for the HCTL-2020 to the MC68HC11. One is a port interface and the other is a bus interface.
Port Interface
The connections are shown in Figure 1, the schematic titled "Port Interface". Port C is used to read the data in and 3 pins on port B are used for the control signals to the HCTL-2020. The E clock from the 68HC11E9 is used to clock the HCTL-2020. In this interface it is assumed that the 68HC11E9 is in the single chip mode. The subroutines to read from the HCTL-2020 and to reset the HCTL-2020 follow.
PUT PORT C IN INPUT MODE. SEL LO AND OE LO. HIGH BYTE OF DATA IN REG. A. SEL HI AND OE LO. LO BYTE IN REG. B. REGISTER IX HAS THE 16 BIT VALUE FROM THE HCTL-2020 SEL HI AND OE HI. RESTORE REG B FROM STACK. RESTORE REG A FROM STACK.
RSTLO. RSTHI.
5964-3770E
U1 8 XT 7 EX 17 19 18 2 RESET IRQ XIRQ MODB PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R / W 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 1 2 3 4 5 6 7 8 9 10
34 PA0 33 PA1 32 PA2 43 44 45 46 47 48 49 50 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7
Vcc U2 DO CLK SEL OE U / D NC RST CHB CHA VSS HCTL-2020 VDD D1 D2 D3 CNTDCDR CNTCAS D4 D5 D6 D7 20 19 18 17 16 15 14 13 12 11
52 VRH 51 VRL
68HC11E9 NOTE: 68HC11E9 IS IN THE SINGLE CHIP MODE. REFER TO THE 68HC11E9 REFERENCE MANUAL FOR DETAILS.
Figure 1. Port Interface Schematic.
Bus Interface
In applications where the expanded-mode is already being used, it is convenient to use the bus interface to the HCTL-2020. Figure 2, "Bus Interface Control Signals", is the schematic diagram to generate the control signals in the expanded mode. The subroutines to read and reset follow.
THIS SUBROUTINE READS A VALUE FROM THE HCTL-2020. THE HIGH BYTE OF DATA IS RETURNED IN REG IY IN THE CORRECT ORDER OF HIGH AND LOW BYTES. THE TWO BYTES ARE MAPPED AT THE MEMORY LOCATIONS AT 0CFFOh AND 0CFF1h RESPECTIVELY.
SEL MC68HC11 BUS E AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 1 11 U2 U1 D0 D1 D2 D3 D4 D5 D6 D7 OC G 74HC373 A8 A9 A10 A11 A12 A13 A14 A15 9 10 U3C 8 74HC00 12 13 U3D 11 74HC00 1 2 3 4 U5 5 6 74HC30 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 1 2 3 A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 1 2 U3A 3 74HC00 4 5 U3B 6 74HC00 OE
1 U4A 2 4 5 74HC20
74HC32
G1 G2A G2B 74HC138
SIGNALS ARE ACTIVE LOW.
NOTE: ALL
Figure 2. Bus Interface Control Signals.