This application brief describes interfaces HCTL-2020 MC68HC11. port i
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Interfacing MC68HC11 HCTL-2020 Application Brief M-023
This application brief describes interfaces HCTL-2020 MC68HC11. port interface other interface.
;THIS SUBROUTINE USED READ DATA FROM HCTL-2020 ;FOR PORT INTERFACE. ;THE SUBROUTINE RETURNS DATA FROM HCTL;2020 REGISTER DENOTES ACTIVE SIGNALS. RD2020: PSHA PSHB LDAA#00 STAA$1007 LDAA#0FA STAA$1004 LDAA$1003 LDAB#0FB STAB$1004 LDAB$1003 XGDX LDAA#0FF STAA$1004 PULB PULA ;SAVE STACK.
Port Interface
connections shown Figure schematic titled "Port Interface". Port used read data pins port used control signals HCTL-2020. clock from 68HC11E9 used clock HCTL-2020. this interface assumed that 68HC11E9 single chip mode. subroutines read from HCTL-2020 reset HCTL-2020 follow.
;PUT PORT INPUT MODE. ;SEL ;HIGH BYTE DATA REG. ;SEL BYTE REG. ;REGISTER VALUE FROM ;THE HCTL-2020 ;SEL ;RESTORE FROM STACK. ;RESTORE FROM STACK.
;THIS SUBROUTINE USED RESET HCTL-2020 ;PORT INTERFACE. RST2020: PSHA LDAA#0EF STAA$1004 LDAA#0FF STAA$1004 PULA
;RST*LO. ;RST*HI.
5964-3770E
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RESET XIRQ MODB MODA
HCTL-2020 CNTDCDR CNTCAS
68HC11E9 NOTE: 68HC11E9 SINGLE CHIP MODE. REFER 68HC11E9 REFERENCE MANUAL DETAILS.
Figure Port Interface Schematic.
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Interface
applications where expanded-mode already being used, convenient interface HCTL-2020. Figure "Bus Interface Control Signals", schematic diagram generate control signals expanded mode. subroutines read reset follow.
;THIS SUBROUTINE READS VALUE FROM HCTL-2020. HIGH ;BYTE DATA RETURNED CORRECT ORDER ;HIGH BYTES. ;THE BYTES MAPPED MEMORY LOCATIONS 0CFFOh ;AND 0CFF1h RESPECTIVELY.
H2020 $0C000 RD2020: H2020
;THIS SUBROUTINE USED RESET HCTL-2020. RESET ;SIGNAL MAPPED MEMORY LOCATION 0CFF2h. REST2020 $0CFF2 RST2020: PSHA LDAA REST2020 PULA
;READ LOCATION $CFF2 CAUSE RESET
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MC68HC11 74HC373 74HC00 74HC00 74HC30 74HC00 74HC00
74HC20
74HC32
74HC138
SIGNALS ACTIVE LOW.
NOTE:
Figure Interface Control Signals.
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