certain applications becomes necessary interface HCTL2020 (Digital Ana

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

certain applications becomes necessary interface HCTL2020 (Digital Ana

Datasheet Thumbnail

Top Searches for this datasheet

Simple Interface HCTL-2020 with 16-bit without Using Processor Application Brief M-020
certain applications becomes necessary interface HCTL2020 (Digital Analog Converter) without having processor micro controller. typical block diagram shown Figure simple circuit with easily available components used. Analog Devices 16-bit shown. 8-bit interface signals control loading high bytes from HCTL-2020 called (High Byte Enable) (Low Byte Enable) respectively. These signals active signals. LDAC signal connected ground tied LBE. signal tied ground. Please refer data sheets detailed timing diagrams. different operations needed achieve interface described shown Table last three states Table simplify design. They arbitrarily selected. example, they used reset inhibit HCTL-2020 dummy read. order simplify design they have been chosen
Table
Remarks ;enable byte from HCTL-2020, ;load byte into with ;HBE signal. ;complete loading process. ;enable byte from HCTL;2020, load byte into ;with signal. ;complete loading process. ;pull high complete inhibit ;reset HCTL-2020. ;The above three sets states have ;been added total states.
here. Note that cannot used corresponds enabling HCTL-2020 569. After this last state circuit made start from beginning therefore repeat read HCTL-2020, write cycle. Note: using 16-bit with 8-bit interface, only 16-bit interface, consider using signals
enable external latches connected bytes respectively shown Figure design consists dividing main clock using 74LS193 counter, combining 8-states give sequence steps described above each signal. diagrams shown "Sequencer Control Signals Timing Diagram"
5964-3767E
2-259
"Truth Table" descriptive process. signal realized with gate. similar manner other signals constructed also. logic gate diagram sequencer control signals shown Figure maximum rate which updated with count equal main clock rate into HCTL-2020 divided
HCTL-2016 DATA
ANALOG
SEQUENCER
(FOR 16-BIT WITHOUT 8-BIT LOAD CAPABILITY BELOW) FROM HCTL-2020 BITS
LATCH 8-BIT ENABLE
LATCH 8-BIT ENABLE
ANALOG
16-BIT ENABLE LATCH 8-BIT
Figure Interfacing HCTL-2020 with 16-bit 569.
Truth Table Note: CLK/2 CLK/4 CLK/8
2-260
RESISTOR
74LS14
74LS14 LOAD 74LS193 RESET HCTL-2020 74LS04
CAPACITOR
74LS32
74LS32
74LS32
74LS32
NOTE: MAIN CLOCK THAT CLOCKS HCTL-2020
Figure Sequencer Control Signals Logic Diagram.
Figure Sequencer Control Signals Timing Diagram.
2-261

certain applications becomes necessary interface HCTL2020 (Digital Ana

Top Searches for this datasheet

Other recent searches