Download

PDF Abstract Text:

A Simple Interface for the HCTL-2020 with a 16-bit DAC without Using a Processor Application Brief M-020

Table 1.

A Simple Interface for the HCTL-2020 with a 16-bit DAC without Using a Processor Application Brief M-020
Introduction
In certain applications it becomes necessary to interface the HCTL2020 to a DAC (Digital Analog Converter) without having to use a processor or micro controller. A typical block diagram is shown in Figure 1. A simple circuit with easily available components can be used. The Analog Devices AD 569 16-bit DAC is shown. It has an 8-bit interface and signals to control the loading of the high and low bytes from the HCTL-2020 called HBE (High Byte Enable) and LBE (Low Byte Enable) respectively. These signals are active LO signals. The LDAC signal on the AD 569 can be connected to ground or tied to LBE. The CS signal is tied to ground. Please refer to the data sheets for the DAC AD 569 for detailed timing diagrams. The different operations needed to achieve the interface can be described as shown in Table 1. The last three states in Table 1 simplify the design. They can be arbitrarily selected. For example, they can be used to reset the inhibit in the HCTL-2020 by dummy read. In order to simplify the design they have been chosen
Table 1.
SEL LO OE LO HEB LO LBE HI Remarks enable the HI byte from HCTL-2020, load the byte into the DAC with the HBE signal. complete the loading process. enable the LO byte from the HCTL 2020, load the byte into the DAC with the LBE signal. complete the loading process. pull OE high to complete inhibit reset of HCTL-2020. The above three sets of states have been added to get a total of 8 states.
to be HI here. Note that LO on all cannot be used as it corresponds to enabling the HCTL-2020 and the AD 569. After this last state the circuit is made to start from the beginning and therefore repeat the read to the HCTL-2020, write to the DAC cycle. Note: If you are using a 16-bit DAC with no 8-bit interface, but only a 16-bit interface, consider using the signals HBE and LBE
to enable external latches connected to the HI and LO bytes of the DAC respectively as shown in Figure 1. The design consists of dividing the main clock by 2, 4 and 8 using a 74LS193 counter, and combining the 8-states to give the sequence of steps described above for each signal. The diagrams shown in "Sequencer and Control Signals Timing Diagram" and
5964-3767E
"Truth Table" are descriptive of the process. The SEL signal can be realized with an OR gate. In a similar manner the other signals can be constructed also. A logic gate diagram of the sequencer and control signals is shown in Figure 2. The maximum rate at which the DAC is updated with a new count is equal to the main clock rate into the HCTL-2020 divided by 8.
HCTL-2016 CLK SEL OE DATA 8 8 MSB
AD 569 ANALOG OUT
CHA CHB
SEQUENCER
(FOR A 16-BIT DAC WITHOUT 8-BIT LOAD CAPABILITY SEE BELOW) FROM HCTL-2020 8 BITS
LATCH 8-BIT ENABLE
ANALOG OUT
16-BIT DAC LBE ENABLE 8 LATCH 8-BIT 8 LSB
Figure 1. Interfacing the HCTL-2020 with the 16-bit DAC AD 569.
R1 RESISTOR
U4A 1 74LS14 2 3
U4B 4 74LS14 U1 15 1 10 9 Vcc CLK 5 UP 4 DN 11 LOAD 14 CLR 74LS193 CO BO 12 13 A B C D 3 QA 2 QB 6 QC 7 QD TO RESET OF HCTL-2020 1 2 U2A 3 U3A 2 74LS04 4 5 U2B 6 12 13 U2D 11 HBE SEL OE 9 10 U2C 8 LBE
C1 CAPACITOR
74LS32
Figure 2. Sequencer and Control Signals Logic Diagram.
Figure 3. Sequencer and Control Signals Timing Diagram.