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Interfacing the HCTL-1100 to the 8051 Application Brief M-015

HCTL-1100 / 8051 Interfaces

Interfacing the HCTL-1100 to the 8051 Application Brief M-015
HCTL-1100 / 8051 Interfaces
brief. There is only a marginal performance difference between the two approaches. The execution times for these routines are listed in Table 1. These execution times do not include stack operations and subroutine overhead. The HCTL-1100 bus interface circuit is capable of supporting four HCTL-1100s with no additional logic. If an I / O port based design requires more than one HCTL-1100, the interface
would require only two additional I / O port lines per chip. These lines would control OE (Output Enable) and CS (Chip Select) for each of the individual HCTL-1100s. If there is an inadequate number of I / O port lines available for this purpose, a separate decoder chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s.
5964-3776E
Read Operation 15 µs at 12 MHz 180 Clock Per. 12 µs at 12 MHz 144 Clock Per.
Write Operation 13 µs at 12 MHz 156 Clock Per. 6 µs at 12 MHz 72 Clock Per.
PHA PHB PHC PHD MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 SIGN PULSE
22 pF 18 9 X2 RESET
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
RD WR T0 T1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 8051
R / W OE CS ALE RESET
CHA CHB INDEX PROF INIT LIMIT STOP Vcc
EXT CLK HCTL 1100
14 B 2MHz OSC 7
Figure 1. Interfacing the HCTL-1100 to the 8051 Using I / O Ports.
HCTL-1100 READ / WRITE ROUTINES THIS SOFTWARE IS USED IN CONJUNCTION WITH THE HCTL-1100 / 8051 I / O PORT INTERFACE SUBROUTINE RD1100 READS HCTL REG POINTED TO BY B AND RETURNS REG VALUE IN ACC RD1100: SETB P2.0 SET R / W LINE TO READ MOV CLR SETB MOV CLR SETB NOP NOP NOP CLR MOV SETB RET 2-242 P1, B P2.3 P2.3 P1, #0FFH P2.2 P2.2 LATCH ADDRESS PULSE ALE
PULSE CS DELAY 4µS ALLOW ENOUGH TIME FOR 1MHz HCTL-1100 OR FASTER
P2.1 A, P0 P2.1
SET R / W LINE TO WRITE SEND DATA PULSE CS RETURN R / W TO READ MODE
BRING RESET LINE HIGH
PHA PHB PHC PHD MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 SIGN PULSE
25 27 28 29 18 19 20 21 22 23 24 25 17 18 31 30 33 12 13 14 15 Vcc
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
4 5 74LS00
G1 G2A G2B 74LS138 10 9 74LS00
14 B 2MHz OSC 7
RESET 1 µF TO 8051 BUS 10 32 HCTL-1100 11 35
74LS00
74LS138
18 Vcc
Figure 2. Interfacing the HCTL-1100 to the 8051 Using the Address / Data Bus.
HCTL-1100 READ / WRITE ROUTINES THIS SOFTWARE IS USED IN CONJUNCTION WITH THE HCTL-1100 BUS INTERFACE HCTL-1100 ADDRESS OE1100 EQU 060H CS1100 EQU 061H
SUBROUTINE RD1100 READS HCTL REG POINTED TO BY B AND RETURNS REG VALUE IN ACC RD1100: PUSH PUSH MOV MOV MOVX NOP NOP MOV MOVX POP POP RET DPL DPH DPH, #CS1100 DPL, B A, @DPTR SAVE DATA POINTER
POINT TO BASE CS ADDRESS LOAD REG ADDRESS IN LOWER 8 BITS OF DATA POINTER LATCH HCTL-1100 REG ADDRESS ALLOW ENOUGH TIME FOR 1MHz CLK (NOT REQUIRED FOR 2MHz HCTL-1100 CLK) POINT TO BASE OE ADDRESS READ BYTE FROM HCTL-1100 RESTORE DATA POINTER
DPH, #OE1100 A, @DPTR DPH DPL
SUBROUTINE WR1100 LOADS HCTL-1100 REGISTER POINTED TO BY B WITH VALUE IN ACC WR1100: PUSH PUSH MOV MOV MOVX POP POP RET DPL DPH SAVE DATA POINTER
DPTR, #CS1100 POINT TO BASE CS ADDRESS DPL, B LOAD REG ADDRESS IN LOWER 8 BITS OF DATA POINTER @DPTR, A WRITE BYTE TO HCTL-1100 DPH DPL RESTORE DATA POINTER