Intersil HSP45116/HSP45116A Numerically Controlled Oscillator/Modulato

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Intersil HSP45116/HSP45116A Numerically Controlled Oscillator/Modulato

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Using HSP45116/HSP45116A Complex Multiplier Accumulator
Intersil HSP45116/HSP45116A Numerically Controlled Oscillator/Modulator also used high speed 16-Bit Multiplier/Accumulator (CMAC). This technical briefing details part configuration perform such functions; provides functional block diagram interface circuit that required, shows timing diagrams data control signals involved. features HSP45116/HSP45116A configured CMAC include: 33MHz Output Rate Complex Vector (HSP45116) 52MHz Output Rate Complex Vector (HSP45116A) 16-Bit Complex Inputs 20-Bit Complex Output 32-Bit Internal Accumulator Two's Complement Offset Binary (Unsigned) Outputs Available Peak Growth Accumulator Available through Status Pins HSP45116A additionally provides higher speed operation 52MHz, available MQFP. HSP45116/HSP45116A combines high performance quadrature numerically controlled oscillator high speed 16-bit complex multiplier/accumulator. utilize HSP45116 HSP45116A CMAC only, number input pins have logic levels specified attached Settings Complex Multiplier Operation Table. These assignments necessary order bypass operations Numerically Controlled Oscillator (NCO) advance data directly CMAC portion device. order accomplish proper data alignment within part, some external interface circuitry required illustrated functional block diagram Figure Each complex input includes real imaginary component. Notice that while first complex input vector being clocked HSP45116/HSP45116A through parallel input ports RIN(18:0) IMIN(18:0), second complex input vector being clocked from single 16-bit input port (C(15:0)), clocking complex component time. This implies that clock second complex vector (WR) must twice frequency clock first complex vector (CLK). exact timing relationships between inputs, outputs, control signals, clocks shown Figure Given timing diagram Figure external interface circuit shown Figure then full data alignment accomplished. Figure shows internal block diagram device. block diagram illustrates additional data path second complex vector being input through C(15:0) port follows before lines with first complex vector internal device. addition, this second input vector C(15:0) must transferred CMAC without being altered HSP45116/HSP45116A functions. highlighted signal path second complex vector C(15:0), shows three additional registers that data being clocked through compared with direct path CMAC) first complex vector RIN(18:0) IMIN(18:0) inputs. This three register delay derives requirement external pipeline delays shown Figure data alignment complex vectors. addition, suggested configuration, attached configuration table, allows C(15:0) data flow unaltered operation inputs CMAC. following this internal data path, verify that suggested logic levels assure transparent transfer data CMAC portion HSP45116/HSP45116A. Note that maximum data size second complex input vector bits, each real imaginary components, while data size first complex input through RIN(18:0) IMIN(18:0) accommodate longer length.
http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
Technical Brief
PIPELINE DELAY CLKS)
RIN(18:0)
PIPELINE DELAY CLKS)
IMIN(18:0)
RO(19:0) IO(19:0)
HSP45116 HSP45116A C(15:0)
NOTE: Refer Figure timing relationship between input signals, control signals clocks. FIGURE INTERFACE BLOCK DIAGRAM UTILIZING HSP45116/HSP45116A CMAC
RIN(18:0) IMIN(18:0) C(15:0) AD(1) RO(19:0) IO(19:0)
NOTES: Timing assumes accumulations complex product. Accumulations accomplished controlling input (refer Data Book). XR(n) This represents real data first input vector. XI(n) YI(n) This represents imaginary data first input vector. This represents imaginary data second input vector. FIGURE TIMING DIAGRAM HSP45116/HSP45116A USED CMAC YR(n) This represents real data second input vector.
Technical Brief
IMIN(18:0)
IMIN(18:0) RIN(18:0) MOD(1:0) ENCODE PHASE INPUT REGISTER C(15:0) PHEN R.ENPHREG PHASE REGISTER
RIN(18:0)
R.PMSEL
INPUT REGISTER
CENTER FREQUENCY REGISTER
FREQUENCY ADDER SIN/COS ARGUMENT
MSEN
PHASE
INPUT REGISTER
OFFSET FREQUENCY R.ENCFREG REGISTER
AD(1:0)
SINE/COSINE GENERATOR
LSEN DECODER R.ENOFREG
R.CLROFR R.PMSEL R.ENPHREG R.ENCFREG R.ENOFREG R.CLROFR R.LOAD R.ENPHAC R.MODPI/2PI R.RBYTILD R.ENTIREG PHASE ACCUMULATOR ADDER PHASE ACCUMULATOR REGISTER PACO
PHASE ACCUMULATOR
PMSEL ENPHREG ENCFREG ENOFREG CLROFR LOAD ENPHAC MODPI/2PI RBYTILD ENTIREG
PHASE ADDER
MSBs
R.ENPHAC R.LOAD PACI R.MODPI/2PI SH(1:0) PEAK BINFMT
R.SH(1:0) R.RBYTILD R.SH(1:0) R.ENI R.ACC R.PEAK R.BINFMT
PACI
LSBs
R.ENI R.ACC R.PEAK R.BINFMT
TIME ACCUMULATOR REGISTER
CARRY
OEIEXT OEREXT OUTMUX(1:0)
ADDER
TIME INCREMENT
TICO
R.ENTIREG
TIME ACCUMULATOR
TICO PACO
FIGURE BLOCK DIAGRAM HSP45116/HSP4511A SHOWING SIGNAL PATHS WHEN USED CMAC
Technical Brief
IMIN(18:0) RIN(18:0) R.ENI RIN(18:0) SHIFTER PHASE IMIN0-18 SHIFTER R.SH(1:0)
COMPLEX MULTIPLIER
ADDER R1.ACC
ADDER
R.RBYTILD
COMPLEX ACCUMULATOR
R2.ACC
ROUND
ADDER
ADDER
ROUND CMAC ACCUMULATOR
R1.ACC
R.PEAK
R.ACC
OUTMUX(1:0)
OUTMUX(1:0)
R.SH(1:0) R.ENI R.PEAK R.BINFMT
OEIEXT OEREXT
R.BINFMT
R.ENI
OUTMUX(1:0)
RO(19-16) RO(15:0)
DET(1:0)
IO(19-16) IO(15:0)
FIGURE BLOCK DIAGRAM HSP45116/HSP4511A SHOWING SIGNAL PATHS WHEN USED CMAC (Continued)
R.SH(1:0)
GROWTH DETECT
OUTMUX(1:0)
Technical Brief Settings Complex Multiplier Operation
NAME NUMBER (HSP45116) NUMBER (HSP45116A) TYPE DESCRIPTION
A15, J15, 102, 111, 124, 132, 145, A14, H15, P15, 108, 114, 119, 125, 131, 143, 54-61, 63-70 2-19,
C(15:0) AD(1:0) ENPHREG ENOFREG ENCRFEG ENPHAC ENTIREG MODPI/2PI CLROFR LOAD MOD(1:0) PMSEL RBYTILD PACI PACO3 TICO3 RIN(18:0)
N8-11, P8-13, Q9-14 E1-3, F1-3, J1-3, A2-7, B2-7, C3-8,
Input real imaginary complex vectors. Selects write alternatively data from C(15:0). Chip Select Writes C(15:0) data, must twice clock frequency. Clock Logic "0". Logic "1". Logic "0". Logic "0". Logic "0". Logic "0". Logic "0". Logic "0". Logic "0". Both pins Logic "0". Logic "0". Logic "0". Logic "1".
Input real data input vectors with imaginary data IMIN(18:0). Input imaginary data input vectors with real data RIN(18.0) Shift Control Inputs. These lines control input shifters inputs complex multiplier. shift controls common shifters both busses. Accumulate/Dump Control. This input controls complex accumulators their holding registers. When high, accumulators accumulate holding registers disabled. When low, feedback accumulators zeroed cause accumulators load. holding registers enabled clock results accumulation. This input registered CLK.
IMIN(18:0) SH(1:0)
138-142, 144, 146-156,
Technical Brief Settings Complex Multiplier Operation
NAME BINFMT NUMBER (HSP45116) NUMBER (HSP45116A) TYPE (Continued)
DESCRIPTION This input used convert two's complement output offset binary (unsigned) applications using converters. When low, bits RO19 IO19 inverted from internal two's complement representation. This input registered CLK. This input enables peak detect feature block floating point detector. When high, maximum growth output holding registers encoded output DET(1:0) pins. When PEAK input asserted, block floating point detector output will track maximum growth holding registers, including data holding registers time that PEAK activated. Logic "0". These three state outputs controlled OEREXT. OUTMUX(1:0) select data output bus.
PEAK
OUTMUX(1:0) RO(19:0)
N12, C15, D14, D15, E14, E15, F13-15, G13-15, H13, H14, J13, J14, K13-15, L15, A10-13, B8-15, C9-14, D13, N15,
84-86, 88-91, 93-94, 96-97, 99-101, 103-107, 110, 112-113, 115-118, 121-123, 126-130, 133-137
IO(19:0)
Imaginary output data bus. These three-state outputs controlled OEIEXT. OUTMUX(1:0) select data output bus. These output pins indicate number bits growth accumulators. While PEAK low, these pins indicate peak growth. detector examines bits 15-18, real imaginary accumulator holding registers bits 30-33 real imaginary CMAC holding registers. bits indicate largest growth four registers. Three-state control bits RO(15:0). Outputs enabled when line low. Three-state control bits RO(19:16). Outputs enabled when line low. Three-state control bits IO(15:0). Outputs enabled when line low. Three-State control bits IO(19:16). Outputs enabled when line low. Round enable (available HSP45116A only). This input enables rounding output data precision from bits (see HSP45116A Description Operation). This input active "low". This input must tied either high low.
DET(1:0)
OEREXT OEIEXT
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Intersil HSP45116/HSP45116A Numerically Controlled Oscillator/Modulato

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