TB310.1 Loads many coefficients. Only "half" coefficients (includ
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HSP43220: Common Configuration Problems Avoid
TB310.1
Loads many coefficients. Only "half" coefficients (including center tap) needed. Loading more less coefficients will cause incorrect operation. Improper reset part. Both clocks must active during reset. Both start pins high during reset remain high until programming complete. Starting part soon. Under software control, start pins float momentarily before programming complete. Once started, writes coefficients ignored. DECIMATE, designer tries bypass setting Hdec Stages correct settings HDec Stages designer violating CK_IN duty cycle requirements when bypassed. A.C. Specifications data sheet. designer confuses even/odd symmetry with even/odd length filters. designer tries bypassed with CK_IN FIR_CK. designer thinks that taking start inactive will stop part. Only reset stop Section once been started. intermittent poor results from using quality cheap socket poor part insertion. General input rise/fall time slow (>10ns), input setup/hold violations, noise. System board problems causing incorrect acquisition outputs from DDF. i.e., multiplexed structure there contention. designer does realize data held outputs until next DATA_RDY. designer does relax passband attenuation much possible valuable taps wasted.
Debug Ideas
Bypass Sections individually together. clocks tied together Section pseudo bypassed setting HDRATE usual, GROWTH STAGES will output every input sample. This will verify correct wiring DATA_IN some C_BUS bits. Read coefficients memo. writing F_DIS then F_DIS before loading coefficients. this helps then poor reset procedure floating start pins likely. Input value, should pass through pass filter. DATA_RDY's correct frequency? (CK_IN/(Hdec+Fdec).
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