HSP48410 Histogrammer/Accumulating Buffer several modes; these Histogr

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Histogramming With Variable Pixel Increment
HSP48410 Histogrammer/Accumulating Buffer several modes; these Histogram mode, which part computes histogram input data stream, accumulate mode, which computes totals rank-ordered data. These operations work generalized digital data, purposes this tech brief, image data will used example. Histogram mode (Figure HSP48410 accepts pixel data PIN0-9 bus. uses this information address internal compute number pixels image that each gray level. contents given address into adder; other input adder zeroes except LSB. output adder written back into same location. When pixels have been processed chip, contains histogram image. When placed Accumulate mode (Figure HSP48410 operates similar manner, except that inputs adder come from DIN0-23 input bus. this mode, user loads with desired increment value. Since this synchronous input, changed pixel pixel basis. When operation finished, completed histogram will stored before. Figure shows implementation latter function using TMS320 system microprocessor. circuit diagram timing were derived from TMS320C25 data sheet 1989 Second Generation User's Guide. This circuit been verified with physical implementation. Initially, part Accumulate mode (FCT 100). memory reset with (Flash Clear) prior data processing. input image data latched into PIN0-9, histogram increment that pixel simultaneously loaded into DIN0-23. internal pipeline delays align sets data internally that proper histogram incremented with right number. SYNC signal used flag beginning frame data, stays while image data being into part. When frame image data been processed, histogram read memory over microprocessor interface. After START brought high, TMS320 uses FCT0-2 lines configure part Asynchronous mode (FCT 111). contents bins read asynchronously pixel clock random order. START 4-remains high during this operation.
ADDRESS
START
START CONTROL
FIGURE HISTOGRAMMER MODE BLOCK DIAGRAM
FIGURE ACCUMULATE MODE BLOCK DIAGRAM
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ADDRESS GENERATOR
ADDRESS GENERATOR
CONTROL
0-23
0-23
ADDRESS
0-23
Technical Brief
PIXEL ADDRESS
INCREMENT DIO0-15 DECODE DIN0-23 PIN0-9 IOADD0-9 FCT0-2
A1-A10 A0-A2 DECODE
DATA0-15 A0-A10 A11-A15
PIXEL DATA SYNC
START
74AS04
74AS32 PIXEL CLOCK
STRB 74AS32
HSP48410
READY WAIT STATE GENERATOR WAIT STATE) 74AS30 (UNUSED INPUTS TIED HIGH)
MICRO PROCESSOR (TMS320)
FIGURE HSP48410 CIRCUIT SHOWING INTERFACE TMS320 DYNAMIC PIXEL INCREMENT
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