HA-5020 cost single amplifier optimized video applications gains betwe

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HA-5020 cost single amplifier optimized video applications gains betwe

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HA-5020 SPICE Macromodel (CFA)
HA-5020 cost single amplifier optimized video applications gains between current feedback amplifier; thus yields less bandwidth degradation high closed loop gains than voltage feedback amplifiers. HA-5020 also features disable function that significantly reduces supply current while forcing output true high impedance state. macromodel HA5020 PSPICE (registered trademark MicroSim Corp.) compatible, compatible with other simulation programs well. model file ASCII format viewed/edited with text editor. models require trade-off between accuracy complexity (simulation time). Intersil's models emulate nominal performance typical device, designed match typical performance curves device data sheet. SPICE simulations should considered substitute breadboarding circuit; rather, they should used select preliminary component values verify validity design approach. rely simulations predict device performance when deviating from operating conditions specified data sheet (e.g. just because model works with supplies, don't assume that actual amplifier does). Instead, refer data sheet performance curves, call factory assistance (407-727-9207). HA-5020 model configured subcircuit easy incorporation into larger circuit files. When using PSPICE, call subcircuit from level circuit file adding .LIB statement point file containing subcircuit (e.g. .lib c:\models\ha5020.cir), including subcircuit call following form: xname ENABLE model name (e.g. HA5020) Note that node order subcircuit call follows industry standard, order also documented comment section beginning model file. slew limiting negative input fractional step feed-through from positive input negative input. Other elements model voltage current limiting negative input. bias current positive input high frequency voltage gain also accounted input buffer section model. output section transimpedance amplifier constructed from four stages: current probe, stage, frequency transfer, output drive. current probe stage monitors current through negative input also models input offset voltage. stage used bias current negative input power supply gains. This stage also used capture operation output transimpedance amplifier while disabled. frequency transfer block consists poles zeros modelling high frequency open-loop transimpedance gain. output drive stage accounts several characteristics including: output slew limits resulting transimpedance gain bandwidth product, saturation delay times, voltage current limiting output. enable section model used control certain characteristics other blocks model. This section operates according voltage level enable input status output pin. characteristics output which controlled this section impedance slew limiting. internal bias currents input buffer section also enable section. result, high impedance states achieved input pins whenever amplifier disabled. addition three main functional sections, smaller constructs individual components used model other important amplifier characteristics. Specifically, section used capture change voltage limits output function current through negative input. Power supply currents also modelled with additional section. each amplifier pin, several individual components included model high frequency impedance characteristics, including significant package parasitics. model optimized operation ±5V, operates over full range supply voltages. Beware, model does simulate various breakdown conditions such exceeding maximum ratings, does have input limiting. model does include input voltage current noise, temperature effects. poles zeros transimpedance frequency transfer section have been located with great care insure that performance different inverting non-inverting gains matched closely curves given data sheet. Also, pole/zero placement insures that transient response matches that shown data sheet.
Model Description
macromodel schematic shown Figure PSPICE listing macromodel follows. model topology consists three main functional sections: buffer between input pins, output section between negative input output pin, enable section. topology input buffer section basic four transistor voltage follower. This configuration used order efficiently model Enable capability amplifier. Additional components added this structure order model critical characteristics actual amplifier. these additional components, some used model both
http://www.intersil.com 407-727-9207 Copyright
Intersil Corporation 1999
Application Note MM5020
IQIP CIP2
MACROMODEL OUTPUT STAGE (SEE BELOW) MOUT
VGRO
CIM2 CIN2
VCPI
FIGURE HA-5020 AMPLIFIER MACROMODEL SCHEMATIC
FREQUENCY TRANSFER (SIMPLE POLE/ZERO PAIRS) RZ1A RZ2A
MID-STAGE WITH BIASING POWER SUPPLY DEPENDENCE CURRENT PROBE OFFSET VOLTAGE RITV HITV
GMI2 GMI3 GINA
AMPLIFIER OUTPUT DRIVE WITH LIMITING MOUT GOUTA GRDP
FIGURE HA-5020 MACROMODEL OUTPUT STAGE
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
Application Note MM5020
ENABLE CAPABILITY
OUTPUT VOLTAGE LIMITING INPUT CURRENT
POWER SUPPLY CURRENT GENERATOR
I(OUT)
FIGURE HA-5020 MACROMODEL ADDITIONAL SUPPORT CIRCUITS
HA-5020 SPICE Macromodel Listing
.SUBCKT HA5020 250N 1.5P 2.5P .MODEL IS=1.0E-16 BF=130 NF=2.2 .MODEL IS=1.0E-16 BF=220 NF=2.5 .MODEL IS=1.0E-16 BF=180 NF=2.2 .MODEL IS=1.1E-16 BF=50 NF=2.5 +3.50000000E+02 CIP2 +2.73661972E-13 +6.70000000E-13 DLIM +3.35000000E-04 DIPL DLIM
Application Note MM5020 HA-5020 SPICE Macromodel Listing
(Continued)
CIN2 .03P +2.60000000E+07 .5PF +3.35000000E-04 DIML DLIM DLIM +6.29914530E-13 CIM2 +3.24501425E-13 +3.50000000E+02 .MODEL DLIM2 N=.01 IS=1E-10 .MODEL BV=+5.26 IBV=1.0E-10 +0.00000000E+00 POLY -2.13000009E-03 +3.09210000E-04 ++3.09210000E-04 -3.15209991E-04 -3.03210009E-04 -1.88100000E-06 ++1.88100000E-06 -1.88100000E-06 +1.88100000E-06 +1.88100000E-06 +-1.88100000E-06 +1.00000000E-16 HITV RITV POLY -1.97000000E-03 POLY +7.80927711E-09 ++2.78640749E-11 +2.78640749E-11 +3.49558407E-11 +2.07723091E-11 -1.92087022E-16 +1.92087022E-16 -1.92087022E-16 ++1.92087022E-16 +1.92087022E-16 -1.92087022E-16 +1.00000000E+00 POLY +0.00000000E+00 +0.00000000E+00 +2.14285714E+03 RZ1A -1.14285714E+03 +7.95798186E-13 GINA +4.66666667E-04 +2.25000000E+03 RZ2A -1.25000000E+03 +3.18319274E-13 +4.44444444E-04 GOUTA -1.00000000E+00 +1.02164070E+01 POLY +3.46573590E-07 +3.46573590E-07 GRDP POLY -5.10970951E+00 -5.10970951E+00 +1.44269504E+06 +1.00000000E-14 +3.32000000E+02 +8.00000000E+00 +1.00000000E+00 +1.00000000E+00 .MODEL IS=+2.16387643E-14 N=.2
Application Note MM5020 HA-5020 SPICE Macromodel Listing
(Continued)
.MODEL IS=+6.45488179E-15 N=.2 POLY -1.10000000E+00 POLY +1.13500000E+00 POLY -1.30520000E-04 +1.30000000E-01 +1.00000000E-10 DLIMVO POLY +2.19120000E-04 +2.20000000E-01 +1.00000000E-10 DLIMVO .MODEL DLIMVO N=.01 IS=1E-20 +1.00000000E+00 POLY -1.75393075E-01 +1.17421768E+00 +1.00000000E+00 POLY +8.82115687E-02 +9.09643047E-01 .MODEL IS=1E-9 +5.78000000E-03 +1.25000000E-01 POLY +1.52098765E-02 -3.04197531E-02 +2.28148148E-02 +-7.60493827E-03 +9.50617284E-04 .MODEL IS=1E-16 N=+3.40657494E+00 POLY +4.00000000E+00 +1.00000000E+00 +-1.00000000E+00 +0.00000000E+00 DLIM DLIM 0.99 DLIM .MODEL DLIM N=.01 IS=1E-20 POLY +1.42857143E+01 GMI2 POLY +2.04356846E-10 -2.04356846E-10 POLY -6.40000000E-01 +1.28000000E+00 DLIM DLIM DLIM POLY +1.25000000E+01 POLY +1.25000000E+01 DLIM +8.00000000E+04 DLIM DLIM +8.00000000E+04 DLIM 0.99 GMI3 POLY -1.10000000E-08 +1.60000000E-08 ++1.10000000E-08 -1.60000000E-08 .ENDS HA5020
Application Note MM5020 HA-5020 Macromodel Performance
Intersil application note AN9523 titled "Evaluation Programs SPICE Models" used guideline evaluating HA-5020 performance. Figure shows noninverting transfer function. gain configuration peaking 2.5dB versus 3.2dB peaking shown data sheet. -3dB bandwidth 125MHz both cases. This quite good correlation between model data sheet. Similarly, non-inverting gains closely match data sheet transfer functions. cases data sheet conditions were during SPICE analysis; i.e., 400, VSUPPLY ±5V, 10pF. inverting transfer function shown Figure Notice that gain configuration peaking 0.5dB versus 1.5dB peaking shown data sheet, that gain curves match those shown data sheet. Again correlation between model data sheet quite good. small signal pulse response shown Figure rise time, fall time, propagation delay, time domain peaking read this waveform.
-120 GAIN TIME (ns)
common mode rejection ratio obtained through identical amplifiers equation CMRR common mode input voltage divided differential input voltage constant output voltage (see Figure input this test chosen square wave. This enables evaluation worst case CMRR.
(mV)
VOUT
FIGURE HA-5020 SMALL SIGNAL PULSE RESPONSE
-2.0 GAIN -4.0 GAIN
(mV)
-6.0 FREQUENCY (MHz)
-1.0 1.3mV CMRR 20LOG 63.7dB -3.0 TIME (ns)
FIGURE HA-5020 NON-INVERTING TRANSFER FUNCTION
-2.0
FIGURE HA-5020 CMRR
-2.0 GAIN -4.0 GAIN GAIN -6.0 FREQUENCY (MHz)
Figures show salient parameters HA-5020. input signal this test sweep which enables evaluation parameters around zero. response stimulus input shown Figure configured non-inverting follower circuit with input voltage switched from ground switch off. slower turn-off time seen figure along with much faster turn-on time.
FIGURE HA-5020 INVERTING TRANSFER FUNCTION
Application Note MM5020
IVEE (mA) VDIS
ENABLED IVCC (mV) TIME (µs) VOUT
FIGURE HA-5020 POWER SUPPLY CURRENT DRAIN
FIGURE HA-5020 ENABLE/DISABLE RESPONSE TIME
Summary
macromodel performs well both parameters. fraction some tests, this acceptable approximation. least model peaking where peaking, response different gains modeled correctly. model just approximation! cannot predict performance percent; especially when considers that circuit layout parameters have such large effect high frequency performance. model will predict actual performance many circumstances such non-linearities, limits performance, extended range operation. Only testing will confirm performance normal operating range, circuits should tested confirm model's predictions.
I(RF1) I(RI) (µA) I(RF1) I(RI)
(mV)
FIGURE HA-5020 INPUT CURRENT
License Statement
information these SPICE macromodels (models) protected United States copyright laws. Intersil Corporation (Intersil) hereby grants users these models, herein referred licensee, nonexclusive, nontransferable license these models long licensee abides terms this agreement. Before using models, licensee should read this license accept terms. licensee sell, loan, rent, lease, license models, whole, part, modified form, anyone outside licensee's company. licensee modify these models suit specific application. These models provided WHERE WITH WARRANTY KIND EITHER EXPRESSED IMPLIED, INCLUDING LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE." event will Intersil liable special, collateral, incidental, consequential damages connection with arising these models. Intersil reserves right make changes products models without prior notice.
(mV) V(13) V(11) V(13)
(mV)
FIGURE HA-5020 INPUT OFFSET VOLTAGE

HA-5020 cost single amplifier optimized video applications gains betwe

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