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Encore!® Series
PS022506-0504 Preliminary
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Document Disclaimer
ZiLOG registered trademark ZiLOG Inc. United States other countries. other products and/or service names mentioned herein trademarks companies with which they associated. ©2004 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Devices sold ZiLOG, Inc. covered warranty limitation liability provisions appearing ZiLOG, Inc. Terms Conditions Sale. ZiLOG, Inc. makes warranty merchantability fitness purpose Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights.
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Table Contents
Introduction Features Part Selection Guide Block Diagram Peripheral Overview Features General Purpose Flash Controller 10-Bit Analog-to-Digital Converter UART Serial Peripheral Interface Timers Interrupt Controller Reset Controller On-Chip Debugger Signal Descriptions Overview Available Packages Configurations Signal Descriptions Characteristics Address Space Overview Register File Program Memory Data Memory Information Area Register File Address Control Register Summary Reset STOP Mode Recovery Overview Reset Types System Reset Reset Sources Power-On Reset Voltage Brown-Out Reset Watch-Dog Timer Reset
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External Reset On-Chip Debugger Initiated Reset STOP Mode Recovery STOP Mode Recovery Using Watch-Dog Timer Time-Out STOP Mode Recovery Using GPIO Port Transition Low-Power Modes Overview STOP Mode HALT Mode General-Purpose Overview GPIO Port Availability Device Architecture GPIO Alternate Functions GPIO Interrupts GPIO Control Register Definitions Port Address Registers Port Control Registers Port Input Data Registers Port Output Data Register Interrupt Controller Overview Interrupt Vector Listing Architecture Operation Master Interrupt Enable Interrupt Vectors Priority Interrupt Assertion Software Interrupt Assertion Interrupt Control Register Definitions Interrupt Request Register Interrupt Request Register Interrupt Request Register IRQ0 Enable High Registers IRQ1 Enable High Registers IRQ2 Enable High Registers Interrupt Edge Select Register Interrupt Control Register Timers Overview Architecture
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Operation Timer Operating Modes Reading Timer Count Values Timer Output Signal Operation Timer Control Register Definitions Timer High Byte Registers Timer Reload High Byte Registers Timer High Byte Registers Timer Control Registers Timer Control Registers Watch-Dog Timer Overview Operation Watch-Dog Timer Refresh Watch-Dog Timer Time-Out Response Watch-Dog Timer Reload Unlock Sequence Watch-Dog Timer Control Register Definitions Watch-Dog Timer Control Register Watch-Dog Timer Reload Upper, High Byte Registers UART Overview Architecture Operation Data Format Transmitting Data using Polled Method Transmitting Data using Interrupt-Driven Method Receiving Data using Polled Method Receiving Data using Interrupt-Driven Method Clear Send (CTS) Operation Multiprocessor (9-bit) Mode External Driver Enable UART Interrupts UART Baud Rate Generator UART Control Register Definitions UART Transmit Data Register UART Receive Data Register UART Status Register UART Status Register UART Control Control Registers UART Address Compare Register UART Baud Rate High Byte Registers
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Infrared Encoder/Decoder Overview Architecture Operation Transmitting IrDA Data Receiving IrDA Data Infrared Encoder/Decoder Control Register Definitions Serial Peripheral Interface Overview Architecture Operation Signals Clock Phase Polarity Control Multi-Master Operation Slave Operation Error Detection Interrupts Baud Rate Generator Control Register Definitions Data Register Control Register Status Register Mode Register Diagnostic State Register Baud Rate High Byte Registers Controller Overview Operation Signals Interrupts Start STOP Conditions Write Transaction with 7-Bit Address Write Transaction with 10-Bit Address Read Transaction with 7-Bit Address Read Transaction with 10-Bit Address Control Register Definitions Data Register Status Register Control Register Baud Rate High Byte Registers Diagnostic State Register
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Diagnostic Control Register Analog-to-Digital Converter Overview Architecture Operation Automatic Power-Down Single-Shot Conversion Continuous Conversion Control Register Definitions Control Register Data High Byte Register Data Bits Register Program Memory Flash Memory Overview Information Area Operation Timing Using Flash Frequency Registers Flash Read Protection Flash Write/Erase Protection Byte Programming Page Erase Mass Erase Flash Controller Bypass Flash Controller Behavior Debug Mode Flash Control Register Definitions Flash Control Register Flash Status Register Page Select Register Flash Sector Protect Register Flash Frequency High Byte Registers Read-Only Memory (ROM) Overview Information Area Code Protection Against External Access Control Register Definitions Page Select Register Option Bits Overview Operation Option Configuration Reset
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Option Address Space Program Memory Address 0000H Program Memory Address 0001H On-Chip Debugger Overview Architecture Operation Interface Debug Mode Data Format Auto-Baud Detector/Generator Serial Errors Breakpoints OCDCNTR Register On-Chip Debugger Commands On-Chip Debugger Control Register Definitions Control Register Status Register On-Chip Oscillator Overview Operating Modes Crystal Oscillator Operation Oscillator Operation with External Network Electrical Characteristics Absolute Maximum Ratings Characteristics Characteristics On-Chip Peripheral Electrical Characteristics General Purpose Port Input Data Sample Timing General Purpose Port Output Timing On-Chip Debugger Timing MASTER Mode Timing SLAVE Mode Timing Timing UART Timing Instruction Assembly Language Programming Introduction Assembly Language Syntax Instruction Notation Condition Codes Instruction Classes
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Instruction Summary Flags Register Opcode Maps Packaging Ordering Information Part Number Suffix Designations
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Encore!® Series Block Diagram Encore!® Series 20-Pin SSOP PDIP Packages Encore!® Series 28-Pin SOIC PDIP Packages Encore!® Series 20-Pin SSOP PDIP Packages Encore!® Series 28-Pin SOIC PDIP Packages Power-On Reset Operation) Voltage Brown-Out Reset Operation GPIO Port Block Diagram Interrupt Controller Block Diagram Timer Block Diagram UART Block Diagram UART Asynchronous Data Format without Parity UART Asynchronous Data Format with Parity UART Asynchronous MULTIPROCESSOR Mode Data Format UART Driver Enable Signal Timing (with STOP Parity) UART Receiver Interrupt Service Routine Flow Infrared Data Communication System Block Diagram Infrared Data Transmission Infrared Data Reception Configured Master Single Master, Single Slave System Configured Master Single Master, Multiple Slave System Configured Slave Timing When PHASE Timing When PHASE 7-Bit Addressed Slave Data Transfer Format 10-Bit Addressed Slave Data Transfer Format Receive Data Transfer Format 7-Bit Addressed Slave Receive Data Format 10-Bit Addressed Slave Analog-to-Digital Converter Block Diagram Flash Memory Arrangement On-Chip Debugger Block Diagram Interfacing On-Chip Debugger's with RS-232 Interface
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Figure Interfacing On-Chip Debugger's with RS-232 Interface Figure Data Format Figure Recommended 20MHz Crystal Oscillator Configuration Figure Connecting On-Chip Oscillator External Network Figure Typical Oscillator Frequency Function External Capacitance with 15KW Resistor Figure Versus System Clock Frequency Figure Versus System Clock Frequency Figure Port Input Sample Timing Figure GPIO Port Output Timing Figure On-Chip Debugger Timing Figure MASTER Mode Timing Figure SLAVE Mode Timing Figure Timing Figure UART Timing with Figure UART Timing without Figure Flags Register Figure Opcode Cell Description Figure First Opcode Figure Second Opcode after Figure 20-Pin Small Shrink Outline Package (SSOP) Figure 20-Pin Plastic Dual-Inline Package (PDIP) Figure 28-Pin Small Outline Integrated Circuit Package (SOIC) Figure 28-Pin Plastic Dual-Inline Package (PDIP)
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List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Encore!® Series Part Selection Guide Encore!® Series Package Options Signal Descriptions Characteristics Encore!® Series Program Memory Maps Information Area Register File Address Reset STOP Mode Recovery Characteristics Latency Reset Sources Resulting Reset Type STOP Mode Recovery Sources Resulting Action Port Availability Device Package Type Port Alternate Function Mapping GPIO Port Registers Sub-Registers Port GPIO Address Registers (PxADDR) Port Control Registers (PxCTL) Port Data Direction Sub-Registers Port Alternate Function Sub-Registers Port Output Control Sub-Registers Port High Drive Enable Sub-Registers Port STOP Mode Recovery Source Enable Sub-Registers Port Input Data Registers (PxIN) Port Pull-Up Enable Sub-Registers Port Output Data Register (PxOUT) Interrupt Vectors Order Priority Interrupt Request Register (IRQ0) Interrupt Request Register (IRQ2) Interrupt Request Register (IRQ1) IRQ0 Enable Priority Encoding IRQ0 Enable High Register (IRQ0ENH) IRQ1 Enable Priority Encoding IRQ0 Enable Register (IRQ0ENL) IRQ1 Enable Register (IRQ1ENL) IRQ2 Enable Priority Encoding IRQ1 Enable High Register (IRQ1ENH)
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
IRQ2 Enable Register (IRQ2ENL) IRQ2 Enable High Register (IRQ2ENH) Interrupt Edge Select Register (IRQES) Interrupt Control Register (IRQCTL) Timer High Byte Register (TxH) Timer Byte Register (TxL) Timer Reload High Byte Register (TxRH) Timer Reload Byte Register (TxRL) Timer High Byte Register (TxPWMH) Timer Byte Register (TxPWML) Timer Control Register (TxCTL0) Timer Control Register (TxCTL) Watch-Dog Timer Approximate Time-Out Delays Watch-Dog Timer Control Register (WDTCTL) Watch-Dog Timer Reload Upper Byte Register (WDTU) Watch-Dog Timer Reload High Byte Register (WDTH) Watch-Dog Timer Reload Byte Register (WDTL) UART Transmit Data Register (U0TXD) UART Receive Data Register (U0RXD) UART Status Register (U0STAT0) UART Status Register (U0STAT1) UART Control Register (U0CTL0) UART Control Register (U0CTL1) UART Address Compare Register (U0ADDR) UART Baud Rate High Byte Register (U0BRH) UART Baud Rate Byte Register (U0BRL) UART Baud Rates Clock Phase (PHASE) Clock Polarity (CLKPOL) Operation Data Register (SPIDATA) Control Register (SPICTL) Status Register (SPISTAT) Mode Register (SPIMODE) Diagnostic State Register (SPIDST) Baud Rate High Byte Register (SPIBRH) Baud Rate Byte Register (SPIBRL) Data Register (I2CDATA)
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 100. Table 101. Table 102. Table 103.
Status Register (I2CSTAT) Control Register (I2CCTL) Baud Rate High Byte Register (I2CBRH) Baud Rate Byte Register (I2CBRL) Diagnostic State Register (I2CDST) Diagnostic Control Register (I2CDIAG) Control Register (ADCCTL) Data High Byte Register (ADCD_H) Data Bits Register (ADCD_L) Flash Memory Configurations Flash Memory Sector Addresses Series Information Area Flash Control Register (FCTL) Flash Status Register (FSTAT) Page Select Register (FPS) Flash Sector Protect Register (FPROT) Flash Frequency High Byte Register (FFREQH) Flash Frequency Byte Register (FFREQL) Encore!® Series Memory Configurations Encore!® Series Information Area Page Select Register (RPS) Option Bits Program Memory Address 0000H Series Flash Devices Option Bits Program Memory Address 0000H Series Devices Options Bits Program Memory Address 0001H Baud-Rate Limits On-Chip Debugger Commands Control Register (OCDCTL) Status Register (OCDSTAT) Recommended Crystal Oscillator Specifications (20MHz Operation) Absolute Maximum Ratings Characteristics Characteristics Power-On Reset Voltage Brown-Out Electrical Characteristics Timing
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Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129.
Flash Memory Electrical Characteristics Timing Watch-Dog Timer Electrical Characteristics Timing Analog-to-Digital Converter Electrical Characteristics Timing GPIO Port Input Timing GPIO Port Output Timing On-Chip Debugger Timing MASTER Mode Timing SLAVE Mode Timing Timing UART Timing with UART Timing without Assembly Language Syntax Example Assembly Language Syntax Example Notational Shorthand Additional Symbols Condition Codes Arithmetic Instructions Manipulation Instructions Block Transfer Instructions Control Instructions Load Instructions Logical Instructions Program Control Instructions Rotate Shift Instructions Instruction Summary Opcode Abbreviations
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Manual Objectives
This Product Specification provides detailed operating information Encore!® Series devices within Encore!® Microcontroller (MCU) family products. Within this document, Encore!® Series referred collectively Encore!® Series unless specifically stated otherwise.
About This Manual
ZiLOG recommends that user read understand everything this manual before setting using product. However, recognize that there different styles learning. Therefore, have designed this Product Specification used either procedural manual reference guide important data.
Intended Audience
This document written ZiLOG customers experienced working with microcontrollers, integrated circuits, printed circuit assemblies.
Manual Conventions
following assumptions conventions adopted provide clarity ease use: Courier Typeface Commands, code lines fragments, bits, equations, hexadecimal addresses, various executable items distinguished from general text Courier typeface. Where font indicated, Index, name entity presented upper case.
Example: FLAGS[1] smrf.
Hexadecimal Values Hexadecimal values designated uppercase suffix appear Courier typeface.
Example: F8H.
Brackets square brackets, indicate register bus.
Example: register R1[7:0], 8-bit register, R1[7] most significant bit, R1[0] least significant bit.
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Braces curly braces, indicate single register created concatenating some combination smaller registers, buses, individual bits.
Example: 12-bit register address {0H, RP[7:4], R1[3:0]} composed 4-bit hexadecimal value (0H) 4-bit register values taken from Register Pointer (RP) Working Register most significant nibble (4-bit value) 12-bit register, R1[3:0] least significant nibble 12-bit register.
Parentheses parentheses, indicate indirect register address lookup.
Example: (R1) memory location referenced address contained Working Register
Parentheses/Bracket Combinations parentheses, indicate indirect register address lookup square brackets, indicate register bus.
Example: assume PC[15:0] contains value 1234h. (PC[15:0]) then refers contents memory location address 1234h.
Words Set, Reset Clear word implies that register condition contains logical words reset clear imply that register condition contains logical When either these terms followed number, word logical included; however, implied. Notation Bits Similar Registers field bits within register designated Register[n:n].
Example: ADDR[15:0] refers bits through Address.
Terms LSB, MSB, lsb, this document, terms MSB, when appearing upper case, mean least significant byte most significant byte, respectively. lowercase forms, msb, mean least significant most significant bit, respectively. Initial Uppercase Letters Initial uppercase letters designate settings conditions general text.
Example receiver forces line Low. Example Master generate STOP condition abort transfer.
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Uppercase Letters uppercase letters designates names states, modes, commands.
Example considered BUSY after Start condition. Example START command triggers processing initialization sequence. Example STOP mode.
Numbering Bits numbered from where indicates total number bits. example, bits register numbered from
Safeguards
important that users understand following safety terms, which defined here. Caution: Indicates procedure file become corrupted user does follow directions.
Trademarks
ZiLOG, eZ8, Encore! trademarks ZiLOG, Inc. U.S.A. other countries. other trademarks property their respective corporations.
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Introduction
Encore!® product family line ZiLOG microcontrollers based 8-bit CPU. Encore!® Series, hereafter referred collectively Encore!® Series, adds Flash memory ZiLOG's extensive line 8-bit microcontrollers. Flash in-circuit programming allows faster development time program changes field. Encore!® Series also includes devices that pin-and function-compatible with Flash products. devices provide lowcost alternative customers require reprogrammability Flash devices. upward-compatible with existing instructions. rich peripheral Encore!® makes suitable variety applications including motor control, security systems, home appliances, personal electronic devices sensors.
Features
20MHz core Flash optional ROM) with in-circuit programming capability (Flash only) register Optional 5-channel, 10-bit analog-to-digital converter (ADC) Full-duplex 9-bit UART with transceiver Driver Enable Control Serial peripheral interface (SPI) Infrared Data Association (IrDA)-compliant infrared encoder/decoders 16-bit timers with capture, compare, capability Watch-Dog Timer (WDT) with internal oscillator 11-19 pins depending upon package interrupts with configurable priority On-Chip Debugger Voltage Brown-out Protection (VBO) Power-On Reset (POR)
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Crystal oscillator with three power settings oscillator option 2.7-3.6V operating voltage with 5V-tolerant inputs 28-pin packages +70°C standard temperature -40° +105°C extended temperature operating ranges
Part Selection Guide
Table identifies basic features package styles available each device within Encore!® Series Flash product line.
Table Encore!® Series Part Selection Guide 16-bit Timers with Package Counts Inputs UARTs with IrDA
Part Number Z8X0822 Z8X0821 Z8X0812 Z8X0811 Z8X0422 Z8X0421 Z8X0412 Z8X0411
Flash/ROM (KB) (KB)
Flash: ROM:
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Block Diagram
Figure illustrates block diagram architecture Encore!® Series devices.
Crystal Oscillator
On-Chip Debugger POR/VBO Reset Controller
System Clock
Interrupt Controller
with Oscillator
Memory Busses Register
Timers
UART
Flash/ROM Controller
Controller
IrDA
Flash/ROM Memory
GPIO
Figure Encore!® Series Block Diagram
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Peripheral Overview
Features
eZ8, ZiLOG's latest 8-bit Central Processing Unit (CPU), meets continuing demand faster more code-efficient microcontrollers. executes superset original instruction set. features include:
Direct register-to-register architecture allows each register function accumulator, improving execution time decreasing required program memory Software stack allows much greater depth subroutine calls interrupts than hardware stacks Compatible with existing code Expanded internal Register File allows access instructions improve execution efficiency code developed using higher-level programming languages, including Pipelined instruction fetch execution instructions improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, instructions support 12-bit linear addressing Register File MIPS operation C-Compiler friendly clock cycles instruction
more information regarding CPU, refer User Manual available download www.zilog.com.
General Purpose
Encore!® Series features port pins (Ports A-C) general purpose (GPIO). number GPIO pins available function package. Each individually programmable.
Flash Controller
Flash Controller programs erases Flash memory.
10-Bit Analog-to-Digital Converter
optional Analog-to-Digital Converter (ADC) converts analog input signal 10bit binary number. accepts inputs from different analog input sources.
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UART
UART full-duplex capable handling asynchronous data transfers. UART supports 9-bit data modes selectable parity.
inter-integrated circuit (I2C®) controller makes Encore!® compatible with protocol. controller consists bidirectional lines, serial data (SDA) line serial clock (SCL) line.
Serial Peripheral Interface
serial peripheral interface (SPI) allows Encore!® exchange data between other peripheral devices such EEPROMs, converters ISDN devices. full-duplex, synchronous, character-oriented channel that supports four-wire interface.
Timers
16-bit reloadable timers used timing/counting events motor control operations. These timers provide 16-bit programmable reload counter operate One-Shot, Continuous, Gated, Capture, Compare, Capture Compare, modes.
Interrupt Controller
Encore!® Series products support interrupts. These interrupts consist internal peripheral interrupts general-purpose interrupt sources. interrupts have levels programmable interrupt priority.
Reset Controller
Encore!® Series products reset using RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
Encore!® Series products feature integrated On-Chip Debugger (OCD). provides rich debugging capabilities, such reading writing registers, programming Flash, setting breakpoints executing code. single-pin interface provides communication OCD.
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Signal Descriptions
Overview
Encore!® Series products available variety packages styles configurations. This chapter describes signals available configurations each package styles. information regarding physical package specifications, please refer chapter Packaging page 221.
Available Packages
Table identifies package styles that available each device within Encore!® Series product line.
Table Encore!® Series Package Options 20-pin SSOP PDIP 28-pin SOIC PDIP
Part Number Z8X0822 Z8X0821 Z8X0812 Z8X0811 Z8X0422 Z8X0421 Z8X0412 Z8X0411
10-bit
Flash: ROM:
Configurations
Figures through illustrate configurations packages available Encore!® Series. Refer Table description signals. Note: analog input alternate functions (ANAx) available Encore!® Series
devices.
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RESET XOUT T0IN T0OUT
T1IN ANA0 ANA1 VREF AVSS AVDD TXD0 RXD0 CTS0
Figure Encore!® Series 20-Pin SSOP PDIP Packages
T1IN RESET XOUT MISO MOSI T0IN T0OUT
ANA0 ANA1 ANA2 ANA3 ANA4 VREF AVSS AVDD T1OUT TXD0 RXD0 CTS0
Figure Encore!® Series 28-Pin SOIC PDIP Packages
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RESET XOUT T0IN T0OUT
T1IN Connect AVSS AVDD TXD0 RXD0 CTS0
Figure Encore!® Series 20-Pin SSOP PDIP Packages
T1IN RESET XOUT MISO MOSI T0IN T0OUT
Connect AVSS AVDD T1OUT TXD0 RXD0 CTS0
Figure Encore!® Series 28-Pin SOIC PDIP Packages
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Signal Descriptions
Table describes Encore!® Series signals. Refer section Configurations page determine signals available specific package styles.
Table Signal Descriptions Signal Mnemonic Description
General-Purpose Ports PA[7:0] PB[4:0] PC[5:0] Controller Serial Clock. This open-drain clocks data transfers accordance with standard protocol. This multiplexed with general-purpose pin. When general-purpose configured alternate function enable function, this open-drain. Serial Data. This open-drain transfers data between slave. This multiplexed with general-purpose pin. When general-purpose configured alternate function enable function, this open-drain. Port These pins used general-purpose I/O. Port These pins used general-purpose I/O. Port These pins used general-purpose I/O.
Controller
Slave Select. This signal output input. Encore!® master, this configured Slave Select output. Encore!® slave, this input slave select. multiplexed with general-purpose pin. Serial Clock. master supplies this pin. Encore!® master, this output. Encore!® slave, this input. multiplexed with general-purpose pin. Master Slave This signal data output from master device data input slave device. multiplexed with general-purpose pin. Master Slave Out. This data input master device data output from slave device. multiplexed with general-purpose pin.
MOSI
MISO
UART Controllers TXD0 RXD0 Transmit Data. This signal transmit outputs from UART IrDA. signals multiplexed with general-purpose pins. Receive Data. This signal receiver inputs UART IrDA. signals multiplexed with general-purpose pins.
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Table Signal Descriptions (Continued) Signal Mnemonic Description Clear Send. This signal control inputs UART. signals multiplexed with general-purpose pins. Driver Enable. This signal allows automatic control external RS-485 drivers. This signal approximately inverse (Transmit Empty) UART Status register. signal used ensure external RS-485 driver enabled when data transmitted UART.
CTS0
Timers T0OUT T1OUT T0IN T1IN Analog ANA[4:0] VREF Analog Input. These signals inputs analog-to-digital converter (ADC). analog inputs multiplexed with general-purpose pins. Analog-to-digital converter reference voltage input. output, VREF signal recommended reference voltage external devices. configured internal reference voltage generator, this should left unconnected capacitively coupled analog ground (AVSS). Timer Output 0-1. These signals output pins from timers. Timer Output signals multiplexed with general-purpose pins. Timer Input 0-1. These signals used capture, gating counter inputs. Timer Input signals multiplexed with general-purpose pins.
Oscillators External Crystal Input. This input crystal oscillator. crystal connected between XOUT form oscillator. addition, this used with external networks external clock drivers provide system clock system. External Crystal Output. This output crystal oscillator. crystal connected between form oscillator. When system clock referred this manual, refers frequency signal this pin. This must left unconnected when using crystal.
XOUT
On-Chip Debugger Debug. This control data input output from On-Chip Debugger. This open-drain. operation On-Chip Debugger, power pins (VDD AVDD) must supplied with power ground pins (VSS AVSS) must properly grounded. open-drain must have external pull-up resistor ensure proper operation.
Caution:
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Table Signal Descriptions (Continued) Signal Mnemonic Reset Description
RESET
Power Supply AVDD AVSS
RESET. Generates Reset when asserted (driven Low).
Digital Power Supply. Analog Power Supply. Must powered grounded VDD, even using analog features. Digital Ground. Analog Ground. Must grounded connected VSS, even using analog features.
Characteristics
Table provides detailed information characteristics each available Encore!® Series products. Data Table sorted alphabetically symbol mnemonic.
Table Characteristics Active Schmitt Reset Tri-State Internal Pull-up Trigger Direction Active High Output Pull-down Input Programmable Pull-up Programmable Pull-up Programmable Pull-up Pull-up
Symbol Mnemonic AVDD AVSS PA[7:0] PB[4:0] PC[5:0] RESET VREF
Direction Analog
Open Drain Output Yes, Programmable Yes, Programmable Yes, Programmable
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Table Characteristics (Continued) Active Schmitt Reset Tri-State Internal Pull-up Trigger Direction Active High Output Pull-down Input
Symbol Mnemonic XOUT
Direction
Open Drain Output
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Address Space
Overview
access three distinct address spaces:
Register File contains addresses general-purpose registers CPU, peripheral, general-purpose port control registers. Program Memory contains addresses memory locations having executable code and/or data. Data Memory contains addresses memory locations that hold data only.
These three address spaces covered briefly following subsections. more detailed information regarding address space, refer User Manual available download www.zilog.com.
Register File
Register File address space Encore!® (4096 bytes). Register File composed sections-control registers general-purpose registers. When instructions executed, registers read from when defined sources written when defined destinations. architecture allows general-purpose registers function accumulators, address pointers, index registers, stack areas, scratch memory. upper bytes Register File address space reserved control CPU, on-chip peripherals, ports. These registers located addresses from F00H FFFH. Some addresses within 256-byte control register section reserved (unavailable). Reading from reserved Register File addresses returns undefined value. Writing reserved Register File addresses recommended produce unpredictable results. on-chip always begins address 000H Register File address space. Encore!® Series contain on-chip RAM. Reading from Register File addresses outside available addresses (and within control register address space) returns undefined value. Writing these Register File addresses produces effect.
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Address Space
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Program Memory
supports 64KB Program Memory address space. Encore!® Series contain on-chip Flash/Read-Only Memory (ROM) Program Memory address space, depending upon device. Reading from Program Memory addresses outside available Flash/ROM addresses returns FFH. Writing unimplemented Program Memory addresses produces effect. Table describes Program Memory Maps Encore!® Series devices.
Table Encore!® Series Program Memory Maps Program Memory Address (Hex) Z8X082x Z8X081x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-1FFF Z8X042x Z8X041x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-0FFF Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
Table page list interrupt vectors.
Data Memory
Encore!® Series does CPU's 64KB Data Memory address space.
Information Area
Table describes Encore!® Series Information Area. This byte Information Area accessed setting Page Select Register When access enabled, Information Area mapped into Program Memory overlays bytes
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addresses FE00H FFFFH. When Information Area access enabled, reads from these Program Memory addresses return Information Area data rather than Program Memory data. Access Information Area read-only.
Table Information Area Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified filled with zeros Reserved
FE54H-FFFFH
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Register File Address
Table provides address Register File Encore!® Series products. devices package styles Series support ADC, SPI, GPIO Ports. Consider registers unimplemented peripherals Reserved.
Table Register File Address Address (Hex) Register Description Mnemonic T0RH T0RL T0PWMH T0PWML T0CTL0 T0CTL1 T1RH T1RL T1PWMH T1PWML T1CTL0 T1CTL1 U0TXD U0RXD U0STAT0 U0CTL0 U0CTL1 U0STAT1 Reset (Hex) 0000011Xb Page General Purpose 000-3FF General-Purpose Register File 400-EFF Reserved Timer Timer F10-F3F UART XX=Undefined Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control Reserved UART0 Transmit Data UART0 Receive Data UART0 Status UART0 Control UART0 Control UART0 Status
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Register File Address
Encore!® Series
Table Register File Address (Continued) Address (Hex) F48-F4F F57-F5F Register Description UART0 Address Compare Register UART0 Baud Rate High Byte UART0 Baud Rate Byte Reserved Data Status Control Baud Rate High Byte Baud Rate Byte Diagnostic State Diagnostic Control Reserved Mnemonic U0ADDR U0BRH U0BRL I2CDATA I2CSTAT I2CCTL I2CBRH I2CBRL I2CDST I2CDIAG Reset (Hex) XX000000b Page
Serial Peripheral Interface (SPI) Unavailable 20-Pin Package Devices Data SPIDATA Control SPICTL Status SPISTAT Mode SPIMODE Diagnostic State SPIDST Reserved Baud Rate High Byte SPIBRH Baud Rate Byte SPIBRL F68-F6F Reserved Analog-to-Digital Converter (ADC) Control Reserved Data High Byte Data Bits F74-FBF Reserved Interrupt Controller Interrupt Request IRQ0 Enable High IRQ0 Enable Interrupt Request IRQ1 Enable High IRQ1 Enable Interrupt Request IRQ2 Enable High IRQ2 Enable FC9-FCC Reserved XX=Undefined ADCCTL ADCD_H ADCD_L IRQ0 IRQ0ENH IRQ0ENL IRQ1 IRQ1ENH IRQ1ENL IRQ2 IRQ2ENH IRQ2ENL
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Register File Address
Encore!® Series
Table Register File Address (Continued) Address (Hex) GPIO Port GPIO Port GPIO Port FDC-FEF Register Description Interrupt Edge Select Reserved Interrupt Control Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Reserved Mnemonic IRQES IRQCTL PAADDR PACTL PAIN PAOUT PBADDR PBCTL PBIN PBOUT PCADDR PCCTL PCIN PCOUT WDTCTL WDTU WDTH WDTL FCTL FSTAT FPROT FFREQH FFREQL Reset (Hex) XXX00000b Page
Watch-Dog Timer (WDT) Watch-Dog Timer Control Watch-Dog Timer Reload Upper Byte Watch-Dog Timer Reload High Byte Watch-Dog Timer Reload Byte FF4-FF7 Reserved Flash Memory Controller Flash Control Flash Status Page Select enabled) Flash Sector Protect Flash Programming Frequency High Byte Flash Programming Frequency Byte Read-Only Memory Reserved Page Select FFA-FFB Reserved XX=Undefined
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Register File Address
Encore!® Series
Table Register File Address (Continued) Address (Hex) XX=Undefined Register Description Flags Register Pointer Stack Pointer High Byte Stack Pointer Byte Mnemonic Reset (Hex) Page Refer User Manual
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Register File Address
Encore!® Series
Control Register Summary
Timer High Byte (F00H Read/Write)
Timer current count value [15:8]
Timer Control T0CTL1 (F07H Read/Write)
Timer Mode One-Shot mode Continuous mode Counter mode mode Capture mode Compare mode Gated mode Capture/Compare mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
Timer Byte (F01H Read/Write)
Timer current count value [7:0]
Timer Reload High Byte T0RH (F02H Read/Write)
Timer reload value [15:8]
Timer Reload Byte T0RL (F03H Read/Write)
Timer reload value [7:0]
Timer High Byte (F08H Read/Write) Timer High Byte T0PWMH (F04H Read/Write)
Timer value [15:8] Timer current count value [15:8]
Timer Byte (F09H Read/Write) Timer Control T0CTL0 (F06H Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved Timer current count value [7:0]
Timer Reload High Byte T1RH (F0AH Read/Write)
Timer reload value [15:8]
Timer Reload Byte T1RL (F0BH Read/Write)
Timer reload value [7:0]
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Control Register Summary
Encore!® Series
Timer High Byte T1PWMH (F0CH Read/Write)
Timer value [15:8]
UART0 Transmit Data U0TXD (F40H Write Only)
UART0 transmitter data byte [7:0]
Timer Byte T1PWML (F0DH Read/Write)
Timer value [7:0]
UART0 Receive Data U0RXD (F40H Read Only)
UART0 receiver data byte [7:0]
Timer Control T1CTL0 (F0EH Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved
UART0 Status U0STAT0 (F41H Read Only)
signal Returns level signal Transmitter Empty Data currently transmitting Transmission complete Transmitter Data Register Empty Transmit Data Register full Transmit Data register empty Break Detect break occurred break occurred Framing Error framing error occurred framing occurred Overrun Error overrrun error occurred overrun error occurred Parity Error parity error occurred parity error occurred Receive Data Available Receive Data Register empty byte available Receive Data Register
Timer Control T1CTL1 (F0FH Read/Write)
Timer Mode One-Shot mode Continuous mode Counter mode mode Capture mode Compare mode Gated mode Capture/Compare mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
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Control Register Summary
Encore!® Series
UART0 Control U0CTL0 (F42H Read/Write)
Loop Back Enable Normal operation Transmit data looped back receiver STOP Select Transmitter sends STOP Transmitter sends STOP bits Send Break break sent Output transmitter zero Parity Select Even parity parity Parity Enable Parity disabled Parity enabled Enable signal effect transmitter UART recognizes signal transmit enable control signal Receive Enable Receiver disabled Receiver enabled Transmit Enable Transmitter disabled Transmitter enabled
UART0 Control U0CTL1 (F43H Read/Write)
Infrared Encoder/Decoder Enable Infrared endec disabled Infrared endec enabled Received Data Interrupt Enable Received data errors generate interrupt requests Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer UART chapter operation Driver Enable Polarity signal active High signal active Multiprocessor Transmit Send multiprocessor Send multiprocessor Multiprocessor Mode Multiprocessor Mode below Multiprocessor (9-bit) Enable Multiprocessor mode disabled Multiprocessor mode enabled Multiprocessor Mode with Multiprocess Mode Interrupt received bytes Interrupt only address bytes Interrupt address match following data Interrupt data following address match
UART0 Status U0STAT1 (F44H- Read Only)
Mulitprocessor Receive Returns value last multiprocessor Frame Current byte start frame Current byte start frame Reserved
UART0 Address Compare U0ADDR (F45H Read/Write)
UART0 Address Compare [7:0]
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Control Register Summary
Encore!® Series
UART0 Baud Rate Generator High Byte U0BRH (F46H Read/Write)
UART0 Baud Rate divisor [15:8]
Control I2CCTL (F52H Read/Write)
Signal Filter Enable Digital filtering disabled Low-pass digital filters enabled input signals Flush Data effect Clears Data register Send send Send after next byte received from slave Enable TDRE Interrupts generate interrupt when Data register empty Generate interrupt when Transmit Data register empty Baud Rate Generator Interrupt Request Interrupts behave control generates interrupt when counts down zero Send STOP Condition issue STOP condition after data transmission complete Issue STOP condition after data transmission complete Send Start Condition send Start Condition Send Start Condition Enable disabled enabled
UART0 Baud Rate Generator Byte U0BRL (F47H Read/Write)
UART0 Baud Rate divisor [7:0]
Data I2CDATA (F50H Read/Write)
data [7:0]
Status I2CSTAT (F51H Read Only)
NACK Interrupt action required service START/STOP after Data Shift State Data being transferred Data being transferred Transmit Address State Address being transferred Address being transferred Read Write operation Read operation 10-Bit Address 7-bit address being transmitted 10-bit address being transmitted Acknowledge Acknowledge transmitted/received last byte, Acknowledge transmitted/received Receive Data Register Full received data Data register contains received data Transmit Data Register Empty Data register full Data register empty
Baud Rate Generator High Byte I2CBRH (F53H Read/Write)
Baud Rate divisor [15:8]
Baud Rate Generator Byte I2CBRL (F54H Read/Write)
Baud Rate divisor [7:0]
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Control Register Summary
Encore!® Series
Data SPIDATA (F60H Read/Write)
Data [7:0]
Status SPISTAT (F62H Read Only)
Slave Select Slave, asserted Slave, asserted Transmit Status data transmission progress Data transmission progress Reserved Slave Mode Transaction Abort slave mode transaction abort detected Slave mode transaction abort detected Collision multi-master collision detected Multi-master collision detected Overrun overrun error detected Overrun error detected Interrupt Request interrupt request pending interrupt request pending
Control SPICTL (F61H Read/Write)
Enable disabled enabled Master Mode Enabled configured Slave mode configured Master mode Wire-OR (open-drain) Mode Enabled signals configured open-drain signals (SCK, MISO, MOSI) configured open-drain Clock Polarity idles idles High Phase Select Sets phase relationship data clock. Timer Interrupt Request timer function disabled time-out interrupt enabled Start Interrupt Request effect Generate interrupt request Interrupt Request Enable interrupt requests disabled interrupt requests enabled
Mode SPIMODE (F63H Read/Write)
Slave Select Value Master SPIMODE[1] driven driven High Slave Select configured input configured output (Master mode only) Number Data Bits Character bits bits bits bits bits bits Diagnostic Mode Control Reading from SPIBRH, SPIBRL returns reload values Reading from SPIBRH, SPIBRL returns current count value Reserved
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Control Register Summary
Encore!® Series
Diagnostic State SPIDST (F64H Read Only)
State Transmit Clock Enable Internal transmit clock enable signal deasserted Internal transmit clock enable signal asserted Shift Clock Enable Internal shift clock enable signal deasserted Internal shift clock enable signal asserted
Data High Byte ADCD_H (F72H Read Only)
Data [9:2]
Data Bits ADCD_L (F73H Read Only)
Reserved Data [1:0]
Baud Rate Generator High Byte SPIBRH (F66H Read/Write)
Baud Rate divisor [15:8]
Interrupt Request IRQ0 (FC0H Read/Write)
Interrupt Request Interrupt Request Interrupt Request
Baud Rate Generator Byte SPIBRL (F67H Read/Write)
Baud Rate divisor [7:0]
UART Transmitter Interrupt Request UART Receiver Interrupt Request Timer Interrupt Request Timer Interrupt Request
Control ADCCTL (F70H Read/Write)
Analog Input Select 0000 ANA0 0001 ANA1 0010 ANA2 0011 ANA3 0100 ANA4 0101 through 21111 Reserved Continuous Mode Select Single-shot conversion Continuous conversion External VREF select Internal voltage reference selected External voltage reference selected Reserved Conversion Enable Conversion complete Begin conversion
Reserved above peripherals: Peripheral pending Peripheral awaiting service
IRQ0 Enable High IRQ0ENH (FC1H Read/Write)
Enable Enable High Enable High UART Transmitter Enable High UART Receiver Enable High Timer Enable High Timer Enable High Reserved
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Control Register Summary
Encore!® Series
IRQ0 Enable IRQ0ENL (FC2H Read/Write)
Enable Enable Enable UART Transmitter Enable UART Receiver Enable Timer Enable Timer Enable Reserved
IRQ2 Enable High IRQ2ENH (FC7H Read/Write)
Port Enable High Reserved
IRQ2 Enable IRQ2ENL (FC8H Read/Write)
Port Enable Reserved
Interrupt Request IRQ1 (FC3H Read/Write)
Port Interrupt Request from corresponding [7:0] pending from corresponding [7:0] awaiting service
Interrupt Control IRQCTL (FCFH Read/Write)
Reserved Interrupt Request Enable Interrupts disabled Interrupts enabled
IRQ1 Enable High IRQ1ENH (FC4H Read/Write)
Port Enable High
Port Address PAADDR (FD0H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable Pull-up enable 07H-FFH function
IRQ1 Enable IRQ1ENL (FC5H Read/Write)
Port Enable
Interrupt Request IRQ2 (FC6H Read/Write)
Port Interrupt Request from corresponding [3:0] pending from corresponding [3:0] awaiting service Reserved
Port Control PACTL (FD1H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
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Control Register Summary
Encore!® Series
Port Input Data PAIN (FD2H Read Only)
Port Input Data [7:0]
Port Address PCADDR (FD8H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable Pull-up enable 07H-FFH function
Port Output Data PAOUT (FD3H Read/Write)
Port Output Data [7:0]
Port Address PBADDR (FD4H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable Pull-up enable 07H-FFH function
Port Control PCCTL (FD9H Read/Write)
Port Control [5:0] Provides Access Port Sub-Registers Reserved
Port Input Data PCIN (FDAH Read Only)
Port Input Data [5:0]
Port Control PBCTL (FD5H Read/Write)
Port Control [4:0] Provides Access Port Sub-Registers Reserved
Reserved
Port Output Data PCOUT (FDBH Read/Write)
Port Output Data [5:0]
Port Input Data PBIN (FD6H Read Only)
Port Input Data [4:0] Reserved
Reserved
Port Output Data PBOUT (FD7H Read/Write)
Port Output Data [4:0] Reserved
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Control Register Summary
Encore!® Series
Watch-Dog Timer Control WDTCTL (FF0H Read Only)
configuration indicator Reserved Reset generated RESET Reset generated RESET timeout occurred timeout occurred STOP occurred occurred occurred occurred
Watch-Dog Timer Reload Upper Byte WDTU (FF1H Read/Write)
reload value [23:16]
Watch-Dog Timer Reload Middle Byte WDTH (FF2H Read/Write)
reload value [15:8]
Watch-Dog Timer Reload Byte WDTL (FF3H Read/Write)
reload value [7:0]
Flash Control FCTL (FF8H Write Only)
Flash Command First unlock command Second unlock command Page erase command Mass erase command Flash Sector Protect select
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Control Register Summary
Encore!® Series
Flash Status FSTAT (FF8H Read Only)
Flash Controller Status 00_0000 Flash controller locked 00_0001 First unlock received 00_0010 Second unlock received 00_0011 Flash controller unlocked 00_0100 Flash Sector Protect register selected 00_1xxx Programming progress 01_0xxx Page erase progress 10_0xxx Mass erase progress Reserved
Page Select (FF9H Read/Write)
Page Select [6:0] Identifies Flash memory page Page Erase operation. Information Area Enable
Flash Sector Protect FPROT (FF9H Read/Write 1's)
Flash Sector Protect [7:0] Sector programmed erased from user code Sector protected cannot programmed erased from user code
Flash Frequency High Byte FFREQH (FFAH Read/Write)
Flash Frequency value [15:8]
Flash Frequency Byte FFREQL (FFBH Read/Write)
Flash Frequency value [7:0]
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Control Register Summary
Encore!® Series
Flags FLAGS (FFCH Read/Write)
User Flag User Flag Half Carry Decimal Adjust Overflow Flag Sign Flag Zero Flag Carry Flag
Register Pointer (FFDH- Read/Write)
Working Register Page Address [11:8] Working Register Group Address [7:4]
Stack Pointer High Byte (FFEH Read/Write)
Stack Pointer [15:8]
Stack Pointer Byte (FFFH Read/Write)
Stack Pointer [7:0]
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Control Register Summary
Encore!® Series
Reset STOP Mode Recovery
Overview
Reset Controller within Encore!® Series controls Reset STOP Mode Recovery operation. typical operation, following events cause Reset occur:
Power-On Reset (POR) Voltage Brown-Out (VBO) Watch-Dog Timer time-out (when configured through WDT_RES Option initiate Reset) External RESET assertion On-Chip Debugger initiated Reset (OCDCTL[0]
When Encore!® Series device STOP mode, STOP Mode Recovery initiated following events:
Reset Types
Watch-Dog Timer time-out GPIO Port input transition enabled STOP Mode Recovery source driven
Encore!® Series provides types reset operation (System Reset STOP Mode Recovery). type reset function both current operating mode Encore!® Series device source Reset. Table lists types Reset their operating characteristics.
Table Reset STOP Mode Recovery Characteristics Latency Reset Characteristics Latency Reset Type System Reset STOP Mode Recovery Control Registers Reset applicable) Unaffected, except WDT_CTL register Reset Latency (Delay) Reset Reset Oscillator cycles System Clock cycles Oscillator cycles System Clock cycles
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Reset STOP Mode Recovery
Encore!® Series
System Reset
During System Reset, Encore!® Series device held Reset cycles Watch-Dog Timer oscillator followed cycles system clock. beginning Reset, GPIO pins configured inputs. GPIO programmable pull-ups disabled. During Reset, on-chip peripherals idle; however, on-chip crystal oscillator Watch-Dog Timer oscillator continue run. system clock begins operating following Watch-Dog Timer oscillator cycle count. on-chip peripherals remain idle through cycles system clock. Upon Reset, control registers within Register File that have defined Reset value loaded with their reset values. Other control registers (including Stack Pointer, Register Pointer, Flags) general-purpose undefined following Reset. fetches Reset vector Program Memory addresses 0002H 0003H loads that value into Program Counter. Program execution begins Reset vector address.
Reset Sources
Table lists reset sources function operating mode. text following provides more detailed information individual Reset sources. Please note that PowerOn Reset Voltage Brown-Out event always priority over other possible reset sources insure full system reset occurs.
Table Reset Sources Resulting Reset Type Operating Mode Normal HALT modes Reset Source Reset Type
Power-On Reset Voltage Brown-Out System Reset Watch-Dog Timer time-out when configured Reset RESET assertion On-Chip Debugger initiated Reset (OCDCTL[0] System Reset System Reset System Reset except On-Chip Debugger unaffected reset
STOP mode
Power-On Reset Voltage Brown-Out System Reset RESET assertion driven System Reset System Reset
Power-On Reset
Each device Encore!® Series contains internal Power-On Reset (POR) circuit. circuit monitors supply voltage holds device Reset state
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Reset STOP Mode Recovery
Encore!® Series
until supply voltage reaches safe operating level. After supply voltage exceeds voltage threshold (VPOR), Counter enabled counts cycles Watch-Dog Timer oscillator. After counter times out, XTAL Counter enabled count total system clock pulses. device held Reset state until both Counter XTAL counter have timed out. After Encore!® Series device exits Power-On Reset state, fetches Reset vector. Following Power-On Reset, status Watch-Dog Timer Control (WDTCTL) register Figure illustrates Power-On Reset operation. Refer Electrical Characteristics chapter threshold voltage (VPOR).
3.3V VPOR VVBO
0.0V
Program Execution
Clock
Primary Oscillator Oscillator Start-up
Internal RESET signal
Scale
Counter Delay
XTAL Counter Delay
Figure Power-On Reset Operation)
Voltage Brown-Out Reset
devices Encore!® Series provide Voltage Brown-Out (VBO) protection. circuit senses when supply voltage drops unsafe level (below threshold voltage) forces device into Reset state. While supply voltage remains below Power-On Reset voltage threshold (VPOR), block holds device Reset state.
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Reset STOP Mode Recovery
Encore!® Series
After supply voltage again exceeds Power-On Reset voltage threshold, device progresses through full System Reset sequence, described Power-On Reset section. Following Power-On Reset, status Watch-Dog Timer Control (WDTCTL) register Figure illustrates Voltage Brown-Out operation. Refer Electrical Characteristics chapter threshold voltages (VVBO VPOR). Voltage Brown-Out circuit either enabled disabled during STOP mode. Operation during STOP mode VBO_AO Option Bit. Refer Option Bits chapter information configuring VBO_AO.
3.3V VPOR VVBO Program Execution Voltage Brownout Program Execution
3.3V
Clock
Primary Oscillator
Internal RESET signal
Counter Delay
XTAL Counter Delay
Figure Voltage Brown-Out Reset Operation
Watch-Dog Timer Reset
device normal HALT mode, Watch-Dog Timer initiate System Reset time-out WDT_RES Option This default (unprogrammed) setting WDT_RES Option Bit. status Control register signify that reset initiated Watch-Dog Timer.
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Reset STOP Mode Recovery
Encore!® Series
External Reset
RESET contains Schmitt-triggered input, internal pull-up, analog filter digital filter reject noise. After RESET asserted least system clock cycles, device progresses through System Reset sequence. While RESET input asserted Low, Encore!® Series device continues held Reset state. RESET held beyond System Reset time-out, device exits Reset state immediately following RESET deassertion. Following System Reset initiated external RESET pin, status Watch-Dog Timer Control (WDTCTL) register
On-Chip Debugger Initiated Reset
Power-On Reset initiated using On-Chip Debugger setting Control register. On-Chip Debugger block reset rest chip goes through normal system reset. automatically clears during system reset. Following system reset Control register set.
STOP Mode Recovery
STOP mode entered execution STOP instruction CPU. Refer Low-Power Modes chapter detailed STOP mode information. During STOP Mode Recovery, device held reset cycles Watch-Dog Timer oscillator followed cycles system clock. STOP Mode Recovery only affects contents Watch-Dog Timer Control register.TOP Mode recovery does affect other values Register File, including Stack Pointer, Register Pointer, Flags, peripheral control registers, general-purpose RAM. fetches Reset vector Program Memory addresses 0002H 0003H loads that value into Program Counter. Program execution begins Reset vector address. Following STOP Mode Recovery, STOP Watch-Dog Timer Control Register Table lists STOP Mode Recovery sources resulting actions. text following provides more detailed information each STOP Mode Recovery sources.
Table STOP Mode Recovery Sources Resulting Action Operating Mode STOP mode STOP Mode Recovery Source Watch-Dog Timer time-out when configured Reset Watch-Dog Timer time-out when configured interrupt Data transition GPIO Port enabled STOP Mode Recovery source Action STOP Mode Recovery STOP Mode Recovery followed interrupt interrupts enabled) STOP Mode Recovery
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Reset STOP Mode Recovery
Encore!® Series
STOP Mode Recovery Using Watch-Dog Timer Time-Out
Watch-Dog Timer times during STOP mode, device undergoes STOP Mode Recovery sequence. Watch-Dog Timer Control register, STOP bits Watch-Dog Timer configured generate interrupt upon timeout Encore!® Series device configured respond interrupts, services Watch-Dog Timer interrupt request following normal STOP Mode Recovery sequence.
STOP Mode Recovery Using GPIO Port Transition
Each GPIO Port pins configured STOP Mode Recovery input source. GPIO enabled STOP Mode Recover source, change input value (from High from High) initiates STOP Mode Recovery. GPIO STOP Mode Recovery signals filtered reject pulses less than 10ns (typical) duration. Watch-Dog Timer Control register, STOP Caution: STOP mode, GPIO Port Input Data registers (PxIN) disabled. Port Input Data registers record Port transition only signal stays Port through STOP Mode Recovery delay. Thus, short pulses Port initiate STOP Mode Recovery without being written Port Input Data register without initiating interrupt enabled that pin).
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Reset STOP Mode Recovery
Encore!® Series
Low-Power Modes
Overview
Encore!® Series products contain power-saving features. highest level power reduction provided STOP mode. next level power reduction provided HALT mode.
STOP Mode
Execution CPU's STOP instruction places device into STOP mode. STOP mode, operating characteristics are:
Primary crystal oscillator stopped; driven High XOUT driven Low. System clock stopped stopped Program counter (PC) stops incrementing enabled operation STOP Mode, Watch-Dog Timer internal oscillator continue operate enabled operation STOP mode through associated Option Bit, Voltagebrown protection circuit continues operate other on-chip peripherals idle
minimize current STOP mode, Watch-Dog Timer must disabled GPIO pins that configured digital inputs must driven supply rails (VCC GND). device brought STOP mode using STOP Mode Recovery. more information STOP Mode Recovery refer Reset STOP Mode Recovery chapter page Caution: STOP Mode must used when driving Z8F082x family devices with external clock driver source.
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Low-Power Modes
Encore!® Series
HALT Mode
Execution CPU's HALT instruction places device into HALT mode. HALT mode, operating characteristics are:
Primary crystal oscillator enabled continues operate System clock enabled continues operate stopped Program counter (PC) stops incrementing Watch-Dog Timer's internal oscillator continues operate enabled, Watch-Dog Timer continues operate other on-chip peripherals continue operate
brought HALT mode following operations: Interrupt Watch-Dog Timer time-out (interrupt reset) Power-on reset Voltage-brown reset External RESET assertion
minimize current HALT mode, GPIO pins which configured inputs must driven supply rails (VCC GND).
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Low-Power Modes
Encore!® Series
General-Purpose
Overview
Encore!® Series products support maximum port pins (Ports A-C) general-purpose input/output (GPI/O) operations. Each port contains control data registers. GPIO control registers used determine data direction, open-drain, output drive current, programmable pull-ups, STOP Mode Recovery functionality, alternate functions. Each port individually programmable.
GPIO Port Availability Device
Table lists port pins available with each device package type.
Table Port Availability Device Package Type Devices Z8X0821, Z8X0811, Z8X0421, Z8X0411 Z8X0822, Z8X0812, Z8X0422, Z8X0412 Package 20-pin 28-pin Port [7:0] [7:0] Port [1:0] [4:0] Port [5:0]
Architecture
Figure illustrates simplified block diagram GPIO port pin. this figure, ability accommodate alternate functions, variable port current drive strength, programmable pull-up illustrated.
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General-Purpose
Encore!® Series
Port Input Data Register
Schmitt Trigger
System Clock Port Output Control Port Output Data Register DATA System Clock Port
Port Data Direction
Figure GPIO Port Block Diagram
GPIO Alternate Functions
Many GPIO port pins used both general-purpose provide access on-chip peripheral functions such timers serial communication devices. Port Alternate Function sub-registers configure these pins either general-purpose alternate function operation. When configured alternate function, control port direction (input/output) passed from Port Data Direction registers alternate function assigned this pin. Table lists alternate functions associated with each port pin.
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General-Purpose
Encore!® Series
Table Port Alternate Function Mapping Port Port Port Port Mnemonic T0IN T0OUT CTS0 Alternate Function Description Timer Input Timer Output UART Driver Enable UART Clear Send
RXD0 IRRX0 UART IrDA Receive Data TXD0 IRTX0 ANA0 ANA1 ANA2 ANA3 ANA4 T1IN T1OUT MOSI MISO UART IrDA Transmit Data Clock (automatically open-drain) Data (automatically open-drain) Analog Input Analog Input Analog Input Analog Input Analog Input Timer Input Timer Output Slave Select Serial Clock Master Slave Master Slave
GPIO Interrupts
Many GPIO port pins used interrupt sources. Some port pins configured generate interrupt request either rising edge falling edge input signal. Other port interrupts generate interrupt when edge occurs (both rising falling). Refer Interrupt Controller chapter more information interrupts using GPIO pins.
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General-Purpose
Encore!® Series
GPIO Control Register Definitions
Four registers each Port provide access GPIO control, input data, output data. Table lists these Port registers. Port Address Control registers together provide access sub-registers Port configuration control.
Table GPIO Port Registers Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic PxDD PxAF PxOC PxHDE PxSMRE PxPUE Port Register Name Port Address Register (Selects sub-registers) Port Control Register (Provides access sub-registers) Port Input Data Register Port Output Data Register Port Register Name Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable Pull-up Enable
Port Address Registers
Port Address registers select GPIO Port functionality accessible through Port Control registers. Port Address Control registers combine provide access GPIO Port control (Table 13).
Table Port GPIO Address Registers (PxADDR)
BITS FIELD RESET ADDR
PADDR[7:0] FD0H, FD4H, FD8H
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Encore!® Series
PADDR[7:0]-Port Address Port Address selects sub-registers accessible through Port Control register.
PADDR[7:0] 07H-FFH Port Control sub-register accessible using Port Control Registers function. Provides some protection against accidental Port reconfiguration. Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable. Pull-up Enable function.
Port Control Registers
Port Control registers GPIO port operation. value corresponding Port Address register determines control sub-registers accessible using Port Control register (Table 14).
Table Port Control Registers (PxCTL)
BITS FIELD RESET ADDR
PCTL
FD1H, FD5H, FD9H
PCTL[7:0]-Port Control Port Control register provides access sub-registers that configure GPIO Port operation.
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Encore!® Series
Port Data Direction Sub-Registers Port Data Direction sub-register accessed through Port Control register writing Port Address register (Table 15).
Table Port Data Direction Sub-Registers
BITS FIELD RESET ADDR
Port Address Register, accessible through Port Control Register
DD[7:0]-Data Direction These bits control direction associated port pin. Port Alternate Function operation overrides Data Direction register setting. Output. Data Port Output Data register driven onto port pin. Input. port sampled value written into Port Input Data Register. output driver tri-stated. Port Alternate Function Sub-Registers Port Alternate Function sub-register (Table accessed through Port Control register writing Port Address register. Port Alternate Function sub-registers select alternate functions selected pins. Refer GPIO Alternate Functions section determine alternate function associated with each port pin. Caution: enable alternate function GPIO port pins which have associated alternate function. Failure follow this guideline result unpredictable operation.
Table Port Alternate Function Sub-Registers
BITS FIELD RESET ADDR
Port Address Register, accessible through Port Control Register
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Encore!® Series
AF[7:0]-Port Alternate Function enabled port NORMAL mode Port Data Direction sub-register determines direction pin. alternate function selected. Port operation controlled alternate function. Port Output Control Sub-Registers Port Output Control sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port Output Control sub-registers configures specified port pins opendrain operation. These sub-registers affect pins directly and, result, alternate functions also affected.
Table Port Output Control Sub-Registers
BITS FIELD RESET ADDR
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
Port Address Register, accessible through Port Control Register
POC[7:0]-Port Output Control These bits function independently alternate function always disable drains drains enabled output mode (unless overridden alternate function). drain associated disabled (open-drain mode).
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Encore!® Series
Port High Drive Enable Sub-Registers Port High Drive Enable sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port High Drive Enable sub-registers configures specified port pins high current output drive operation. Port High Drive Enable sub-register affects pins directly and, result, alternate functions also affected.
Table Port High Drive Enable Sub-Registers
BITS FIELD RESET ADDR
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
Port Address Register, accessible through Port Control Register
PHDE[7:0]-Port High Drive Enabled Port configured standard output current drive. Port configured high output current drive. Port STOP Mode Recovery Source Enable Sub-Registers Port STOP Mode Recovery Source Enable sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port STOP Mode Recovery Source Enable sub-registers configures specified Port pins STOP Mode Recovery source. During STOP Mode, logic transition Port enabled STOP Mode Recovery source initiates STOP Mode Recovery.
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General-Purpose
Encore!® Series
Table Port STOP Mode Recovery Source Enable Sub-Registers
BITS FIELD RESET ADDR
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
Port Address Register, accessible through Port Control Register
PSMRE[7:0]-Port STOP Mode Recovery Source Enabled Port configured STOP Mode Recovery source. Transitions this during STOP mode initiate STOP Mode Recovery. Port configured STOP Mode Recovery source. logic transition this during STOP mode initiates STOP Mode Recovery. Port Pull-up Enable Sub-Registers Port Pull-up Enable sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port Pull-up Enable sub-registers enables weak internal resistive pull-up specified Port pins.
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Table Port Pull-Up Enable Sub-Registers
BITS FIELD RESET ADDR
PPUE7
PPUE6
PPUE5
PPUE4
PPUE3
PPUE2
PPUE1
PPUE0
Port Address Register, accessible through Port Control Register
PPUE[7:0]-Port Pull-up Enabled weak pull-up Port disabled. weak pull-up Port enabled.
Port Input Data Registers
Reading from Port Input Data registers (Table returns sampled values from corresponding port pins. Port Input Data registers Read-only.
Table Port Input Data Registers (PxIN)
BITS FIELD RESET ADDR
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
FD2H, FD6H, FDAH
PIN[7:0]-Port Input Data Sampled data from corresponding port input. Input data logical (Low). Input data logical (High).
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Port Output Data Register
Port Output Data register (Table controls output data pins.
Table Port Output Data Register (PxOUT)
BITS FIELD RESET ADDR
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
FD3H, FD7H, FDBH
POUT[7:0]-Port Output Data These bits contain data driven port pins. values only driven corresponding configured output configured alternate function operation. Drive logical (Low). Drive logical (High). High value driven drain been disabled setting corresponding Port Output Control register
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Encore!® Series
Interrupt Controller
Overview
interrupt controller Encore!® Series products prioritizes interrupt requests from on-chip peripherals GPIO port pins. features interrupt controller include following:
unique interrupt vectors: GPIO port interrupt sources on-chip peripheral interrupt sources Flexible GPIO interrupts selectable rising falling edge GPIO interrupts dual-edge interrupts levels individually programmable interrupt priority Watch-Dog Timer configured generate interrupt
Interrupt requests (IRQs) allow peripheral devices suspend operation orderly manner force start interrupt service routine (ISR). Usually this interrupt service routine involved with exchange data, status information, control information between interrupting peripheral. When service routine completed, returns operation from which interrupted. supports both vectored polled interrupt handling. polled interrupts, interrupt control effect operation. Refer User Manual more information regarding interrupt servicing CPU. User Manual available download www.zilog.com.
Interrupt Vector Listing
Table lists interrupts available order priority. interrupt vector stored with most significant byte (MSB) even Program Memory address least significant byte (LSB) following Program Memory address.
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Table Interrupt Vectors Order Priority Program Memory Priority Vector Address Interrupt Source Highest 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H Lowest 0036H Reset (not interrupt) Watch-Dog Timer (see section Watch-Dog
Timer page
Illegal Instruction Trap (not interrupt) Reserved Timer Timer UART receiver UART transmitter Port rising falling input edge Port rising falling input edge Port rising falling input edge Port rising falling input edge Port rising falling input edge Port rising falling input edge Port rising falling input edge Port rising falling input edge Reserved Reserved Reserved Reserved Port both input edges Port both input edges Port both input edges Port both input edges
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Architecture
Figure illustrates block diagram interrupt controller.
Port Interrupts Interrupt Request Latches Control
High Priority
Vector Medium Priority Priority Request
Internal Interrupts
Priority
Figure Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
master interrupt enable (IRQE) Interrupt Control register globally enables disables interrupts. Interrupts globally enabled following actions:
Execution (Enable Interrupt) instruction Execution IRET (Return from Interrupt) instruction Writing IRQE Interrupt Control register Execution (Disable Interrupt) instruction acknowledgement interrupt service request from interrupt controller Writing IRQE Interrupt Control register Reset Execution Trap instruction
Interrupts globally disabled following actions:
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Illegal Instruction trap
Interrupt Vectors Priority
interrupt controller supports three levels interrupt priority. Level highest priority, Level second highest priority, Level lowest priority. interrupts were enabled with identical interrupt priority (all Level interrupts, example), then interrupt priority would assigned from highest lowest specified Table Level interrupts always have higher priority than Level interrupts which, turn, always have higher priority than Level interrupts. Within each interrupt priority level (Level Level Level priority assigned specified Table Reset, Watch-Dog Timer interrupt enabled), Illegal Instruction Trap always have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests only single system clock period (single pulse). When interrupt request acknowledged CPU, corresponding Interrupt Request register cleared until next interrupt occurs. Writing corresponding Interrupt Request register likewise clears interrupt request. Caution: following style coding clear bits Interrupt Request registers recommended. incoming interrupts that received between execution first command last command lost. Poor coding style that result lost interrupt requests: IRQ0 MASK IRQ0, avoid missing interrupts, following style coding clear bits Interrupt Request register recommended: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK
Software Interrupt Assertion
Program code generate interrupts directly. Writing desired Interrupt Request register triggers interrupt (assuming that interrupt enabled). When interrupt request acknowledged CPU, Interrupt Request register automatically cleared
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Caution:
following style coding generate software interrupts setting bits Interrupt Request registers recommended. incoming interrupts that received between execution first command last command lost. Poor coding style that result lost interrupt requests: IRQ0 MASK IRQ0,
Note:
avoid missing interrupts, following style coding bits Interrupt Request registers recommended: Good coding style that avoids lost interrupt requests: IRQ0, MASK
Interrupt Control Register Definitions
interrupts other than Watch-Dog Timer interrupt, interrupt control registers enable individual interrupts, interrupt priorities, indicate interrupt requests.
Interrupt Request Register
Interrupt Request (IRQ0) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ0 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending.
Table Interrupt Request Register (IRQ0)
BITS FIELD RESET ADDR
Reserved
U0RXI FC0H
U0TXI
I2CI
SPII
ADCI
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Reserved-Must T1I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service. T0I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service. U0RXI-UART Receiver Interrupt Request interrupt request pending UART receiver. interrupt request from UART receiver awaiting service. U0TXI-UART Transmitter Interrupt Request interrupt request pending UART transmitter. interrupt request from UART transmitter awaiting service. I2CI- Interrupt Request interrupt request pending I2C. interrupt request from awaiting service. SPII-SPI Interrupt Request interrupt request pending SPI. interrupt request from awaiting service. ADCI-ADC Interrupt Request interrupt request pending Analog-to-Digital Converter. interrupt request from Analog-to-Digital Converter awaiting service.
Interrupt Request Register
Interrupt Request (IRQ1) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ1 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending.
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Table Interrupt Request Register (IRQ1)
BITS FIELD RESET ADDR
PA7I
PA6I
PA5I
PA4I FC3H
PA3I
PA2I
PA1I
PA0I
PAxI-Port Interrupt Request interrupt request pending GPIO Port interrupt request from GPIO Port awaiting service. where indicates specific GPIO Port number through
Interrupt Request Register
Interrupt Request (IRQ2) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ2 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending.
Table Interrupt Request Register (IRQ2)
BITS FIELD RESET ADDR
Reserved
PC3I FC6H
PC2I
PC1I
PC0I
Reserved-Must PCxI-Port Interrupt Request interrupt request pending GPIO Port interrupt request from GPIO Port awaiting service. where indicates specific GPIO Port number through
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IRQ0 Enable High Registers
IRQ0 Enable High registers (Tables Table form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register. Table describes priority control IRQ0.
Table IRQ0 Enable Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
Table IRQ0 Enable High Register (IRQ0ENH)
BITS FIELD RESET ADDR
Reserved
T1ENH
T0ENH
U0RENH FC1H
U0TENH
I2CENH
SPIENH
ADCENH
Reserved-Must T1ENH-Timer Interrupt Request Enable High T0ENH-Timer Interrupt Request Enable High U0RENH-UART Receive Interrupt Request Enable High U0TENH-UART Transmit Interrupt Request Enable High I2CENH-I2C Interrupt Request Enable High SPIENH-SPI Interrupt Request Enable High ADCENH-ADC Interrupt Request Enable High
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Table IRQ0 Enable Register (IRQ0ENL)
BITS FIELD RESET ADDR
Reserved
T1ENL
T0ENL
U0RENL FC2H
U0TENL
I2CENL
SPIENL
ADCENL
Reserved-Must T1ENL-Timer Interrupt Request Enable T0ENL-Timer Interrupt Request Enable U0RENL-UART Receive Interrupt Request Enable U0TENL-UART Transmit Interrupt Request Enable I2CENL-I2C Interrupt Request Enable SPIENL-SPI Interrupt Request Enable ADCENL-ADC Interrupt Request Enable
IRQ1 Enable High Registers
Table describes priority control IRQ1. IRQ1 Enable High registers (Tables form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register.
Table IRQ1 Enable Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
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Table IRQ1 Enable High Register (IRQ1ENH)
BITS FIELD RESET ADDR
PA7ENH
PA6ENH
PA5ENH
PA4ENH FC4H
PA3ENH
PA2ENH
PA1ENH
PA0ENH
PAxENH-Port Bit[x] Interrupt Request Enable High
Table IRQ1 Enable Register (IRQ1ENL)
BITS FIELD RESET ADDR
PA7ENL
PA6ENL
PA5ENL
PA4ENL FC5H
PA3ENL
PA2ENL
PA1ENL
PA0ENL
PAxENL-Port Bit[x] Interrupt Request Enable
IRQ2 Enable High Registers
Table describes priority control IRQ. 2The IRQ2 Enable High registers (Tables Table form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register.
Table IRQ2 Enable Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
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Table IRQ2 Enable High Register (IRQ2ENH)
BITS FIELD RESET ADDR
Reserved
C3ENH FC7H
C2ENH
C1ENH
C0ENH
Reserved-Must C3ENH-Port Interrupt Request Enable High C2ENH-Port Interrupt Request Enable High C1ENH-Port Interrupt Request Enable High C0ENH-Port Interrupt Request Enable High
Table IRQ2 Enable Register (IRQ2ENL)
BITS FIELD RESET ADDR
Reserved
C3ENL FC8H
C2ENL
C1ENL
C0ENL
Reserved-Must C3ENL-Port Interrupt Request Enable C2ENL-Port Interrupt Request Enable C1ENL-Port Interrupt Request Enable C0ENL-Port Interrupt Request Enable
Interrupt Edge Select Register
Interrupt Edge Select (IRQES) register (Table determines whether interrupt generated rising edge falling edge selected GPIO Port input pin. min-
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imum pulse width must greater than system clock guarantee capture edge triggered interrupt. Edge detection pulses less than system clock guaranteed.
Table Interrupt Edge Select Register (IRQES)
BITS FIELD RESET ADDR
IES7
IES6
IES5
IES4 FCDH
IES3
IES2
IES1
IES0
IESx-Interrupt Edge Select interrupt request generated falling edge input. interrupt request generated rising edge input. where indicates specific GPIO Port number through
Interrupt Control Register
Interrupt Control (IRQCTL) register (Table contains master enable interrupts.
Table Interrupt Control Register (IRQCTL)
BITS FIELD RESET ADDR
IRQE
Reserved
FCFH
IRQE-Interrupt Request Enable This execution (Enable Interrupts) IRET (Interrupt Return) instruction, direct register write this bit. reset executing instruction, acknowledgement interrupt request, Reset direct register write this bit. Interrupts disabled. Interrupts enabled. Reserved-Must
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Timers
Overview
These Encore!® Series products contain 16-bit reloadable timers that used timing, event counting, generation pulse-width modulated (PWM) signals. timers' features include:
16-bit reload counter Programmable prescaler with prescale values from output generation Capture compare capability External input timer input, clock gating, capture signal. External input signal frequency limited maximum one-fourth system clock frequency. Timer output Timer interrupt
addition timers described this chapter, Baud Rate Generators unused UART, SPI, peripherals also used provide basic timing functionality. Refer respective serial communication peripheral chapters information using Baud Rate Generators timers.
Architecture
Figure illustrates architecture timers.
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Timer Block Data Block Control Timer Control
Compare
16-Bit Reload Register
System Clock Timer Input Gate Input Capture Input
Interrupt, PWM, Timer Output Control
Timer Interrupt Timer Output
16-Bit Counter with Prescaler Compare
16-Bit Compare
Figure Timer Block Diagram
Operation
timers 16-bit up-counters. Minimum time-out delay loading value 0001H into Timer Reload High Byte registers setting prescale value Maximum time-out delay loading value 0000H into Timer Reload High Byte registers setting prescale value 128. Timer reaches FFFFH, timer rolls over 0000H continues counting.
Timer Operating Modes
timers configured operate following modes: ONE-SHOT Mode ONE-SHOT mode, timer counts 16-bit Reload value stored Timer Reload High Byte registers. timer input system clock. Upon reaching Reload value, timer generates interrupt count value Timer High Byte registers reset 0001H. Then, timer automatically disabled stops counting. Also, Timer Output alternate function enabled, Timer Output changes state system clock cycle (from High from High Low) upon timer Reload.
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desired have Timer Output make permanent state change upon One-Shot timeout, first TPOL Timer Control Register start value before beginning ONE-SHOT mode. Then, after starting timer, TPOL opposite value. steps configuring timer ONE-SHOT mode initiating count follows: Write Timer Control register Disable timer Configure timer ONE-SHOT mode. prescale value. using Timer Output alternate function, initial output level (High Low). Write Timer High Byte registers starting count value. Write Timer Reload High Byte registers Reload value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. using Timer Output function, configure associated GPIO port Timer Output alternate function. Write Timer Control register enable timer initiate counting. ONE-SHOT mode, system clock always provides timer input. timer period given following equation: Reload Value Start Value Prescale ONE-SHOT Mode Time-Out Period -System Clock Frequency (Hz) CONTINUOUS Mode CONTINUOUS mode, timer counts 16-bit Reload value stored Timer Reload High Byte registers. timer input system clock. Upon reaching Reload value, timer generates interrupt, count value Timer High Byte registers reset 0001H counting resumes. Also, Timer Output alternate function enabled, Timer Output changes state (from High from High Low) upon timer Reload. steps configuring timer CONTINUOUS mode initiating count follows: Write Timer Control register Disable timer Configure timer CONTINUOUS mode. prescale value.
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using Timer Output alternate function, initial output level (High Low).
Write Timer High Byte registers starting count value (usually 0001H). This only affects first pass CONTINUOUS mode. After first timer Reload CONTINUOUS mode, counting always begins reset value 0001H. Write Timer Reload High Byte registers Reload value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. using Timer Output function, configure associated GPIO port Timer Output alternate function. Write Timer Control register enable timer initiate counting. CONTINUOUS mode, system clock always provides timer input. timer period given following equation: Reload Value Prescale CONTINUOUS Mode Time-Out Period -System Clock Frequency (Hz) initial starting value other than 0001H loaded into Timer High Byte registers, ONE-SHOT mode equation must used determine first time-out period. COUNTER Mode COUNTER mode, timer counts input transitions from GPIO port pin. timer input taken from GPIO Port Timer Input alternate function. TPOL Timer Control Register selects whether count occurs rising edge falling edge Timer Input signal. COUNTER mode, prescaler disabled. Caution: input frequency Timer Input signal must exceed one-fourth system clock frequency.
Upon reaching Reload value stored Timer Reload High Byte registers, timer generates interrupt, count value Timer High Byte registers reset 0001H counting resumes. Also, Timer Output alternate function enabled, Timer Output changes state (from High from High Low) timer Reload. steps configuring timer COUNTER mode initiating count follows: Write Timer Control register Disable timer Configure timer COUNTER mode.
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Select either rising edge falling edge Timer Input signal count. This also sets initial logic level (High Low) Timer Output alternate function. However, Timer Output function does have enabled.
Write Timer High Byte registers starting count value. This only affects first pass COUNTER mode. After first timer Reload COUNTER mode, counting always begins reset value 0001H. Generally, COUNTER mode Timer High Byte registers must written with value 0001H. Write Timer Reload High Byte registers Reload value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. Configure associated GPIO port Timer Input alternate function. using Timer Output function, configure associated GPIO port Timer Output alternate function. Write Timer Control register enable timer. COUNTER mode, number Timer Input transitions since timer start given following equation: COUNTER Mode Timer Input Transitions Current Count Value Start Value
Mode mode, timer outputs Pulse-Width Modulator (PWM) output signal through GPIO Port pin. timer input system clock. timer first counts 16bit match value stored Timer High Byte registers. When timer count value matches value, Timer Output toggles. timer continues counting until reaches Reload value stored Timer Reload High Byte registers. Upon reaching Reload value, timer generates interrupt, count value Timer High Byte registers reset 0001H counting resumes. TPOL Timer Control register Timer Output signal begins High then transitions when timer value matches value. Timer Output signal returns High after timer reaches Reload value reset 0001H. TPOL Timer Control register Timer Output signal begins then transitions High when timer value matches value. Timer Output signal returns after timer reaches Reload value reset 0001H. steps configuring timer mode initiating operation follows:
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Write Timer Control register Disable timer Configure timer mode. prescale value. initial logic level (High Low) High/Low transition Timer Output alternate function. Write Timer High Byte registers starting count value (typically 0001H). This only affects first pass mode. After first timer reset mode, counting always begins reset value 0001H. Write High Byte registers value. Write Timer Reload High Byte registers Reload value (PWM period). Reload value must greater than value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. Configure associated GPIO port Timer Output alternate function. Write Timer Control register enable timer initiate counting. period given following equation: Reload Value Prescale Period -System Clock Frequency (Hz) initial starting value other than 0001H loaded into Timer High Byte registers, One-Shot mode equation must used determine first time-out period. TPOL ratio output High time total period given Reload Value Value Output High Time Ratio Reload Value TPOL ratio output High time total period given Value Output High Time Ratio Reload Value CAPTURE Mode CAPTURE mode, current timer count value recorded when desired external Timer Input transition occurs. Capture count value written Timer High Byte Registers. timer input system clock. TPOL Timer Control register determines Capture occurs rising edge falling edge
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Timer Input signal. When Capture event occurs, interrupt generated timer continues counting. timer continues counting 16-bit Reload value stored Timer Reload High Byte registers. Upon reaching Reload value, timer generates interrupt continues counting. steps configuring timer CAPTURE mode initiating count follows: Write Timer Control register Disable timer Configure timer CAPTURE mode. prescale value. Capture edge (rising falling) Timer Input. Write Timer High Byte registers starting count value (typically 0001H). Write Timer Reload High Byte registers Reload value. Clear Timer High Byte registers 0000H. This allows user software determine interrupts were generated either capture event reload. High Byte registers still contain 0000H after interrupt, then interrupt generated Reload. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. Configure associated GPIO port Timer Input alternate function. Write Timer Control register enable timer initiate counting. CAPTURE mode, elapsed time from timer start Capture event calculated using following equation: Capture Value Start Value Prescale Capture Elapsed Time -System Clock Frequency (Hz)
COMPARE Mode COMPARE mode, timer counts 16-bit maximum Compare value stored Timer Reload High Byte registers. timer input system clock. Upon reaching Compare value, timer generates interrupt counting continues (the timer value reset 0001H). Also, Timer Output alternate function enabled, Timer Output changes state (from High from High Low) upon Compare.
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Timer reaches FFFFH, timer rolls over 0000H continue counting. steps configuring timer COMPARE mode initiating count follows: Write Timer Control register Disable timer Configure timer COMPARE mode. prescale value. initial logic level (High Low) Timer Output alternate function, desired. Write Timer High Byte registers starting count value. Write Timer Reload High Byte registers Compare value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. using Timer Output function, configure associated GPIO port Timer Output alternate function. Write Timer Control register enable timer initiate counting. COMPARE mode, system clock always provides timer input. Compare time given following equation: Compare Value Start Value Prescale Compare Mode Time -System Clock Frequency (Hz) GATED Mode GATED mode, timer counts only when Timer Input signal active state (asserted), determined TPOL Timer Control register. When Timer Input signal asserted, counting begins. timer interrupt generated when Timer Input signal deasserted timer reload occurs. determine Timer Input signal deassertion generated interrupt, read associated GPIO input value compare value stored TPOL bit. timer counts 16-bit Reload value stored Timer Reload High Byte registers. timer input system clock. When reaching Reload value, timer generates interrupt, count value Timer High Byte registers reset 0001H counting resumes (assuming Timer Input signal still asserted). Also, Timer Output alternate function enabled, Timer Output changes state (from High from High Low) timer reset. steps configuring timer GATED mode initiating count follows: Write Timer Control register Disable timer
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Configure timer GATED mode. prescale value.
Write Timer High Byte registers starting count value. This only affects first pass GATED mode. After first timer reset GATED mode, counting always begins reset value 0001H. Write Timer Reload High Byte registers Reload value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers. Configure associated GPIO port Timer Input alternate function. Write Timer Control register enable timer. Assert Timer Input signal initiate counting. CAPTURE/COMPARE Mode CAPTURE/COMPARE mode, timer begins counting first external Timer Input transition. desired transition (rising edge falling edge) TPOL Timer Control Register. timer input system clock. Every subsequent desired transition (after first) Timer Input signal captures current count value. Capture value written Timer High Byte Registers. When Capture event occurs, interrupt generated, count value Timer High Byte registers reset 0001H, counting resumes. Capture event occurs, timer counts 16-bit Compare value stored Timer Reload High Byte registers. Upon reaching Compare value, timer generates interrupt, count value Timer High Byte registers reset 0001H counting resumes. steps configuring timer CAPTURE/COMPARE mode initiating count follows: Write Timer Control register Disable timer Configure timer CAPTURE/COMPARE mode. prescale value. Capture edge (rising falling) Timer Input. Write Timer High Byte registers starting count value (typically 0001H). Write Timer Reload High Byte registers Compare value. desired, enable timer interrupt timer interrupt priority writing relevant interrupt registers.
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Configure associated GPIO port Timer Input alternate function. Write Timer Control register enable timer. Counting begins first appropriate transition Timer Input signal. interrupt generated this first edge. CAPTURE/COMPARE mode, elapsed time from timer start Capture event calculated using following equation: Capture Value Start Value Prescale Capture Elapsed Time -System Clock Frequency (Hz)
Reading Timer Count Values
current count value timers read while counting (enabled). This capability effect timer operation. When timer enabled Timer High Byte register read, contents Timer Byte register placed holding register. subsequent read from Timer Byte register returns value holding register. This operation allows accurate reads full 16-bit timer count value while enabled. When timers enabled, read from Timer Byte register returns actual value counter.
Timer Output Signal Operation
Timer Output GPIO Port alternate function. Generally, Timer Output toggled every time counter reloaded.
Timer Control Register Definitions
Timer High Byte Registers
Timer High Byte (TxH TxL) registers (Tables contain current 16-bit timer count value. When timer enabled, read from causes value stored temporary holding register. read from TMRL always returns this temporary register when timers enabled. When timer disabled, reads from TMRL reads register directly. Writing Timer High Byte registers while timer enabled recommended. There temporary holding registers available write operations, simultaneous 16-bit writes possible. either Timer High Byte registers
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written during counting, 8-bit written value placed counter (High Byte) next clock edge. counter continues counting from value.
Table Timer High Byte Register (TxH)
BITS FIELD RESET ADDR
F00H, F08H
Table Timer Byte Register (TxL)
BITS FIELD RESET ADDR
F01H, F09H
TL-Timer High Bytes These bytes, {TMRH[7:0], TMRL[7:0]}, contain current 16-bit timer count value.
Timer Reload High Byte Registers
Timer Reload High Byte (TxRH TxRL) registers (Tables store 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written Timer Reload High Byte register stored temporary holding register. When write Timer Reload Byte register occurs, temporary holding register value written Timer High Byte register. This operation allows simultaneous updates 16-bit Timer Reload value.
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COMPARE mode, Timer Reload High Byte registers store 16-bit Compare value.
Table Timer Reload High Byte Register (TxRH)
BITS FIELD RESET ADDR
F02H, F0AH
Table Timer Reload Byte Register (TxRL)
BITS FIELD RESET ADDR
F03H, F0BH
TRL-Timer Reload Register High These bytes form 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets maximum count value which initiates timer reload 0001H. COMPARE mode, these byte form 16-bit Compare value.
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Timer High Byte Registers
Timer High Byte (TxPWMH TxPWML) registers (Tables used Pulse-Width Modulator (PWM) operations. These registers also store Capture values CAPTURE CAPTURE/COMPARE modes.
Table Timer High Byte Register (TxPWMH)
BITS FIELD RESET ADDR
PWMH
F04H, F0CH
Table Timer Byte Register (TxPWML)
BITS FIELD RESET ADDR
PWML
F05H, F0DH
PWMH PWML-Pulse-Width Modulator High Bytes These bytes, {PWMH[7:0], PWML[7:0]}, form 16-bit value that compared current 16-bit timer count. When match occurs, output changes state. output value TPOL Timer Control Register (TxCTL) register. TxPWMH TxPWML registers also store 16-bit captured timer value when operating CAPTURE CAPTURE/COMPARE modes.
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Timer Control Registers
Timer Control (TxCTL0) registers (Tables allow cascading Timers.
Table Timer Control Register (TxCTL0)
BITS FIELD RESET ADDR
Reserved
Reserved
F06H, F0EH, F16H, F1EH
CSC-Cascade Timers Timer Input signal comes from pin. Timer input signal connected Timer output. Timer input signal connected Timer output.
Timer Control Registers
Timer Control (TxCTL) registers enable/disable timers, prescaler value, determine timer operating mode.
Table Timer Control Register (TxCTL)
BITS FIELD RESET ADDR
TPOL
PRES
TMODE
F07H, F0FH
TEN-Timer Enable Timer disabled. Timer enabled count. TPOL-Timer Input/Output Polarity Operation this function current operating mode timer. ONE-SHOT mode When timer disabled, Timer Output signal value this bit.
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When timer enabled, Timer Output signal complemented upon timer Reload. CONTINUOUS mode When timer disabled, Timer Output signal value this bit. When timer enabled, Timer Output signal complemented upon timer Reload. COUNTER mode When timer disabled, Timer Output signal value this bit. When timer enabled, Timer Output signal complemented upon timer Reload. mode Timer Output forced when timer disabled. When enabled, Timer Output forced High upon count match forced upon Reload. Timer Output forced High when timer disabled. When enabled, Timer Output forced upon count match forced High upon Reload. CAPTURE mode Count captured rising edge Timer Input signal. Count captured falling edge Timer Input signal. COMPARE mode When timer disabled, Timer Output signal value this bit. When timer enabled, Timer Output signal complemented upon timer Reload. GATED mode Timer counts when Timer Input signal High interrupts generated falling edge Timer Input. Timer counts when Timer Input signal interrupts generated rising edge Timer Input. CAPTURE/COMPARE mode Counting started first rising edge Timer Input signal. current count captured subsequent rising edges Timer Input signal. Counting started first falling edge Timer Input signal. current count captured subsequent falling edges Timer Input signal. PRES-Prescale value. timer input clock divided 2PRES, where PRES from prescaler reset each time Timer disabled. This insures proper clock division
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each time Timer restarted. Divide Divide Divide Divide Divide Divide Divide Divide TMODE-Timer mode ONE-SHOT mode CONTINUOUS mode COUNTER mode mode CAPTURE mode COMPARE mode GATED mode CAPTURE/COMPARE mode
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Watch-Dog Timer
Overview
Watch-Dog Timer (WDT) helps protect against corrupt unreliable software, power faults, other system-level problems which place Encore!® Series device into unsuitable operating states. Watch-Dog Timer includes following features:
Operation
On-chip oscillator selectable time-out response: Reset interrupt 24-bit programmable time-out value
Watch-Dog Timer (WDT) retriggerable one-shot timer that resets interrupts Encore!® Series device when reaches terminal count. Watch-Dog Timer uses dedicated on-chip oscillator clock source. Watch-Dog Timer only modes operation-on off. Once enabled, always counts must refreshed prevent time-out. enable performed executing instruction setting WDT_AO Option Bit. WDT_AO enables Watch-Dog Timer operate time, even instruction been executed. Watch-Dog Timer 24-bit reloadable downcounter that uses three 8-bit registers register space reload value. nominal time-out period given following equation:
Reload Value Time-out Period (ms)
where reload value decimal value 24-bit value given {WDTU[7:0], WDTH[7:0], WDTL[7:0]} typical Watch-Dog Timer oscillator frequency 10kHz. Watch-Dog Timer cannot refreshed once reaches 000002H. Reload Value must values below 000004H. Table provides
PS022506-0504
Preliminary
Watch-Dog Timer
Encore!® Series
information approximate time-out delays minimum maximum reload values.
Table Watch-Dog Timer Approximate Time-Out Delays Approximate Time-Out Delay (with 10KHz typical Oscillator Frequency) Typical 400µs 1677.5s Description Minimum time-out delay Maximum time-out delay
Reload Value (Hex) 000004 FFFFFF
Reload Value (Decimal) 16,777,215
Watch-Dog Timer Refresh
When first enabled, Watch-Dog Timer loaded with value Watch-Dog Timer Reload registers. Watch-Dog Timer then counts down 000000H unless instruction executed CPU. Execution instruction causes downcounter reloaded with Reload value stored Watch-Dog Timer Reload registers. Counting resumes following reload operation. When Encore!® Series device operating DEBUG Mode (using OnChip Debugger), Watch-Dog Timer continuously refreshed prevent spurious Watch-Dog Timer time-outs.
Watch-Dog Timer Time-Out Response
Watch-Dog Timer times when counter reaches 000000H. time-out Watch-Dog Timer generates either interrupt Reset. WDT_RES Option determines time-out response Watch-Dog Timer. Refer Option Bits chapter information regarding programming WDT_RES Option Bit. Interrupt Normal Operation configured generate interrupt when time-out occurs, Watch-Dog Timer issues interrupt request interrupt controller sets status Watch-Dog Timer Control register. interrupts enabled, responds interrupt request fetching Watch-Dog Timer interrupt vector executing code from vector address. After time-out interrupt generation, Watch-Dog Timer counter rolls over maximum value FFFFFH continues counting. Watch-Dog Timer counter automatically returned Reload Value. Reset STOP Mo
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