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PS019913-0305 Preliminary
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Document Disclaimer
ZiLOG registered trademark ZiLOG Inc. United States other countries. other products and/or service names mentioned herein trademarks companies with which they associated. ©2005 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Devices sold ZiLOG, Inc. covered warranty limitation liability provisions appearing ZiLOG, Inc. Terms Conditions Sale. ZiLOG, Inc. makes warranty merchantability fitness purpose Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights.
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Revision History
Each instance Table reflects change this document from previous revision. more detail, click appropriate link table.
Table Revision History this Document Revision Level
Date January 2005 March 2005
Section
Description
Page
Added Form Sales information Table
Provided timing equation when Baud Rate Generator peripheral 109, 115, used simple timer. Closes CR#5618. 131, 137,
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Revision History. Manual Objectives About This Manual Intended Audience Manual Conventions Safeguards Trademarks Introduction Features Part Selection Guide Block Diagram Peripheral Overview Features General Purpose I/O. Flash Controller 10-Bit Analog-to-Digital Converter. UARTs Serial Peripheral Interface Timers Interrupt Controller Reset Controller On-Chip Debugger Controller Signal Descriptions Overview Available Packages. Configurations Signal Descriptions. Characteristics Address Space Overview Register File Program Memory Data Memory Information Area Register File Address
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Control Register Summary Reset STOP Mode Recovery Overview Reset Types Reset Sources Power-On Reset Voltage Brown-Out Reset Watch-Dog Timer Reset External Reset On-Chip Debugger Initiated Reset STOP Mode Recovery STOP Mode Recovery Using Watch-Dog Timer Time-Out STOP Mode Recovery Using GPIO Port Transition HALT Low-Power Modes Overview STOP Mode HALT Mode General-Purpose I/O. Overview GPIO Port Availability Device Architecture GPIO Alternate Functions GPIO Interrupts GPIO Control Register Definitions Port Address Registers. Port Control Registers Port Input Data Registers Port Output Data Register Interrupt Controller Overview Interrupt Vector Listing Architecture Operation Master Interrupt Enable Interrupt Vectors Priority Interrupt Assertion Software Interrupt Assertion Interrupt Control Register Definitions Interrupt Request Register Interrupt Request Register Interrupt Request Register
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IRQ0 Enable High Registers IRQ1 Enable High Registers IRQ2 Enable High Registers Interrupt Edge Select Register Interrupt Port Select Register. Interrupt Control Register Timers Overview Architecture Operation Timer Operating Modes. Reading Timer Count Values Timer Output Signal Operation Timer Control Register Definitions Timer High Byte Registers Timer Reload High Byte Registers. Timer High Byte Registers Timer Control Registers Timer Control Registers Watch-Dog Timer Overview Operation Watch-Dog Timer Refresh Watch-Dog Timer Time-Out Response Watch-Dog Timer Reload Unlock Sequence Watch-Dog Timer Control Register Definitions Watch-Dog Timer Control Register Watch-Dog Timer Reload Upper, High Byte Registers UART Overview Architecture Operation Data Format Transmitting Data using Polled Method Transmitting Data using Interrupt-Driven Method Receiving Data using Polled Method Receiving Data using Interrupt-Driven Method Clear Send (CTS) Operation MULTIPROCESSOR (9-bit) Mode External Driver Enable UART Interrupts
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UART Baud Rate Generator UART Control Register Definitions. UART Transmit Data Register UART Receive Data Register UART Status Register. UART Status Register UART Control Control Registers UART Address Compare Register UART Baud Rate High Byte Registers Infrared Encoder/Decoder Overview Architecture Operation Transmitting IrDA Data Receiving IrDA Data Infrared Encoder/Decoder Control Register Definitions Serial Peripheral Interface. Overview Architecture Operation Signals Clock Phase Polarity Control Multi-Master Operation Slave Operation Error Detection Interrupts Baud Rate Generator Control Register Definitions Data Register. Control Register Status Register Mode Register Diagnostic State Register Baud Rate High Byte Registers Controller Overview Architecture Operation Signals Interrupts Software Control Transactions
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Start Stop Conditions Master Write Read Transactions Address Only Transaction with 7-bit Address Write Transaction with 7-Bit Address Address Only Transaction with 10-bit Address Write Transaction with 10-Bit Address Read Transaction with 7-Bit Address Read Transaction with 10-Bit Address Control Register Definitions Data Register. Status Register Control Register Baud Rate High Byte Registers Diagnostic State Register Diagnostic Control Register Direct Memory Access Controller Overview Operation DMA0 DMA1 Operation Configuring DMA0 DMA1 Data Transfer DMA_ADC Operation Configuring DMA_ADC Data Transfer Control Register Definitions DMAx Control Register DMAx Address Register DMAx Address High Nibble Register. DMAx Start/Current Address Byte Register DMAx Address Byte Register DMA_ADC Address Register DMA_ADC Control Register Status Register Analog-to-Digital Converter Overview Architecture Operation Automatic Power-Down Single-Shot Conversion Continuous Conversion Control Control Register Definitions Control Register
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Data High Byte Register Data Bits Register Program Memory Flash Memory Information Area Operation Timing Using Flash Frequency Registers Flash Read Protection Flash Write/Erase Protection Byte Programming Page Erase Mass Erase Flash Controller Bypass Flash Controller Behavior Debug Mode Flash Control Register Definitions. Flash Control Register Flash Status Register Page Select Register. Flash Sector Protect Register Flash Frequency High Byte Registers Read-Only Memory Information Area Code Protection Against External Access Control Register Definitions Page Select Register. Option Bits Overview Operation Option Configuration Reset Option Address Space Program Memory Address 0000H Program Memory Address 0001H On-Chip Debugger Overview Architecture Operation Interface Debug Mode Data Format Auto-Baud Detector/Generator Serial Errors
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Breakpoints On-Chip Debugger Commands On-Chip Debugger Control Register Definitions. Control Register Status Register On-Chip Oscillator Overview Operating Modes Crystal Oscillator Operation Oscillator Operation with External Network Electrical Characteristics Absolute Maximum Ratings. Characteristics On-Chip Peripheral Electrical Characteristics Characteristics General Purpose Port Input Data Sample Timing General Purpose Port Output Timing On-Chip Debugger Timing Master Mode Timing. Slave Mode Timing Timing UART Timing Instruction Set. Assembly Language Programming Introduction Assembly Language Syntax Instruction Notation Condition Codes Instruction Classes Instruction Summary Flags Register Opcode Maps Packaging Ordering Information Part Number Suffix Designations Precharacterization Product Document Information Customer Feedback Form Index
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List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Encore!® Series Block Diagram Series 40-Pin Dual Inline Package (PDIP) Series 44-Pin Plastic Leaded Chip Carrier (PLCC) Series 44-Pin Low-Profile Quad Flat Package (LQFP) Series 64-Pin Low-Profile Quad Flat Package (LQFP) Series 68-Pin Plastic Leaded Chip Carrier (PLCC) Series 80-Pin Quad Flat Package (QFP) Power-On Reset Operation) Voltage Brown-Out Reset Operation GPIO Port Block Diagram Interrupt Controller Block Diagram Timer Block Diagram UART Block Diagram UART Asynchronous Data Format without Parity UART Asynchronous Data Format with Parity UART Asynchronous MULTIPROCESSOR Mode Data Format UART Driver Enable Signal Timing (shown with Stop Parity) UART Receiver Interrupt Service Routine Flow Infrared Data Communication System Block Diagram Infrared Data Transmission Infrared Data Reception Configured Master Single Master, Single Slave System Configured Master Single Master, Multiple Slave System Configured Slave Timing When PHASE Timing When PHASE Controller Block Diagram 7-Bit Address Only Transaction Format 7-Bit Addressed Slave Data Transfer Format. 10-Bit Address Only Transaction Format 10-Bit Addressed Slave Data Transfer Format Receive Data Transfer Format 7-Bit Addressed Slave Receive Data Format 10-Bit Addressed Slave
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Analog-to-Digital Converter Block Diagram Flash Memory Arrangement. On-Chip Debugger Block Diagram Interfacing On-Chip Debugger's with RS-232 Interface Interfacing On-Chip Debugger's with RS-232 Interface Data Format Recommended 20MHz Crystal Oscillator Configuration Connecting On-Chip Oscillator External Network Typical Oscillator Frequency Function External Capacitance with 45kW Resistor Typical Active Mode Versus System Clock Frequency Maximum Active Mode Versus System Clock Frequency Typical HALT Mode Versus System Clock Frequency Maximum HALT Mode Versus System Clock Frequency. Maximum STOP Mode with enabled versus Power Supply Voltage Maximum STOP Mode with Disabled versus Power Supply Voltage Analog-to-Digital Converter Frequency Response Port Input Sample Timing. GPIO Port Output Timing On-Chip Debugger Timing Master Mode Timing Slave Mode Timing Timing UART Timing with UART Timing without Flags Register Opcode Cell Description First Opcode Second Opcode after 40-Lead Plastic Dual-Inline Package (PDIP) 44-Lead Low-Profile Quad Flat Package (LQFP) 44-Lead Plastic Lead Chip Carrier Package (PLCC) 64-Lead Low-Profile Quad Flat Package (LQFP)
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Figure 68-Lead Plastic Lead Chip Carrier Package (PLCC) Figure 80-Lead Quad-Flat Package (QFP).
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Revision History this Document Encore!® Series Part Selection Guide Encore!® Series Package Options. Signal Descriptions Characteristics Series Encore® Series Program Memory Maps Encore!® Series Information Area Series Register File Address Reset STOP Mode Recovery Characteristics Latency Reset Sources Resulting Reset Type STOP Mode Recovery Sources Resulting Action Port Availability Device Package Type Port Alternate Function Mapping Port GPIO Address Registers (PxADDR) GPIO Port Registers Sub-Registers Port Control Registers (PxCTL) Port Data Direction Sub-Registers Port Alternate Function Sub-Registers Port Output Control Sub-Registers Port High Drive Enable Sub-Registers Port Input Data Registers (PxIN) Port STOP Mode Recovery Source Enable Sub-Registers Port Output Data Register (PxOUT) Interrupt Vectors Order Priority Interrupt Request Register (IRQ0) Interrupt Request Register (IRQ1) Interrupt Request Register (IRQ2) IRQ0 Enable Priority Encoding IRQ0 Enable High Register (IRQ0ENH) IRQ0 Enable Register (IRQ0ENL) IRQ1 Enable Priority Encoding IRQ1 Enable Register (IRQ1ENL) IRQ2 Enable Priority Encoding
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
IRQ1 Enable High Register (IRQ1ENH) IRQ2 Enable Register (IRQ2ENL) IRQ2 Enable High Register (IRQ2ENH) Interrupt Edge Select Register (IRQES) Interrupt Port Select Register (IRQPS) Interrupt Control Register (IRQCTL) Timer High Byte Register (TxH) Timer Byte Register (TxL) Timer Reload High Byte Register (TxRH) Timer Reload Byte Register (TxRL) Timer High Byte Register (TxPWMH) Timer Byte Register (TxPWML) Timer Control Register (TxCTL0) Timer Control Register (TxCTL1) Watch-Dog Timer Approximate Time-Out Delays Watch-Dog Timer Control Register (WDTCTL) Watch-Dog Timer Reload Upper Byte Register (WDTU) Watch-Dog Timer Reload High Byte Register (WDTH) Watch-Dog Timer Reload Byte Register (WDTL) UART Transmit Data Register (UxTXD) UART Receive Data Register (UxRXD) UART Status Register (UxSTAT0) UART Status Register (UxSTAT1) UART Control Register (UxCTL0) UART Control Register (UxCTL1) UART Address Compare Register (UxADDR) UART Baud Rate High Byte Register (UxBRH) UART Baud Rates UART Baud Rate Byte Register (UxBRL) Clock Phase (PHASE) Clock Polarity (CLKPOL) Operation Data Register (SPIDATA) Control Register (SPICTL) Status Register (SPISTAT) Mode Register (SPIMODE) Diagnostic State Register (SPIDST) Baud Rate High Byte Register (SPIBRH)
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Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 100. Table 101. Table 102. Table 103. Table 104. Table 105.
Baud Rate Byte Register (SPIBRL) Data Register (I2CDATA) Status Register (I2CSTAT) Control Register (I2CCTL) Baud Rate High Byte Register (I2CBRH) Baud Rate Byte Register (I2CBRL) Diagnostic State Register (I2CDST) Diagnostic Control Register (I2CDIAG) DMAx Control Register (DMAxCTL) DMAx Address Register (DMAxIO) DMAx Address High Nibble Register (DMAxH) DMAx Start/Current Address Byte Register (DMAxSTART) DMAx Address Byte Register (DMAxEND) DMA_ADC Register File Address Example DMA_ADC Address Register (DMAA_ADDR) DMA_ADC Control Register (DMAACTL) DMA_ADC Status Register (DMAA_STAT) Control Register (ADCCTL) Data High Byte Register (ADCD_H) Data Bits Register (ADCD_L) Flash Memory Configurations Flash Memory Sector Addresses Series Information Area Flash Control Register (FCTL) Flash Status Register (FSTAT) Page Select Register (FPS) Flash Sector Protect Register (FPROT) Flash Frequency High Byte Register (FFREQH) Flash Frequency Byte Register (FFREQL) Encore!® Series Memory Configurations Encore!® Series Information Area Page Select Register (RPS) Flash Option Bits Program Memory Address 0000H Option Bits Program Memory Address 0000H Options Bits Program Memory Address 0001H Baud-Rate Limits
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Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139.
On-Chip Debugger Commands Control Register (OCDCTL) Status Register (OCDSTAT) Recommended Crystal Oscillator Specifications (20MHz Operation) Absolute Maximum Ratings Characteristics Power-On Reset Voltage Brown-Out Electrical Characteristics Timing Reset STOP Mode Recovery Timing External Oscillator Electrical Characteristics Timing Flash Memory Electrical Characteristics Timing Watch-Dog Timer Electrical Characteristics Timing Analog-to-Digital Converter Electrical Characteristics Timing Characteristics GPIO Port Input Timing GPIO Port Output Timing On-Chip Debugger Timing Master Mode Timing Slave Mode Timing Timing UART Timing with UART Timing without Notational Shorthand Additional Symbols Condition Codes Arithmetic Instructions Manipulation Instructions Block Transfer Instructions Control Instructions Load Instructions Logical Instructions Program Control Instructions Rotate Shift Instructions Instruction Summary Opcode Abbreviations
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Manual Objectives
This Product Specification provides detailed operating information Flash devices within Encore!® Series Microcontroller (MCU) products. Within this document, Z8F642x, Z8F482x, Z8F322x, Z8F242x, Z8F162x, Z8R642x, Z8R482x, Z8R322x, Z8R242x, Z8R162x devices referred collectively Encore!® Series unless specifically stated otherwise.
About This Manual
ZiLOG recommends that user read understand everything this manual before setting using product. However, recognize that there different styles learning. Therefore, have designed this Product Specification used either procedural manual reference guide important data.
Intended Audience
This document written ZiLOG customers experienced working with microcontrollers, integrated circuits, printed circuit assemblies.
Manual Conventions
following assumptions conventions adopted provide clarity ease use: Courier Typeface Commands, code lines fragments, bits, equations, hexadecimal addresses, various executable items distinguished from general text Courier typeface. Where font indicated, Index, name entity presented upper case.
Example: FLAGS[1] smrf.
Hexadecimal Values Hexadecimal values designated uppercase suffix appear Courier typeface.
Example: F8H.
Brackets square brackets, indicate register bus.
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Example: register R1[7:0], 8-bit register, R1[7] most significant bit, R1[0] least significant bit.
Braces curly braces, indicate single register created concatenating some combination smaller registers, buses, individual bits.
Example: 12-bit register address {0H, RP[7:4], R1[3:0]} composed 4-bit hexadecimal value (0H) 4-bit register values taken from Register Pointer (RP) Working Register most significant nibble (4-bit value) 12-bit register, R1[3:0] least significant nibble 12-bit register.
Parentheses parentheses, indicate indirect register address lookup.
Example: (R1) memory location referenced address contained Working Register
Parentheses/Bracket Combinations parentheses, indicate indirect register address lookup square brackets, indicate register bus.
Example: assume PC[15:0] contains value 1234h. (PC[15:0]) then refers contents memory location address 1234h.
Words Set, Reset Clear word implies that register condition contains logical words reset clear imply that register condition contains logical When either these terms followed number, word logical included; however, implied. Notation Bits Similar Registers field bits within register designated Register[n:n].
Example: ADDR[15:0] refers bits through Address.
Terms LSB, MSB, lsb, this document, terms MSB, when appearing upper case, mean least significant byte most significant byte, respectively. lowercase forms, msb, mean least significant most significant bit, respectively. Initial Uppercase Letters Initial uppercase letters designate settings conditions general text.
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Example Master generate Stop condition abort transfer.
Uppercase Letters uppercase letters designates names states, modes, commands.
Example considered BUSY after Start condition. Example START command triggers processing initialization sequence. Example STOP mode
Numbering Bits numbered from where indicates total number bits. example, bits register numbered from
Safeguards
important that users understand following safety terms, which defined here. Caution: Indicates procedure file become corrupted user does follow directions.
Trademarks
ZiLOG®, eZ8, Encore!®, trademarks ZiLOG, Inc. U.S.A. other countries. other trademarks property their respective corporations.
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Introduction
Encore!® family products line ZiLOG microcontroller products based upon 8-bit CPU. Encore!® Series, hereafter referred collectively Encore!® Series adds Flash memory ZiLOG's extensive line 8-bit microcontrollers. Flash in-circuit programming capability allows faster development time program changes field. Encore!® Series also includes devices that pin- function-compatible with Flash products. devices provide low-cost alternative customers require reprogrammability Flash devices. upward compatible with existing instructions. rich peripheral Encore!® makes suitable variety applications including motor control, security systems, home appliances, personal electronic devices, sensors.
Features
20MHz 64KB Flash optional ROM) with in-circuit programming capability (Flash only) register 12-channel, 10-bit analog-to-digital converter (ADC) full-duplex 9-bit UARTs with transceiver Driver Enable control Serial Peripheral Interface Infrared Data Association (IrDA)-compliant infrared encoder/decoders four 16-bit timers with capture, compare, capability Watch-Dog Timer (WDT) with internal oscillator 3-channel pins interrupts with configurable priority On-Chip Debugger
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Voltage Brown-out Protection (VBO) Power-On Reset (POR) 3.0-3.6V operating voltage with 5V-tolerant inputs +70°C -40° +105°C operating temperature ranges
Part Selection Guide
Table identifies basic features package styles available each device within Encore!® Encore!® product line.
Table Encore!® Series Part Selection Guide Flash/ (KB) Please contact ZiLOG
Part Number Z8X1621 Z8X1622 Z8X2421 Z8X2422 Z8X3221 Z8X3222 Z8X4821 Z8X4822 Z8X4823 Z8X6421 Z8X6422 Z8X6423 Form Sales
16-bit Timers UARTs 40/44-pin 64/68-pin 80-pin (KB) with Inputs with IrDA packages packages package
Flash: X=F, ROM:
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Block Diagram
Figure illustrates block diagram architecture Encore!® Series.
XTAL Oscillator
On-Chip Debugger POR/VBO Reset Controller
System Clock
Interrupt Controller
with Oscillator
Memory Busses Register
Timers
UARTs
Flash/ROM Controller
Controller
IrDA
Flash/ROM Memory
GPIO
Figure Encore!® Series Block Diagram
Peripheral Overview
Features
eZ8, ZiLOG's latest 8-bit Central Processing Unit (CPU), meets continuing demand faster more code-efficient microcontrollers. executes superset original instruction set. features include:
Direct register-to-register architecture allows each register function accumulator, improving execution time decreasing required program memory
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Software stack allows much greater depth subroutine calls interrupts than hardware stacks Compatible with existing code Expanded internal Register File allows access instructions improve execution efficiency code developed using higher-level programming languages, including Pipelined instruction fetch execution instructions improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, instructions support 12-bit linear addressing Register File MIPS operation C-Compiler friendly clock cycles instruction
more information regarding CPU, refer User Manual available download www.zilog.com.
General Purpose
Series features seven 8-bit ports (Ports A-G) 4-bit port (Port general purpose (GPIO). Each individually programmable. ports (except support 5V-tolerant inputs.
Flash Controller
Flash Controller programs erases Flash memory.
10-Bit Analog-to-Digital Converter
Analog-to-Digital Converter (ADC) converts analog input signal 10-bit binary number. accepts inputs from different analog input sources.
UARTs
Each UART full-duplex capable handling asynchronous data transfers. UARTs support 9-bit data modes, selectable parity, efficient transceiver Driver Enable signal controlling multi-transceiver bus, such RS-485.
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inter-integrated circuit (I2C®) controller makes Encore!® compatible with protocol. controller consists bidirectional lines, serial data (SDA) line serial clock (SCL) line.
Serial Peripheral Interface
serial peripheral interface (SPI) allows Encore!® exchange data between other peripheral devices such EEPROMs, converters ISDN devices. full-duplex, synchronous, character-oriented channel that supports four-wire interface.
Timers
four 16-bit reloadable timers used timing/counting events motor control operations. These timers provide 16-bit programmable reload counter operate One-Shot, Continuous, Gated, Capture, Compare, Capture Compare, modes. Only timers (Timers 0-2) available 44-pin packages.
Interrupt Controller
Series products support interrupts. These interrupts consist internal general-purpose pins. interrupts have levels programmable interrupt priority.
Reset Controller
Encore!® reset using RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
Encore!® features integrated On-Chip Debugger (OCD). provides rich debugging capabilities, such reading writing registers, programming Flash, setting breakpoints executing code. single-pin interface provides communication OCD.
Controller
Series features three channels DMA. channels register from operations. third channel automatically controls transfer data from memory.
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Signal Descriptions
Overview
Encore!® Series products available variety packages styles configurations. This chapter describes signals available configurations each package styles. information regarding physical package specifications, please refer chapter Packaging page 260.
Available Packages
Table identifies package styles that available each device within
Encore!® Series product line. Table Encore!® Series Package Options 40-Pin PDIP 44-pin LQFP 44-pin PLCC 64-pin LQFP 68-pin PLCC 80-pin
Part Number Z8X1621 Z8X1622 Z8X2421 Z8X2422 Z8X3221 Z8X3222 Z8X4821 Z8X4822 Z8X4823 Z8X6421 Z8X6422 Z8X6423 Flash: X=F,
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Configurations
Figures through illustrate configurations packages available Series. Refer Table description signals. Timer available 40-pin 44-pin packages.
PD4/RXD1 MISO CTS0 PA2/DE0 /T0OUT T0IN RESET XOUT AVDD ANA0 ANA1 ANA4 ANA5 Note: Timer supported.
TXD1 MOSI RXD0 TXD0
CTS1
T2IN T1OUT T1IN
AVSS VREF ANA2 ANA3 ANA7 ANA6 T2OUT supported.
Figure Series 40-Pin Dual Inline Package (PDIP)
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T0OUT
RXD1 TXD1 MOSI
CTS0 MISO
RXD0 TXD0
T0IN RESET XOUT AVDD ANA0 ANA1 ANA4 ANA5
CTS1 T2OUT T2IN T1OUT T1IN
ANA7 ANA3 ANA6
Figure Series 44-Pin Plastic Leaded Chip Carrier (PLCC)
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ANA2 VREF AVSS
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T0OUT
RXD1 TXD1 MOSI
CTS0 MISO
RXD0 TXD0
T0IN RESET XOUT
CTS1 T2OUT T2IN T1OUT T1IN
ANA4 ANA5
ANA6 ANA7 ANA3
AVDD ANA0 ANA1
Figure Series 44-Pin Low-Profile Quad Flat Package (LQFP)
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T0OUT
RXD1 TXD1
MISO
T0IN RESET T3OUT T3IN XOUT
RXD0 TXD0 CTS1 RCOUT T2OUT T2IN T1OUT T1IN ANA11 VREF AVSS
MOSI
CTS0
ANA9 ANA0 ANA1
ANA6 ANA7 ANA3 ANA2 ANA10 ANA4 ANA5
Figure Series 64-Pin Low-Profile Quad Flat Package (LQFP)
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AVDD ANA8
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T0OUT
RXD1 TXD1
MISO
T0IN RESET T3OUT T3IN XOUT
RXD0 TXD0 CTS1 RCOUT T2OUT T2IN T1OUT T1IN ANA11 VREF AVSS AVSS
MOSI
CTS0
AVDD ANA8 ANA9 ANA0 ANA1 ANA4 ANA5
ANA6 ANA7 ANA3 ANA2 ANA10
Figure Series 68-Pin Plastic Leaded Chip Carrier (PLCC)
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T0OUT
RXD1 TXD1
MISO
T0IN RESET T3OUT T3IN XOUT
RXD0 TXD0
MOSI
CTS0
CTS1 RCOUT
T2OUT T2IN T1OUT T1IN
AVDD ANA8 ANA9 ANA0
ANA1 ANA4 ANA5 ANA6 ANA7
ANA3 ANA2 ANA10
ANA11 VREF AVSS
Figure Series 80-Pin Quad Flat Package (QFP)
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Signal Descriptions
Table describes Encore! signals. Refer section Configurations page determine signals available specific package styles.
Table Signal Descriptions Signal Mnemonic
Description
General-Purpose Ports PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[7:0] PH[3:0] Controller Serial Clock. This output clock I2C. This multiplexed with general-purpose pin. When general-purpose configured alternate function enable function, this open-drain. Serial Data. This open-drain transfers data between slave. This multiplexed with general-purpose pin. When general-purpose configured alternate function enable function, this open-drain. Port A[7:0]. These pins used general-purpose support 5V-tolerant inputs. Port B[7:0]. These pins used general-purpose I/O. Port C[7:0]. These pins used general-purpose I/O. These pins used general-purpose support 5V-tolerant inputs Port D[7:0]. These pins used general-purpose I/O. These pins used general-purpose support 5V-tolerant inputs Port E[7:0]. These pins used general-purpose I/O. These pins used general-purpose support 5V-tolerant inputs. Port F[7:0]. These pins used general-purpose I/O. These pins used general-purpose support 5V-tolerant inputs. Port G[7:0]. These pins used general-purpose I/O. These pins used general-purpose support 5V-tolerant inputs. Port H[3:0]. These pins used general-purpose I/O.
Controller
Slave Select. This signal output input. Encore!® Series master, this configured Slave Select output. Encore!® Series slave, this input slave select. multiplexed with general-purpose pin. Serial Clock. master supplies this pin. Encore! 64K® Series master, this output. Encore!® Series slave, this input. multiplexed with general-purpose pin.
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Table Signal Descriptions (Continued) Signal Mnemonic MOSI
Description Master Slave This signal data output from master device data input slave device. multiplexed with general-purpose pin. Master Slave Out. This data input master device data output from slave device. multiplexed with general-purpose pin.
MISO UART Controllers TXD0 TXD1 RXD0 RXD1
Transmit Data. These signals transmit outputs from UARTs. signals multiplexed with general-purpose pins. Receive Data. These signals receiver inputs UARTs IrDAs. signals multiplexed with general-purpose pins. Clear Send. These signals control inputs UARTs. signals multiplexed with general-purpose pins. Driver Enable. This signal allows automatic control external RS-485 drivers. This signal approximately inverse (Transmit Empty) UART Status register. signal used ensure external RS-485 driver enabled when data transmitted UART.
CTS0 CTS1
Timers T0OUT T1OUT/ T2OUT T3OUT T0IN T1IN/ T2IN T3IN Analog ANA[11:0] VREF Analog Input. These signals inputs analog-to-digital converter (ADC). analog inputs multiplexed with general-purpose pins. Analog-to-digital converter reference voltage input. VREF must left unconnected capacitively coupled analog ground) internal voltage reference selected reference voltage. Timer Output 0-3. These signals output pins from timers. Timer Output signals multiplexed with general-purpose pins. T3OUT available 44pin package devices. Timer Input 0-3. These signals used capture, gating counter inputs. Timer Input signals multiplexed with general-purpose pins. T3IN available 44-pin package devices.
Oscillators External Crystal Input. This input crystal oscillator. crystal connected between XOUT form oscillator. This signal usable with external networks external clock driver.
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Signal Descriptions
Encore!® Series
Table Signal Descriptions (Continued) Signal Mnemonic XOUT
Description External Crystal Output. This output crystal oscillator. crystal connected between form oscillator. When system clock referred this manual, refers frequency signal this pin. This must left unconnected when using crystal. Oscillator Output. This signal output oscillator. multiplexed with general-purpose pin. This signal must left unconnected when using crystal.
RCOUT
On-Chip Debugger Debug. This control data input output from On-Chip Debugger. This open-drain. Caution:For operation On-Chip Debugger, power pins (VDD AVDD) must supplied with power ground pins (VSS AVSS) must properly grounded. open-drain must have external pull-up resistor ensure proper operation.
Reset
RESET
Power Supply AVDD AVSS
RESET. Generates Reset when asserted (driven Low).
Power Supply. Analog Power Supply. Ground. Analog Ground.
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Signal Descriptions
Encore!® Series
Characteristics
Table provides detailed information characteristics each available Series products. Data Table sorted alphabetically symbol mnemonic.
Table Characteristics Series Active Active High Internal Pull-up Pull-down Pull-up Schmitt Trigger Input
Symbol Mnemonic AVSS AVDD PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE7:0] PF[7:0] PG[7:0] PH[3:0] RESET XOUT
Direction
Reset Direction
Tri-State Output Yes, STOP mode
Open Drain Output Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable
represents integer indicate multiple pins with symbol mnemonics that differ only integer
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Preliminary
Signal Descriptions
Encore!® Series
Address Space
Overview
access three distinct address spaces:
Register File contains addresses general-purpose registers CPU, peripheral, general-purpose port control registers. Program Memory contains addresses memory locations having executable code and/or data. Data Memory contains addresses memory locations that hold data only.
These three address spaces covered briefly following subsections. more detailed information regarding address space, refer User Manual available download www.zilog.com.
Register File
Register File address space Series (4096 bytes). Register File composed sections-control registers general-purpose registers. When instructions executed, registers read from when defined sources written when defined destinations. architecture allows general-purpose registers function accumulators, address pointers, index registers, stack areas, scratch memory. upper bytes Register File address space reserved control CPU, on-chip peripherals, ports. These registers located addresses from F00H FFFH. Some addresses within 256-byte control register section reserved (unavailable). Reading from reserved Register File addresses returns undefined value. Writing reserved Register File addresses recommended produce unpredictable results. on-chip always begins address 000H Register File address space. Series provide on-chip depending upon device. Reading from Register File addresses outside available addresses (and within control register address space) returns undefined value. Writing these Register File addresses produces effect. Refer Part Selection Guide page determine amount available specific Series device.
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Address Space
Encore!® Series
Program Memory
supports 64KB Program Memory address space. Encore!® Series contains 16KB 64KB on-chip Flash /Read-Only memory (ROM) Program Memory address space, depending upon device. Reading from Program Memory addresses outside available Flash/ROM memory addresses returns FFH. Writing these unimplemented Program Memory addresses produces effect. Table describes Program Memory Maps Series products.
Table Encore® Series Program Memory Maps Program Memory Address (Hex) Z8X162x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-3FFF Z8X242x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-5FFF Z8X322x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-7FFF Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
Table page list interrupt vectors. Flash: X=F,
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Address Space
Encore!® Series
Table Encore® Series Program Memory Maps (Continued) Program Memory Address (Hex) Z8X482x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-BFFF Z8X642x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-FFFF Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
Table page list interrupt vectors. Flash: X=F,
Data Memory
Encore!® Series does CPU's 64KB Data Memory address space.
Information Area
Table describes Encore!® Series Information Area. This byte Information Area accessed setting Page Select Register When access enabled, Information Area mapped into Program Memory overlays bytes addresses FE00H FFFFH. When Information Area access enabled, execution LDCI instruction from these Program Memory addresses return Information Area data rather than Program Memory data. Reads these addresses through On-Chip Debugger also returns Information Area data. Execution code from these addresses continues correctly Program Memory. Access Information Area read-only.
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Address Space
Encore!® Series
Table Encore!® Series Information Area Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified filled with zeros (ASCII Null character). Reserved
FE54H-FFFFH
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Address Space
Encore!® Series
Register File Address
Table provides address Register File Series products. devices package styles Series support Timer GPIO Ports. Consider registers unimplemented peripherals Reserved.
Table Series Register File Address Address (Hex) Register Description Mnemonic T0RH T0RL T0PWMH T0PWML T0CTL0 T0CTL1 T1RH T1RL T1PWMH T1PWML T1CTL0 T1CTL1 T2RH T2RL T2PWMH T2PWML T2CTL0 T2CTL1 Reset (Hex) Page General Purpose 000-EFF General-Purpose Register File Timer Timer Timer XX=Undefined Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control
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Register File Address
Encore!® Series
Table Series Register File Address (Continued) Address (Hex) Register Description Mnemonic T3RH T3RL T3PWMH T3PWML T3CTL0 T3CTL1 U0TXD U0RXD U0STAT0 U0CTL0 U0CTL1 U0STAT1 U0ADDR U0BRH U0BRL U1TXD U1RXD U1STAT0 U1CTL0 U1CTL1 U1STAT1 U1ADDR U1BRH U1BRL I2CDATA I2CSTAT I2CCTL I2CBRH I2CBRL I2CDST I2CDIAG Reset (Hex) 0000011Xb 0000011Xb Page Timer (unavailable 44-pin packages) Timer High Byte Timer Byte Timer Reload High Byte Timer Reload Byte Timer High Byte Timer Byte Timer Control Timer Control 20-3F Reserved UART UART F57-F5F XX=Undefined UART0 Transmit Data UART0 Receive Data UART0 Status UART0 Control UART0 Control UART0 Status UART0 Address Compare Register UART0 Baud Rate High Byte UART0 Baud Rate Byte UART1 Transmit Data UART1 Receive Data UART1 Status UART1 Control UART1 Control UART1 Status UART1 Address Compare Register UART1 Baud Rate High Byte UART1 Baud Rate Byte Data Status Control Baud Rate High Byte Baud Rate Byte Diagnostic State Diagnostic Control Reserved
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Register File Address
Encore!® Series
Table Series Register File Address (Continued) Address (Hex) Register Description Mnemonic SPIDATA SPICTL SPISTAT SPIMODE SPIDST SPIBRH SPIBRL ADCCTL ADCD_H ADCD_L DMA0CTL DMA0IO DMA0H DMA0START DMA0END DMA1CTL DMA1IO DMA1H DMA1START DMA1END Reset (Hex) Page Serial Peripheral Interface (SPI) Data Control Status Mode Diagnostic State Reserved Baud Rate High Byte Baud Rate Byte F68-F6F Reserved Analog-to-Digital Converter (ADC) Control Reserved Data High Byte Data Bits F74-FAF Reserved DMA0 Control DMA0 Address DMA0 End/Start Address High Nibble DMA0 Start Address Byte DMA0 Address Byte DMA1 Control DMA1 Address DMA1 End/Start Address High Nibble DMA1 Start Address Byte DMA1 Address Byte DMA_ADC Address DMA_ADC Control DMA_ADC Status
DMAA_ADDR DMAACTL DMAASTAT IRQ0 IRQ0ENH IRQ0ENL IRQ1 IRQ1ENH IRQ1ENL IRQ2
Interrupt Controller Interrupt Request IRQ0 Enable High IRQ0 Enable Interrupt Request IRQ1 Enable High IRQ1 Enable Interrupt Request XX=Undefined
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Register File Address
Encore!® Series
Table Series Register File Address (Continued) Address (Hex) FC9-FCC GPIO Port GPIO Port GPIO Port GPIO Port GPIO Port GPIO Port GPIO Port XX=Undefined PS019913-0305 Register Description IRQ2 Enable High IRQ2 Enable Reserved Interrupt Edge Select Interrupt Port Select Interrupt Control Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Port Address Port Control Port Input Data Port Output Data Mnemonic IRQ2ENH IRQ2ENL IRQES IRQPS IRQCTL PAADDR PACTL PAIN PAOUT PBADDR PBCTL PBIN PBOUT PCADDR PCCTL PCIN PCOUT PDADDR PDCTL PDIN PDOUT PEADDR PECTL PEIN PEOUT PFADDR PFCTL PFIN PFOUT PGADDR PGCTL PGIN PGOUT Reset (Hex) Page
Preliminary
Register File Address
Encore!® Series
Table Series Register File Address (Continued) Address (Hex) GPIO Port Register Description Port Address Port Control Port Input Data Port Output Data Mnemonic PHADDR PHCTL PHIN PHOUT WDTCTL WDTU WDTH WDTL FCTL FSTAT FPROT FFREQH FFREQL Reset (Hex) XXX00000b Refer User Manual Page
Watch-Dog Timer (WDT) Watch-Dog Timer Control Watch-Dog Timer Reload Upper Byte Watch-Dog Timer Reload High Byte Watch-Dog Timer Reload Byte FF4-FF7 Reserved Flash Memory Controller Flash Control Flash Status Page Select enabled) Flash Sector Protect Flash Programming Frequency High Byte Flash Programming Frequency Byte FF4-FF8 Reserved Read-Only Memory Controller Page Select FFA-FFB Reserved XX=Undefined Flags Register Pointer Stack Pointer High Byte Stack Pointer Byte
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Register File Address
Encore!® Series Encore!
Control Register Summary
Timer High Byte (F00H Read/Write)
Timer current count value [15:8]
Timer Control T0CTL1 (F07H Read/Write)
Timer Mode One-Shot mode CONTINUOUS mode COUNTER mode mode CAPTURE mode COMPARE mode GATED mode Capture/COMPARE mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
Timer Byte (F01H Read/Write)
Timer current count value [7:0]
Timer Reload High Byte T0RH (F02H Read/Write)
Timer reload value [15:8]
Timer Reload Byte T0RL (HF03 Read/Write)
Timer reload value [7:0]
Timer High Byte (F08H Read/Write) Timer High Byte T0PWMH (F04H Read/Write)
Timer value [15:8] Timer current count value [15:8]
Timer Byte (F09H Read/Write) Timer Control T0CTL0 (F06H Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved Timer current count value [7:0]
Timer Reload High Byte T1RH (F0AH Read/Write)
Timer reload value [15:8]
Timer Reload Byte T1RL (F0BH Read/Write)
Timer reload value [7:0]
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Control Register Summary
Encore!® Series Encore!
Timer High Byte T1PWMH (F0CH Read/Write)
Timer value [15:8]
Timer High Byte (F10H Read/Write)
Timer current count value [15:8]
Timer Byte T1PWML (F0DH Read/Write)
Timer value [7:0]
Timer Byte (F11H Read/Write)
Timer current count value [7:0]
Timer Control T1CTL0 (F0EH Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved
Timer Reload High Byte T2RH (F12H Read/Write)
Timer reload value [15:8]
Timer Reload Byte T2RL (F13H- Read/Write)
Timer reload value [7:0]
Timer Control T1CTL1 (F0FH Read/Write)
Timer Mode One-Shot mode CONTINUOUS mode COUNTER mode mode CAPTURE mode COMPARE mode GATED mode Capture/COMPARE mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
Timer High Byte T2PWMH (F14H Read/Write)
Timer value [15:8]
Timer Byte T2PWML (F15H Read/Write)
Timer value [7:0]
Timer Control T2CTL0 (F16H Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved
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Control Register Summary
Encore!® Series Encore!
Timer Control T2CTL1 (F17H Read/Write)
Timer Mode One-Shot mode CONTINUOUS mode COUNTER mode mode CAPTURE mode COMPARE mode GATED mode CAPTURE/COMPARE mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
Timer High Byte T3PWMH (F1CH Read/Write)
Timer value [15:8]
Timer Byte T3PWML (F1DH Read/Write)
Timer value [7:0]
Timer Control T3CTL0 (F1EH Read/Write)
Reserved Cascade Timer Timer Input signal GPIO Timer Input signal Timer Reserved
Timer Control T3CTL1 (F1FH Read/Write)
Timer Mode One-Shot mode CONTINUOUS mode COUNTER mode mode CAPTURE mode COMPARE mode GATED mode Capture/COMPARE mode Prescale Value Divide Divide Divide Divide Divide Divide Divide Divide Timer Input/Output Polarity Operation this function current operating mode timer Timer Enable Timer disabled Timer enabled
Timer High Byte (F18H Read/Write)
Timer current count value [15:8]
Timer Byte (F19H Read/Write)
Timer current count value [7:0]
Timer Reload High Byte T3RH (F1AH Read/Write)
Timer reload value [15:8]
Timer Reload Byte T3RL (F1BH Read/Write)
Timer reload value [7:0]
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Control Register Summary
Encore!® Series Encore!
UART0 Transmit Data U0TXD (F40H Write Only)
UART0 transmitter data byte [7:0]
UART0 Control U0CTL0 (F42H Read/Write)
Loop Back Enable Normal operation Transmit data looped back receiver Stop Select Transmitter sends Stop Transmitter sends Stop bits Send Break break sent Output transmitter zero Parity Select Even parity parity Parity Enable Parity disabled Parity enabled Enable signal effect transmitter UART recognizes signal transmit enable control signal Receive Enable Receiver disabled Receiver enabled Transmit Enable Transmitter disabled Transmitter enabled
UART0 Receive Data U0RXD (F40H Read Only)
UART0 receiver data byte [7:0]
UART0 Status U0STAT0 (F41H Read Only)
signal Returns level signal Transmitter Empty Data currently transmitting Transmission complete Transmitter Data Register Empty Transmit Data Register full Transmit Data register empty Break Detect break occurred break occurred Framing Error framing error occurred framing occurred Overrun Error overrun error occurred overrun error occurred Parity Error parity error occurred parity error occurred Receive Data Available Receive Data Register empty byte available Receive Data Register
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Control Register Summary
Encore!® Series Encore!
UART0 Control U0CTL1 (F43H Read/Write)
Infrared Encoder/Decoder Enable Infrared endec disabled Infrared endec enabled Received Data Interrupt Enable Received data errors generate interrupt requests Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer UART chapter operation Driver Enable Polarity signal active High signal active Multiprocessor Transmit Send multiprocessor Send multiprocessor Multiprocessor Mode Multiprocessor Mode below Multiprocessor (9-bit) Enable Multiprocessor mode disabled Multiprocessor mode enabled Multiprocessor Mode with Multiprocess Mode Interrupt received bytes Interrupt only address bytes Interrupt address match following data Interrupt data following address match
UART0 Baud Rate Generator High Byte U0BRH (F46H Read/Write)
UART0 Baud Rate divisor [15:8]
UART0 Baud Rate Generator Byte U0BRL (F47H Read/Write)
UART0 Baud Rate divisor [7:0]
UART1 Transmit Data U1TXD (F48H Write Only)
UART1 transmitter data byte[7:0]
UART1 Receive Data U1RXD (F48H Read Only)
UART receiver data byte [7:0]
UART0 Status U0STAT1 (F44H Read Only)
Mulitprocessor Receive Returns value last multiprocessor Frame Current byte start frame Current byte start frame Reserved
UART0 Address Compare U0ADDR (F45H Read/Write)
UART0 Address Compare [7:0]
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Control Register Summary
Encore!® Series Encore!
UART1 Status U1STAT0 (F49H Read Only)
signal Returns level signal Transmitter Empty Data currently transmitting Transmission complete Transmitter Data Register Empty Transmit Data Register full Transmit Data register empty Break Detect break occurred break occurred Framing Error framing error occurred framing occurred Overrun Error overrun error occurred overrun error occurred Parity Error parity error occurred parity error occurred Receive Data Available Receive Data Register empty byte available Receive Data Register
UART1 Control U1CTL0 (F4AH Read/Write)
Loop Back Enable Normal operation Transmit data looped back receiver Stop Select Transmitter sends Stop Transmitter sends Stop bits Send Break break sent Output transmitter zero Parity Select Even parity parity Parity Enable Parity disabled Parity enabled Enable signal effect transmitter UART recognizes signal transmit enable control signal Receive Enable Receiver disabled Receiver enabled Transmit Enable Transmitter disabled Transmitter enabled
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Control Register Summary
Encore!® Series Encore!
UART1 Control U0CTL1 (F4BH Read/Write)
Infrared Encoder/Decoder Enable Infrared endec disabled Infrared endec enabled Received Data Interrupt Enable Received data errors generate interrupt requests Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer UART chapter operation Driver Enable Polarity signal active High signal active Multiprocessor Transmit Send multiprocessor Send multiprocessor Multiprocessor Mode Multiprocessor Mode below Multiprocessor (9-bit) Enable Multiprocessor mode disabled Multiprocessor mode enabled Multiprocessor Mode with Multiprocess Mode Interrupt received bytes Interrupt only address bytes Interrupt address match following data Interrupt data following address match
UART1 Baud Rate Generator High Byte U0BRH (F4EH Read/Write)
UART1 Baud Rate divisor [15:8]
UART1 Baud Rate Generator Byte U1BRL (F4FH Read/Write)
UART1 Baud Rate divisor [7:0]
Data I2CDATA (F50H Read/Write)
data [7:0]
Status I2CSTAT (F51H Read Only)
NACK Interrupt action required service START/STOP after Data Shift State Data being transferred Data being transferred Transmit Address State Address being transferred Address being transferred Read Write operation Read operation 10-Bit Address 7-bit address being transmitted 10-bit address being transmitted Acknowledge Acknowledge transmitted/received last byte, Acknowledge transmitted/received Receive Data Register Full received data Data register contains received data Transmit Data Register Empty Data register full Data register empty
UART1 Status U0STAT1 (F4CH Read Only)
Mulitprocessor Receive Returns value last multiprocessor Frame Current byte start frame Current byte start frame Reserved
UART1 Address Compare U0ADDR (F4DH Read/Write)
UART1 Address Compare [7:0]
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Control Register Summary
Encore!® Series Encore!
Control I2CCTL (F52H Read/Write)
Signal Filter Enable Digital filtering disabled Low-pass digital filters enabled input signals Flush Data effect Clears Data register Send send Send after next byte received from slave Enable TDRE Interrupts generate interrupt when Data register empty Generate interrupt when Transmit Data register empty Baud Rate Generator Interrupt Request Interrupts behave control generates interrupt when counts down zero Send Stop Condition issue Stop condition after data transmission complete Issue Stop condition after data transmission complete Send Start Condition send Start Condition Send Start Condition Enable disabled enabled
Data SPIDATA (F60H Read/Write)
Data [7:0]
Control SPICTL (F61H Read/Write)
Enable disabled enabled Master Mode Enabled configured Slave mode configured Master mode Wire-OR (open-drain) Mode Enabled signals configured open-drain signals (SCK, MISO, MOSI) configured open-drain Clock Polarity idles idles High Phase Select Sets phase relationship data clock. Timer Interrupt Request timer function disabled time-out interrupt enabled Start Interrupt Request effect Generate interrupt request Interrupt Request Enable interrupt requests disabled interrupt requests enabled
Baud Rate Generator High Byte I2CBRH (F53H Read/Write)
Baud Rate divisor [15:8]
Baud Rate Generator Byte I2CBRL (F54H Read/Write)
Baud Rate divisor [7:0]
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Control Register Summary
Encore!® Series Encore!
Status SPISTAT (F62H Read Only)
Slave Select Slave, asserted Slave, asserted Transmit Status data transmission progress Data transmission progress Reserved Slave Mode Transaction Abort slave mode transaction abort detected Slave mode transaction abort detected Collision multi-master collision detected Multi-master collision detected Overrun overrun error detected Overrun error detected Interrupt Request interrupt request pending interrupt request pending
Diagnostic State SPIDST (F64H Read Only)
State Transmit Clock Enable Internal transmit clock enable signal deasserted Internal transmit clock enable signal asserted Shift Clock Enable Internal shift clock enable signal deasserted Internal shift clock enable signal asserted
Baud Rate Generator High Byte SPIBRH (F66H Read/Write)
Baud Rate divisor [15:8]
Baud Rate Generator Byte SPIBRL (F67H Read/Write)
Baud Rate divisor [7:0]
Mode SPIMODE (F63H Read/Write)
Slave Select Value Master SPIMODE[1] driven driven High Slave Select configured input configured output (Master mode only) Number Data Bits Character bits bits bits bits bits bits Diagnostic Mode Control Reading from SPIBRH, SPIBRL returns reload values Reading from SPIBRH, SPIBRL returns current count value Reserved
Control ADCCTL (F70H Read/Write)
Analog Input Select 0000 ANA0 0001 ANA1 0010 ANA2 0011 ANA3 0100 ANA4 0101 ANA5 0110 ANA6 0111 ANA7 1000 ANA8 1001 ANA9 1010 ANA10 1011 ANA11 11xx Reserved Continuous Mode Select Single-shot conversion Continuous conversion External VREF select Internal voltage reference selected External voltage reference selected Reserved Conversion Enable Conversion complete Begin conversion
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Control Register Summary
Encore!® Series Encore!
Data High Byte ADCD_H (F72H Read Only)
Data [9:2]
DMA0 Address High Nibble DMA0H (FB2H Read/Write)
DMA0 Start Address [11:8] DMA0 Address [11:8]
Data Bits ADCD_L (F73H Read Only)
Reserved Data [1:0]
DMA0 Start/Current Address Byte DMA0START (FB3H Read/Write)
DMA0 Start Address [7:0]
DMA0 Control DMA0CTL (FB0H Read/Write)
Request Trigger Source Select Timer Timer Timer Timer UART0 Received Data register contains valid data UART1 Received Data register contains valid data receiver contains valid data Reserved Word Select transfers byte request transfers bytes request DMA0 Interrupt Enable DMA0 does generate interrupts DMA0 generates interrupt when Address data transferred DMA0 Data Transfer Direction Register File peripheral registers Peripheral registers Register File DMA0 Loop Enable disables after Address reloads Start Address after Address continues DMA0 Enable DMA0 disabled DMA0 enabled
DMA0 Address Byte DMA0END (FB4H Read/Write)
DMA0 Address [7:0]
DMA1 Control DMA1CTL (FB8H Read/Write)
Request Trigger Source Select Timer Timer Timer Timer UART0 Transmit Data register empty UART1 Transmit Data register empty Transmit Data register empty Reserved Word Select transfers byte request transfers bytes request DMA1 Interrupt Enable DMA1 does generate interrupts DMA1 generates interrupt when Address data transferred DMA1 Data Transfer Direction Register File peripheral registers Peripheral registers Register File DMA1 Loop Enable disables after Address reloads Start Address after Address continues DMA1 Enable DMA1 disabled DMA1 enabled
DMA0 Address DMA0IO (FB1H Read/Write)
DMA0 Peripheral Register Address byte on-chip peripheral control registers Register File page
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Control Register Summary
Encore!® Series Encore!
DMA1 Address DMA1IO (FB9H Read/Write)
DMA1 Peripheral Register Address byte on-chip peripheral control registers Register File page
DMA_ADC Control DMAACTL (FBEH Read/Write)
Analog Input Number 0000 Analog input updated 0001 Analog input updated 0010 Analog input updated 0011 Analog input updated 0100 Analog input updated 0101 Analog input updated 0100 Analog input updated 0101 Analog input updated 1000 Analog input updated 1001 Analog input updated 1010 Analog input 0-10 updated 1011 Analog inputs 0-11 updated 11xx Reserved Reserved
DMA1 Address High Nibble DMA1H (FBAH Read/Write)
DMA1 Start Address [11:8] DMA1 Address [11:8]
DMA1 Start/Current Address Byte DMA1START (FBBH Read/Write)
DMA1 Start Address [7:0]
Interrupt request enable DMA_ADC does generate interrupt requests DMA_ADC generates interrupt requests after last analog input DMA_ADC Enable DMA_ADC disabled DMA_ADC enabled
DMA1 Address Byte DMA1END (FBCH Read/Write)
DMA1 Address [7:0]
Status DMAA_STAT (FBFH Read Only)
DMA0 Interrupt Request Indicator DMA0 source DMA0 source DMA1 Interrupt Request Indicator DMA1 source DMA1 source DMA_ADC Interrupt Request Indicator DMA_ADC source DMA_ADC source Reserved Current analog input Identifies analog input currently converting
DMA_ADC Address DMAA_ADDR (FBDH Read/Write)
Reserved DMA_ADC Address
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Control Register Summary
Encore!® Series Encore!
Interrupt Request IRQ0 (FC0H Read/Write)
Interrupt Request Interrupt Request Interrupt Request UART Transmitter Interrupt Request UART Receiver Interrupt Request Timer Interrupt Request Timer Interrupt Request Timer Interrupt Request above peripherals: Peripheral pending Peripheral awaiting service
IRQ0 Enable IRQ0ENL (FC2H Read/Write)
Enable Enable Enable UART Transmitter Enable UART Receiver Enable Timer Enable Timer Enable Timer Enable
Interrupt Request IRQ1 (FC3H Read/Write)
Port Interrupt Request from corresponding [7:0] pending from corresponding [7:0] awaiting service
IRQ0 Enable High IRQ0ENH (FC1H Read/Write)
Enable Enable High Enable High UART Transmitter Enable High UART Receiver Enable High Timer Enable High Timer Enable High Timer Enable High
IRQ1 Enable High IRQ1ENH (FC4H Read/Write)
Port Enable High
IRQ1 Enable IRQ1ENL (FC5H Read/Write)
Port Enable
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Control Register Summary
Encore!® Series Encore!
Interrupt Request IRQ2 (FC6H Read/Write)
Port Interrupt Request from corresponding [3:0] pending from corresponding [3:0] awaiting service Interrupt Request UART Transmitter Interrupt Request UART Receiver Interrupt Request Timer Interrupt Request above peripherals: Peripheral pending Peripheral awaiting service
Interrupt Port Select IRQPS (FCEH Read/Write)
Port Port Select [7:0] Port interrupt source Port interrupt source
Interrupt Control IRQCTL (FCFH Read/Write)
Reserved Interrupt Request Enable Interrupts disabled Interrupts enabled
IRQ2 Enable High IRQ2ENH (FC7H Read/Write)
Port Enable High Enable High UART Transmitter Enable High UART Receiver Enable High Timer Enable High
Port Address PAADDR (FD0H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
IRQ2 Enable IRQ2ENL (FC8H Read/Write)
Port Enable Enable UART Transmitter Enable UART Receiver Enable Timer Enable
Port Control PACTL (FD1H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
Port Input Data PAIN (FD2H Read Only)
Port Input Data [7:0]
Interrupt Edge Select IRQES (FCDH Read/Write)
Port Interrupt Edge Select [7:0] Falling edge Rising edge
Port Output Data PAOUT (FD3H Read/Write)
Port Output Data [7:0]
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Control Register Summary
Encore!® Series Encore!
Port Address PBADDR (FD4H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PCIN (FDAH Read Only)
Port Input Data [7:0]
Port Output Data PCOUT (FDBH Read/Write)
Port Output Data [7:0]
Port Control PBCTL (FD5H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
Port Address PDADDR (FDCH Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PBIN (FD6H Read Only)
Port Input Data [7:0]
Port Output Data PBOUT (FD7H Read/Write)
Port Output Data [7:0]
Port Control PDCTL (FDDH Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
Port Address PCADDR (FD8H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PDIN (FDE Read Only)
Port Input Data [7:0]
Port Output Data PDOUT (FDFH Read/Write)
Port Output Data [7:0]
Port Control PCCTL (FD9H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
PS019913-0305
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Control Register Summary
Encore!® Series Encore!
Port Address PEADDR (FE0H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PFIN (FE6H Read Only)
Port Input Data [7:0]
Port Output Data PFOUT (FE7H Read/Write)
Port Output Data [7:0]
Port Control PECTL (FE1H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
Port Address PGADDR (FE8H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PEIN (FE2H Read Only)
Port Input Data [7:0]
Port Output Data PEOUT (FE3H Read/Write)
Port Output Data [7:0]
Port Control PGCTL (FE9H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
Port Address PFADDR (FE4H Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Port Input Data PGIN (FEAH Read Only)
Port Input Data [7:0]
Port Output Data PGOUT (FEBH Read/Write)
Port Output Data [7:0]
Port Control PFCTL (FE5H Read/Write)
Port Control[7:0] Provides Access Port Sub-Registers
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Encore!® Series Encore!
Port Address PHADDR (FECH Read/Write)
Port Address[7:0] Selects Port Sub-Registers: function Data direction Alternate function Output control (open-drain) High drive enable STOP mode recovery enable 06H-FFH function
Watch-Dog Timer Control WDTCTL (FF0H Read Only)
Configuration Indicator Reserved Reset generated RESET Reset generated RESET timeout occurred timeout occurred STOP occurred occurred occurred occurred
Port Control PHCTL (FEDH Read/Write)
Port Control [3:0] Provides Access Port Sub-Registers Reserved
Watch-Dog Timer Reload Upper Byte WDTU (FF1H Read/Write)
reload value [23:16]
Port Input Data PHIN (FEEH Read Only)
Port Input Data [3:0] Reserved
Watch-Dog Timer Reload Middle Byte WDTH (FF2 Read/Write)
reload value [15:8]
Port Output Data PHOUT (FEFH Read/Write)
Port Output Data [3:0] Reserved
Watch-Dog Timer Reload Byte WDTL (FF3H Read/Write)
reload value [7:0]
Flash Control FCTL (FF8H Write Only)
Flash Command First unlock command Second unlock command Page erase command Mass erase command Flash Sector Protect select
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Encore!® Series Encore!
Flash Status FSTAT (FF8H Read Only)
Flash Controller Status 00_0000 Flash controller locked 00_0001 First unlock received 00_0010 Second unlock received 00_0011 Flash controller unlocked 00_0100 Flash Sector Protect register selected 00_1xxx Programming progress 01_0xxx Page erase progress 10_0xxx Mass erase progress Reserved
Flags FLAGS (FFC Read/Write)
User Flag User Flag Half Carry Decimal Adjust Overflow Flag Sign Flag Zero Flag
Page Select (FF9H Read/Write)
Page Select [6:0] Identifies Flash memory page Page Erase operation. Information Area Enable Information Area access disabled Information Area access enabled
Carry Flag
Register Pointer (FFDH Read/Write)
Working Register Page Address [11:8] Working Register Group Address [7:4]
Flash Sector Protect FPROT (FF9H Read/Write 1's)
Flash Sector Protect [7:0] Sector programmed erased from user code Sector protected cannot programmed erased from user code
Stack Pointer High Byte (FFEH Read/Write)
Stack Pointer [15:8]
Stack Pointer Byte (FFFH Read/Write)
Stack Pointer [7:0]
Flash Frequency High Byte FFREQH (FFAH Read/Write)
Flash Frequency value [15:8]
Flash Frequency Byte FFREQL (FFBH Read/Write)
Flash Frequency value [7:0]
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Reset STOP Mode Recovery
Overview
Reset Controller within Encore!® Series controls Reset STOP Mode Recovery operation. typical operation, following events cause Reset occur:
Power-On Reset (POR) Voltage Brown-Out (VBO) Watch-Dog Timer time-out (when configured WDT_RES Option initiate Reset) External RESET assertion On-Chip Debugger initiated Reset (OCDCTL[0]
When Series devices STOP mode, STOP Mode Recovery initiated either following:
Reset Types
Watch-Dog Timer time-out GPIO Port input transition enabled STOP Mode Recovery source driven
Series provides different types reset operation (System Reset STOP Mode Recovery). type Reset function both current operating mode Series devices source Reset. Table lists types Reset their operating characteristics.
Table Reset STOP Mode Recovery Characteristics Latency Reset Characteristics Latency Reset Type System Reset STOP Mode Recovery Control Registers Reset applicable) Unaffected, except WDT_CTL register Reset Latency (Delay) Reset Reset Oscillator cycles System Clock cycles Oscillator cycles System Clock cycles
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System Reset During System Reset, Series devices held Reset cycles Watch-Dog Timer oscillator followed cycles system clock. beginning Reset, GPIO pins configured inputs. During Reset, on-chip peripherals idle; however, on-chip crystal oscillator Watch-Dog Timer oscillator continue run. system clock begins operating following Watch-Dog Timer oscillator cycle count. on-chip peripherals remain idle through cycles system clock. Upon Reset, control registers within Register File that have defined Reset value loaded with their reset values. Other control registers (including Stack Pointer, Register Pointer, Flags) general-purpose undefined following Reset. fetches Reset vector Program Memory addresses 0002H 0003H loads that value into Program Counter. Program execution begins Reset vector address.
Reset Sources
Table lists reset sources function operating mode. text following provides more detailed information individual Reset sources. Power-On Reset/Voltage Brown-Out event always takes priority over other possible reset sources ensure full system reset occurs.
Table Reset Sources Resulting Reset Type Operating Mode Normal HALT modes Reset Source Reset Type
Power-On Reset Voltage Brown-Out System Reset Watch-Dog Timer time-out when configured Reset RESET assertion On-Chip Debugger initiated Reset (OCDCTL[0] System Reset System Reset System Reset except On-Chip Debugger unaffected reset
STOP mode
Power-On Reset Voltage Brown-Out System Reset RESET assertion driven System Reset System Reset
Power-On Reset
Each device Series contains internal Power-On Reset (POR) circuit. circuit monitors supply voltage holds device Reset state until supply voltage reaches safe operating level. After supply voltage exceeds
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voltage threshold (VPOR), Counter enabled counts cycles WatchDog Timer oscillator. After counter times out, XTAL Counter enabled count total system clock pulses. devices held Reset state until both Counter XTAL counter have timed out. After Series devices exit Power-On Reset state, fetches Reset vector. Following Power-On Reset, status Watch-Dog Timer Control (WDTCTL) register Figure illustrates Power-On Reset operation. Refer Electrical Characteristics chapter threshold voltage (VPOR).
3.3V VPOR VVBO
0.0V
Program Execution
Clock
Primary Oscillator Oscillator Start-up
Internal RESET signal
Scale
counter delay
XTAL counter delay
Figure Power-On Reset Operation)
Voltage Brown-Out Reset
devices Series provide Voltage Brown-Out (VBO) protection. circuit senses when supply voltage drops unsafe level (below threshold voltage) forces device into Reset state. While supply voltage remains below Power-On Reset voltage threshold (VPOR), block holds device Reset state. After supply voltage again exceeds Power-On Reset voltage threshold, devices progress through full System Reset sequence, described Power-On Reset sec-
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tion. Following Power-On Reset, status Watch-Dog Timer Control (WDTCTL) register Figure illustrates Voltage Brown-Out operation. Refer Electrical Characteristics chapter threshold voltages (VVBO VPOR). Voltage Brown-Out circuit either enabled disabled during STOP mode. Operation during STOP mode VBO_AO Option Bit. Refer Option Bits chapter information configuring VBO_AO.
3.3V VPOR VVBO Program Execution Voltage Brownout Program Execution
3.3V
Clock
Primary Oscillator
Internal RESET Signal
Counter Delay
XTAL Counter Delay
Figure Voltage Brown-Out Reset Operation
Watch-Dog Timer Reset
device normal HALT mode, Watch-Dog Timer initiate System Reset time-out WDT_RES Option This capability default (unprogrammed) setting WDT_RES Option Bit. status Control register signify that reset initiated Watch-Dog Timer.
External Reset
RESET Schmitt-triggered input, internal pull-up, analog filter digital filter reject noise. Once RESET asserted least system clock
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cycles, devices progress through System Reset sequence. While RESET input asserted Low, Series devices continue held Reset state. RESET held beyond System Reset time-out, devices exit Reset state immediately following RESET deassertion. Following System Reset initiated external RESET pin, status Watch-Dog Timer Control (WDTCTL) register
On-Chip Debugger Initiated Reset
Power-On Reset initiated using On-Chip Debugger setting Control register. On-Chip Debugger block reset rest chip goes through normal system reset. automatically clears during system reset. Following system reset Control register set.
STOP Mode Recovery
STOP mode entered executing STOP instruction. Refer Section Low-Power Modes page detailed STOP mode information. During STOP Mode Recovery, devices held reset cycles Watch-Dog Timer oscillator followed cycles system clock. STOP Mode Recovery only affects contents Watch-Dog Timer Control register. STOP Mode Recovery does affect other values Register File, including Stack Pointer, Register Pointer, Flags, peripheral control registers, general-purpose RAM. fetches Reset vector Program Memory addresses 0002H 0003H loads that value into Program Counter. Program execution begins Reset vector address. Following STOP Mode Recovery, STOP Watch-Dog Timer Control Register Table lists STOP Mode Recovery sources resulting actions. text following provides more detailed information each STOP Mode Recovery sources.
Table STOP Mode Recovery Sources Resulting Action Operating Mode STOP mode STOP Mode Recovery Source Watch-Dog Timer time-out when configured Reset Watch-Dog Timer time-out when configured interrupt Data transition GPIO Port enabled STOP Mode Recovery source Action STOP Mode Recovery STOP Mode Recovery followed interrupt interrupts enabled) STOP Mode Recovery
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STOP Mode Recovery Using Watch-Dog Timer Time-Out
Watch-Dog Timer times during STOP mode, device undergoes STOP Mode Recovery sequence. Watch-Dog Timer Control register, STOP bits Watch-Dog Timer configured generate interrupt upon timeout Series devices configured respond interrupts, services Watch-Dog Timer interrupt request following normal STOP Mode Recovery sequence.
STOP Mode Recovery Using GPIO Port Transition HALT
Each GPIO Port pins configured STOP Mode Recovery input source. GPIO enabled STOP Mode Recovery source, change input value (from High from High) initiates STOP Mode Recovery. GPIO STOP Mode Recovery signals filtered reject pulses less than 10ns (typical) duration. Watch-Dog Timer Control register, STOP Caution: STOP mode, GPIO Port Input Data registers (PxIN) disabled. Port Input Data registers record Port transition only signal stays Port through STOP Mode Recovery delay. Thus, short pulses Port initiate STOP Mode Recovery without being written Port Input Data register without initiating interrupt enabled that pin).
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Low-Power Modes
Overview
Series products contain power-saving features. highest level power reduction provided STOP mode. next level power reduction provided HALT mode.
STOP Mode
Execution CPU's STOP instruction places device into STOP mode. STOP mode, operating characteristics are:
Primary crystal oscillator stopped; driven High XOUT driven Low. System clock stopped stopped Program counter (PC) stops incrementing Watch-Dog Timer internal oscillator continue operate, enabled operation during STOP mode. Voltage Brown-Out protection circuit continues operate, enabled operation STOP mode using associated Option Bit. other on-chip peripherals idle.
minimize current STOP mode, GPIO pins that configured digital inputs must driven supply rails (VCC GND), Voltage Brown-Out protection must disabled, Watch-Dog Timer must disabled. devices brought STOP mode using STOP Mode Recovery. more information STOP Mode Recovery refer Reset STOP Mode Recovery chapter beginning page Caution: STOP Mode must used when driving Series devices with external clock driver source.
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HALT Mode
Execution CPU's HALT instruction places device into HALT mode. HALT mode, operating characteristics are:
Primary crystal oscillator enabled continues operate System clock enabled continues operate stopped Program counter (PC) stops incrementing Watch-Dog Timer's internal oscillator continues operate Watch-Dog Timer continues operate, enabled other on-chip peripherals continue operate
brought HALT mode following operations: Interrupt Watch-Dog Timer time-out (interrupt reset) Power-on reset Voltage-brown reset External RESET assertion
minimize current HALT mode, GPIO pins which configured inputs must driven supply rails (VCC GND).
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Low-Power Modes
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General-Purpose
Overview
Series products support maximum seven 8-bit ports (Ports A-G) 4bit port (Port general-purpose input/output (I/O) operations. Each port contains control data registers. GPIO control registers used determine data direction, open-drain, output drive current alternate functions. Each port individually programmable. ports (except support 5V-tolerant inputs.
GPIO Port Availability Device
Table lists port pins available with each device package type.
Table Port Availability Device Package Type Device Z8X1621 Z8X1621 Z8X1622 Z8X2421 Z8X2421 Z8X2422 Z8X3221 Z8X3221 Z8X3222 Z8X4821 Z8X4821 Z8X4822 Z8X4823 Packages 40-pin 44-pin 68-pin 40-pin 44-pin 68-pin 40-pin 44-pin 68-pin 40-pin 44-pin 68-pin 80-pin Port [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Port [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Port [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] Port [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [7:0] Port [7:0] [7:0] [7:0] [7:0] [7:0] Port [7:0] Port [7:0] Port [3:0] [3:0] [3:0] [3:0] [3:0]
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Table Port Availability Device Package Type (Continued) Device Z8X6421 Z8X6421 Z8X6422 Z8X6423 Packages 40-pin 44-pin 68-pin 80-pin Port [7:0] [7:0] [7:0] [7:0] Port [7:0] [7:0] [7:0] [7:0] Port [6:0] [7:0] [7:0] [7:0] Port [6:3, 1:0] [6:0] [7:0] [7:0] Port [7:0] [7:0] Port [7:0] Port [7:0] Port [3:0] [3:0]
Architecture
Figure illustrates simplified block diagram GPIO port pin. this figure, ability accommodate alternate functions variable port current drive strength illustrated.
Port Input Data Register Schmitt Trigger
System Clock Port Output Control Port Output Data Register DATA System Clock Port
Port Data Direction
Figure GPIO Port Block Diagram
GPIO Alternate Functions
Many GPIO port pins used both general-purpose provide access on-chip peripheral functions such timers serial communication devices. Port Alternate Function sub-registers configure these pins either general-purpose
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alternate function operation. When configured alternate function, control port direction (input/output) passed from Port Data Direction registers alternate function assigned this pin. Table lists alternate functions associated with each port pin.
Table Port Alternate Function Mapping Port Port Port Port Mnemonic T0IN T0OUT CTS0 Alternate Function Description Timer Input Timer Output UART Driver Enable UART Clear Send
RXD0 IRRX0 UART IrDA Receive Data TXD0 IRTX0 ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 T1IN T1OUT MOSI MISO T2IN T2OUT UART IrDA Transmit Data Clock (automatically open-drain) Data (automatically open-drain) Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Timer Input Timer Output Slave Select Serial Clock Master Slave Master Slave Timer Timer
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Table Port Alternate Function Mapping (Continued) Port Port Port Port Port Port Mnemonic T3IN T3OUT Alternate Function Description Timer (unavailable 44-pin packages) Timer (unavailable 44-pin packages) alternate function UART Driver Enable
RXD1 IRRX1 UART IrDA Receive Data TXD1 IRTX1 CTS1 RCOUT UART IrDA Transmit Data UART Clear Send Watch-Dog Timer Oscillator Output alternate functions alternate functions alternate functions Analog Input Analog Input Analog Input Analog Input
PE[7:0] PF[7:0] PG[7:0] ANA8 ANA9 ANA10 ANA11
GPIO Interrupts
Many GPIO port pins used interrupt sources. Some port pins configured generate interrupt request either rising edge falling edge input signal. Other port interrupts generate interrupt when edge occurs (both rising falling). Refer Interrupt Controller chapter more information interrupts using GPIO pins.
GPIO Control Register Definitions
Four registers each Port provide access GPIO control, input data, output data. Table lists these Port registers. Port Address Control registers together provide access sub-registers Port configuration control.
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Table GPIO Port Registers Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic PxDD PxAF PxOC PxDD PxSMRE Port Register Name Port Address Register (Selects sub-registers) Port Control Register (Provides access sub-registers) Port Input Data Register Port Output Data Register Port Register Name Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable
Port Address Registers
Port Address registers select GPIO Port functionality accessible through Port Control registers. Port Address Control registers combine provide access GPIO Port control (Table 14).
Table Port GPIO Address Registers (PxADDR)
BITS FIELD RESET ADDR
PADDR[7:0] FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
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PADDR[7:0]-Port Address Port Address selects sub-registers accessible through Port Control register.
PADDR[7:0] 06H-FFH Port Control sub-register accessible using Port Control Registers function. Provides some protection against accidental Port reconfiguration. Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable. function.
Port Control Registers
Port Control registers GPIO port operation. value corresponding Port Address register determines control sub-registers accessible using Port Control register (Table 15).
Table Port Control Registers (PxCTL)
BITS FIELD RESET ADDR
PCTL
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
PCTL[7:0]-Port Control Port Control register provides access sub-registers that configure GPIO Port operation.
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Port Data Direction Sub-Registers Port Data Direction sub-register accessed through Port Control register writing Port Address register (Table 16).
Table Port Data Direction Sub-Registers
BITS FIELD RESET ADDR
Port Address Register, accessible through Port Control Register
DD[7:0]-Data Direction These bits control direction associated port pin. Port Alternate Function operation overrides Data Direction register setting. Output. Data Port Output Data register driven onto port pin. Input. port sampled value written into Port Input Data Register. output driver tri-stated. Port Alternate Function Sub-Registers Port Alternate Function sub-register (Table accessed through Port Control register writing Port Address register. Port Alternate Function sub-registers select alternate functions selected pins. Refer GPIO Alternate Functions section determine alternate function associated with each port pin. Caution: enable alternate function GPIO port pins which have associated alternate function. Failure follow this guideline result unpredictable operation.
Table Port Alternate Function Sub-Registers
BITS FIELD RESET ADDR
Port Address Register, accessible through Port Control Register
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AF[7:0]-Port Alternate Function enabled port normal mode Port Data Direction subregister determines direction pin. alternate function selected. Port operation controlled alternate function. Port Output Control Sub-Registers Port Output Control sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port Output Control sub-registers configures specified port pins opendrain operation. These sub-registers affect pins directly and, result, alternate functions also affected.
Table Port Output Control Sub-Registers
BITS FIELD RESET ADDR
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
Port Address Register, accessible through Port Control Register
POC[7:0]-Port Output Control These bits function independently alternate function disables drains drains enabled output mode. drain associated disabled (open-drain mode).
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Port High Drive Enable Sub-Registers Port High Drive Enable sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port High Drive Enable sub-registers configures specified port pins high current output drive operation. Port High Drive Enable sub-register affects pins directly and, result, alternate functions also affected.
Table Port High Drive Enable Sub-Registers
BITS FIELD RESET ADDR
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
Port Address Register, accessible through Port Control Register
PHDE[7:0]-Port High Drive Enabled Port configured standard output current drive. Port configured high output current drive. Port STOP Mode Recovery Source Enable Sub-Registers Port STOP Mode Recovery Source Enable sub-register (Table accessed through Port Control register writing Port Address register. Setting bits Port STOP Mode Recovery Source Enable sub-registers configures specified Port pins STOP Mode Recovery source. During STOP Mode, logic transition Port enabled STOP Mode Recovery source initiates STOP Mode Recovery.
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Table Port STOP Mode Recovery Source Enable Sub-Registers
BITS FIELD RESET ADDR
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
Port Address Register, accessible through Port Control Register
PSMRE[7:0]-Port STOP Mode Recovery Source Enabled Port configured STOP Mode Recovery source. Transitions this during STOP mode initiate STOP Mode Recovery. Port configured STOP Mode Recovery source. logic transition this during STOP mode initiates STOP Mode Recovery.
Port Input Data Registers
Reading from Port Input Data registers (Table returns sampled values from corresponding port pins. Port Input Data registers Read-only.
Table Port Input Data Registers (PxIN)
BITS FIELD RESET ADDR
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
PIN[7:0]-Port Input Data Sampled data from corresponding port input. Input data logical (Low). Input data logical (High).
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Port Output Data Register
Port Output Data register (Table writes output data pins.
Table Port Output Data Register (PxOUT)
BITS FIELD RESET ADDR
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
POUT[7:0]-Port Output Data These bits contain data driven from port pins. values only driven corresponding configured output configured alternate function operation. Drive logical (Low). Drive logical (High). High value driven drain been disabled setting corresponding Port Output Control register
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Interrupt Controller
Overview
interrupt controller Series products prioritizes interrupt requests from on-chip peripherals GPIO port pins. features interrupt controller include following:
unique interrupt vectors: GPIO port interrupt sources on-chip peripheral interrupt sources Flexible GPIO interrupts selectable rising falling edge GPIO interrupts dual-edge interrupts levels individually programmable interrupt priority Watch-Dog Timer configured generate interrupt
Interrupt requests (IRQs) allow peripheral devices suspend operation orderly manner force start interrupt service routine (ISR). Usually this interrupt service routine involved with exchange data, status information, control information between interrupting peripheral. When service routine completed, returns operation from which interrupted. supports both vectored polled interrupt handling. polled interrupts, interrupt control effect operation. Refer User Manual more information regarding interrupt servicing CPU. User Manual available download www.zilog.com.
Interrupt Vector Listing
Table lists interrupts available order priority. interrupt vector stored with most significant byte (MSB) even Program Memory address least significant byte (LSB) following Program Memory address.
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Table Interrupt Vectors Order Priority Program Memory Priority Vector Address Interrupt Source Highest 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H Lowest 0036H Reset (not interrupt) Watch-Dog Timer (see Watch-Dog Timer chapter) Illegal Instruction Trap (not interrupt) Timer Timer Timer UART receiver UART transmitter Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Port Port rising falling input edge Timer (not available 44-pin packages) UART receiver UART transmitter Port both input edges Port both input edges Port both input edges Port both input edges
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Architecture
Figure illustrates block diagram interrupt controller.
Port Interrupts Interrupt Request Latches Control
High Priority Vector Priority Request
Medium Priority
Internal Interrupts
Priority
Figure Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
master interrupt enable (IRQE) Interrupt Control register globally enables disables interrupts. Interrupts globally enabled following actions:
Executing (Enable Interrupt) instruction Executing IRET (Return from Interrupt) instruction Writing IRQE Interrupt Control register Execution (Disable Interrupt) instruction acknowledgement interrupt service request from interrupt controller Writing IRQE Interrupt Control register Reset
Interrupts globally disabled following actions:
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Executing Trap instruction Illegal Instruction trap
Interrupt Vectors Priority
interrupt controller supports three levels interrupt priority. Level highest priority, Level second highest priority, Level lowest priority. interrupts were enabled with identical interrupt priority (all Level interrupts, example), then interrupt priority would assigned from highest lowest specified Table Level interrupts always have higher priority than Level interrupts which, turn, always have higher priority than Level interrupts. Within each interrupt priority level (Level Level Level priority assigned specified Table Reset, Watch-Dog Timer interrupt enabled), Illegal Instruction Trap always have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests only single system clock period (single pulse). When interrupt request acknowledged CPU, corresponding Interrupt Request register cleared until next interrupt occurs. Writing corresponding Interrupt Request register likewise clears interrupt request. Caution: following style coding clear bits Interrupt Request registers recommended. incoming interrupts that received between execution first command last command lost. Poor coding style that result lost interrupt requests: IRQ0 MASK IRQ0, avoid missing interrupts, following style coding clear bits Interrupt Request register recommended: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK
Software Interrupt Assertion
Program code generate interrupts directly. Writing desired Interrupt Request register triggers interrupt (assuming that interrupt enabled). When interrupt request acknowledged CPU, Interrupt Request register automatically cleared
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Caution:
following style coding generate software interrupts setting bits Interrupt Request registers recommended. incoming interrupts that received between execution first command last command lost. Poor coding style that result lost interrupt requests: IRQ0 MASK IRQ0, avoid missing interrupts, following style coding bits Interrupt Request registers recommended: Good coding style that avoids lost interrupt requests: IRQ0, MASK
Interrupt Control Register Definitions
interrupts other than Watch-Dog Timer interrupt, interrupt control registers enable individual interrupts, interrupt priorities, indicate interrupt requests.
Interrupt Request Register
Interrupt Request (IRQ0) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ0 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending
Table Interrupt Request Register (IRQ0)
BITS FIELD RESET ADDR
U0RXI FC0H
U0TXI
I2CI
SPII
ADCI
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T2I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service. T1I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service. T0I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service. U0RXI-UART Receiver Interrupt Request interrupt request pending UART receiver. interrupt request from UART receiver awaiting service. U0TXI-UART Transmitter Interrupt Request interrupt request pending UART transmitter. interrupt request from UART transmitter awaiting service. I2CI- Interrupt Request interrupt request pending I2C. interrupt request from awaiting service. SPII-SPI Interrupt Request interrupt request pending SPI. interrupt request from awaiting service. ADCI-ADC Interrupt Request interrupt request pending Analog-to-Digital Converter. interrupt request from Analog-to-Digital Converter awaiting service.
Interrupt Request Register
Interrupt Request (IRQ1) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ1 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending.
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Table Interrupt Request Register (IRQ1)
BITS FIELD RESET ADDR
PAD7I
PAD6I
PAD5I
PAD4I FC3H
PAD3I
PAD2I
PAD1I
PAD0I
PADxI-Port Port Interrupt Request interrupt request pending GPIO Port Port interrupt request from GPIO Port Port awaiting service. where indicates specific GPIO Port number through each pin, only either Port Port enabled interrupts time. Port selection determined values Interrupt Port Select Register.
Interrupt Request Register
Interrupt Request (IRQ2) register (Table stores interrupt requests both vectored polled interrupts. When request presented interrupt controller, corresponding IRQ2 register becomes interrupts globally enabled (vectored interrupts), interrupt controller passes interrupt request CPU. interrupts globally disabled (polled interrupts), read Interrupt Request register determine interrupt requests pending.
Table Interrupt Request Register (IRQ2)
BITS FIELD RESET ADDR
U1RXI
U1TXI
DMAI FC6H
PC3I
PC2I
PC1I
PC0I
T3I-Timer Interrupt Request interrupt request pending Timer interrupt request from Timer awaiting service.
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Encore!® Series
U1RXI-UART Receive Interrupt Request interrupt request pending UART1 receiver. interrupt request from UART1 receiver awaiting service. U1TXI-UART Transmit Interrupt Request interrupt request pending UART transmitter. interrupt request from UART transmitter awaiting service. DMAI-DMA Interrupt Request interrupt request pending DMA. interrupt request from awaiting service. PCxI-Port Interrupt Request interrupt request pending GPIO Port interrupt request from GPIO Port awaiting service. where indicates specific GPIO Port number through
IRQ0 Enable High Registers
IRQ0 Enable High registers (Tables form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register. Table describes priority control IRQ0.
Table IRQ0 Enable Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
Table IRQ0 Enable High Register (IRQ0ENH)
BITS FIELD RESET ADDR
T2ENH
T1ENH
T0ENH
U0RENH FC1H
U0TENH
I2CENH
SPIENH
ADCENH
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T2ENH-Timer Interrupt Request Enable High T1ENH-Timer Interrupt Request Enable High T0ENH-Timer Interrupt Request Enable High U0RENH-UART Receive Interrupt Request Enable High U0TENH-UART Transmit Interrupt Request Enable High I2CENH-I2C Interrupt Request Enable High SPIENH-SPI Interrupt Request Enable High ADCENH-ADC Interrupt Request Enable High
Table IRQ0 Enable Register (IRQ0ENL)
BITS FIELD RESET ADDR
T2ENL
T1ENL
T0ENL
U0RENL FC2H
U0TENL
I2CENL
SPIENL
ADCENL
T2ENL-Timer Interrupt Request Enable T1ENL-Timer Interrupt Request Enable T0ENL-Timer Interrupt Request Enable U0RENL-UART Receive Interrupt Request Enable U0TENL-UART Transmit Interrupt Request Enable I2CENL-I2C Interrupt Request Enable SPIENL-SPI Interrupt Request Enable ADCENL-ADC Interrupt Request Enable
IRQ1 Enable High Registers
IRQ1 Enable High registers (Tables form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register. Table describes priority control IRQ1.
Table IRQ1 Enable Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
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Encore!® Series
Table IRQ1 Enable High Register (IRQ1ENH)
BITS
FIELD PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH RESET ADDR
FC4H
PADxENH-Port Port Bit[x] Interrupt Request Enable High Refer Interrupt Port Select register selection either Port Port interrupt source.
Table IRQ1 Enable Register (IRQ1ENL)
BITS FIELD RESET ADDR
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL FC5H
PADxENL-Port Port Bit[x] Interrupt Request Enable Refer Interrupt Port Select register selection either Port Port interrupt source.
IRQ2 Enable High Registers
IRQ2 Enable High registers (Tables form priority encoded enabling interrupts Interrupt Request register. Priority generated setting bits each register. Table describes priority control IRQ2.
Table IRQ2 Enable Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority Disabled Level Level Level Description Disabled Nominal High
where indicates register bits from through
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Table IRQ2 Enable High Register (IRQ2ENH)
BITS FIELD RESET ADDR
T3ENH
U1RENH
U1TENH
DMAENH FC7H
C3ENH
C2ENH
C1ENH
C0ENH
T3ENH-Timer Interrupt Request Enable High U1RENH-UART Receive Interrupt Request Enable High U1TENH-UART Transmit Interrupt Request Enable High DMAENH-DMA Interrupt Request Enable High C3ENH-Port Interrupt Request Enable High C2ENH-Port Interrupt Request Enable High C1ENH-Port Interrupt Request Enable High C0ENH-Port Interrupt Request Enable High
Table IRQ2 Enable Register (IRQ2ENL)
BITS FIELD RESET ADDR
T3ENL
U1RENL
U1TENL
DMAENL FC8H
C3ENL
C2ENL
C1ENL
C0ENL
T3ENL-Timer Interrupt Request Enable U1RENL-UART Receive Interrupt Request Enable U1TENL-UART Transmit Interrupt Request Enable DMAENL-DMA Interrupt Request Enable C3ENL-Port Interrupt Request Enable C2ENL-Port Interrupt Request Enable C1ENL-Port Interrupt Request Enable C0ENL-Port Interrupt Request Enable
Interrupt Edge Select Register
Interrupt Edge Select (IRQES) register (Table determines whether interrupt generated rising edge falling edge selected GPIO Port input pin.
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Interrupt Controller
Encore!® Series
Interrupt Port Select register selects between Port Port individual interrupts.
Table Interrupt Edge Select Register (IRQES)
BITS FIELD RESET ADDR
IES7
IES6
IES5
IES4 FCDH
IES3
IES2
IES1
IES0
IESx-Interrupt Edge Select minimum pulse width should greater than system clock guarantee capture edge triggered interrupt. Shorter pulses captured guaranteed. interrupt request generated falling edge PAx/PDx input. interrupt request generated rising edge PAx/PDx input. where indicates specific GPIO Port number through
Interrupt Port Select Register
Port Select (IRQPS) register (Table determines port that generates PAx/PDx interrupts. This register allows either Port Port pins used interrupts. Interrupt Edge Select register controls active interrupt edge.
Table Interrupt Port Select Register (IRQPS)
BITS FIELD RESET ADDR
PAD7S
PAD6S
PAD5S
PAD4S
PAD3S
PAD2S
PAD1S
PAD0S
FCEH PADxS-PAx/PDx Selection used interrupt PAx/PDx interrupt request. used interrupt PAx/PDx interrupt request. where indicates specific GPIO Port number through
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Encore!® Series
Interrupt Control Register
Interrupt Control (IRQCTL) register (Table contains master enable interrupts.
Table Interrupt Control Register (IRQCTL)
BITS FIELD RESET ADDR
IRQE
Reserved
FCFH
IRQE-Interrupt Request Enable This execution (Enable Interrupts) IRET (Interrupt Return) instruction, direct register write this bit. reset executing instruction, acknowledgement interrupt request, Reset. Interrupts disabled Interrupts enabled Reserved Must
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Interrupt Controller
Encore!® Series
Timers
Overview
Series products contain four 16-bit reloadable timers that used timing, event counting, generation pulse-width modulated (PWM) signals. timers' features include:
16-bit reload counter Programmable prescaler with prescale values from output generation Capture compare capability External input timer input, clock gating, capture signal. External input signal frequency limited maximum one-fourth system clock frequency. Timer output Timer interrupt
addition timers described this chapter, Baud Rate Generators unused UART, SPI, peripherals also used provide basic timing functionality. Refer respective serial communication peripheral chapters information using Baud Rate Generators timers. Timer unavailable 44-pin package devices.
Architecture
Figure illustrates architecture timers.
PS019913-0305
Preliminary
Timers
Encore!® Series
Timer Block Data Block Control Timer Control
Compare
16-Bit Reload Register
System Clock Timer Input Gate Input Capture Input
Interrupt, PWM, Timer Output Control
Timer Interrupt Timer Output
16-Bit Counter with Prescaler Compare
16-Bit Compare
Figure Timer Block Diagram
Operation
timers 16-bit up-counters. Minimum time-out delay loading value 0001H into Timer Reload High Byte registers setting prescale value Maximum time-out delay loading value 0000H into Timer Reload High Byte registers setting prescale value 128. Timer reaches FFFFH, timer rolls over 0000H continues counting.
Timer Operating Modes
timers configured operate following modes: ONE-SHOT Mode ONE-SHOT mode, timer counts 16-bit Reload value stored Timer Reload High Byte registers. timer input system clock. Upon reaching Reload value, timer generates interrupt count value Timer High Byte registers reset 0001H. Then, timer automatically disabled stops counting. Also, Timer Output alternate function enabled, Timer Output changes state system clock cycle (from High from High Low) upon timer Reload. desired have
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