Z380 Microprocessor PS010002-0708 Copyright ©2008 Zilog®, In
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Z380 Microprocessor
PS010002-0708
Copyright ©2008 Zilog®, Inc. rights reserved. www.zilog.com
Z380 Microprocessor
Warning: LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS PRIOR WRITTEN APPROVAL PRESIDENT GENERAL COUNSEL ZILOG CORPORATION. used herein Life support devices systems devices which intended surgical implant into body, support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness. Document Disclaimer ©2008 Zilog, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZILOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. information contained within this document been verified according general principles electrical mechanical engineering. Encore!, Encore! Encore! Crimzon, eZ80, ZNEO trademarks registered trademarks Zilog, Inc. other product service names property their respective owners.
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Z380 Microprocessor
Revision History
Each instance Revision History reflects change this document from previous revision. more details, refer corresponding pages appropriate links table below.
Date July 2008 March 2001
Revision Level
Description
Page
Updated format latest template Original Issue
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Revision History
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Z380 Microprocessor
FEATURES
Static CMOS Design with Low-Power Standby Mode Option 32-Bit Internal Data Paths Operating Frequency DC-to-18 DC-to-10 3.3V Enhanced Instruction that Maintains Object-Code Compatibility with Z80® Z180 Microprocessors 16-Bit (64K) 32-Bit (4G) Linear Address Space 16-Bit Data with Dynamic Sizing Two-Clock Cycle Instruction Execution Minimum Four Banks On-Chip Register Files Enhanced Interrupt Capabilities, Including 16-Bit Vector Undefined Opcode Trap Z380Instruction On-Chip Functions: Six-Memory Chip Selects with Programmable Waits Programmable Waits DRAM Refresh Controller 100-Pin Package
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Z380 Microprocessor
GENERAL DESCRIPTION
Z380 Microprocessor integrated high-performance microprocessor with fast efficient throughput increased memory addressing capabilities. Z380 offers continuing growth path present Z80-or Z180-based designs, while maintaining Z80® Z180 object-code compatibility. Z380 enhancements include improved CPU, expanded 4-Gbyte space flexible interface timing. enhanced version Z380 MPU. basic addressing modes microprocessor have been augmented follows: Stack Pointer Relative loads stores, 16-bit 24-bit indexed offsets, more flexible Indirect Register addressing, with addressing modes allowing access entire 32-bit address space. Additions made instruction set, include full complement 16-bit arithmetic logical operations, 16-bit operations, multiply divide, plus complete register-to-register loads exchanges. expanded basic register file microprocessor includes alternate register versions registers. There four sets this basic microprocessor register file present Z380 MPU, along with necessary resources manage switching between different register sets. register-pairs index registers basic microprocessor register file expanded bits. Z380 expands basic Kbyte Z180 address space full Gbyte (32-bit) address space. This address space linear completely accessible user program. address space similarly expanded full Gbyte (32-bit) range 16-bit I/O, both simple block move added. Some features that have traditionally been handled external peripheral devices have been incorporated design Z380 microprocessor. on-chip peripherals reduce system chip count reduce interconnection external bus. Z380 contains refresh controller DRAMs that employs /CAS-before-/RAS refresh cycle programmable rate burst size. programmable memory-chip selects available, along with programmable waitstate generators each chip-select address range. Z380 provides flexible interface timing, with separate control signals timing memory I/O. memory control signals provide timing references suitable direct interface DRAM, static RAM, EPROM, ROM. Full control memory timing possible because /WAIT signal sampled three times during memory transaction, allowing complete user control edge-to-edge timing between reference signals provided Z380 MPU. control signals allow direct interface members family peripherals, Z8000 family peripherals, Z8500 series peripherals. Figure shows Z380 block diagram; Figure shows assignments.
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Z380 Microprocessor
Note:
signals with preceding front slash, "/", active e.g., B//W (WORD active Low); active Low, only) Power connections follow conventional descriptions below:
Connection Power Ground Circuit Device
/LMCS/UMCS/MCS3-0
CNTLS
CNTLS
BUSCLK
CLKSEL
/STNBY
/RESET
Clock with Standby Control
External Interface Logic
Interrupts
Chip Selects Waits
Refresh Conrol
/INT3-0
/BREQ
/BACK
IOCLK
MSIZE
/HALT
CLKO
/WAIT
A31-0
D15-0
CLKI
/NMI
Data (16) Address (32)
Figure Z380 Functional Block Diagram
Figure Z380 Functional Block Diagram
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Z380 Microprocessor
/TREFR /TREFA /TREFC /BHEN /BLEN /MRD /MWR /MSIZE /WAIT BUSCLK IOCLK /IORQ /IORD CLKI CLKO /IOWR
Z380 100-Pin
Figure 100-Pin Assignments
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Z380 Microprocessor
DESCRIPTION
A31-A0 Address (outputs, activeHigh, tri-state).These non-multiplexed address signals provide linear memory address space four gigabytes. 32-address signals also used access devices. /BACK Acknowledge (output, active Low, tri-state). This signal, when asserted, indi-
cates that Z380 accepted external request tri-stated output drivers address bus, data control signals /TREFR, /TREFA, TREFC, /BHEN, /BLEN, /MRD, /MWR, /IORQ, /IORD, /IOWR. Note that Z380 cannot provide DRAM refresh transactions while acknowledge state.
/BHEN Byte High Enable (output, active Low, tri-state). This signal asserted beginning memory, refresh transaction indicate that operation D15-D8 requested. 16-bit memory transaction, /MSIZE asserted, indicating byte-wide memory, another memory transaction performed transfer data D15-D8, this time through D15-D8. /BLEN Byte Enable (output, active Low, tri-state). This signal asserted beginning memory refresh transaction indicate that operation D7-D0 requested. 16-bit memory transaction, /MSIZE asserted, indicating byte-wide memory, only data D7-D0 will transferred during this transaction, another transaction will performed transfer data D15-D8, this time through D7-D0. /BREQ Request (input, active Low). When this signal asserted, external
master requesting control bus. /BREQ higher priority than nonmaskable maskable interrupt requests.
BUSCLK Clock (output, active High, tri-state). This signal, output Z380 MPU, reference edge majority other signals generated Z380 MPU. BUSCLK delayed version input. CLKI Clock/Crystal (input, active High). externally generated direct clock input
this Z380 would operate CLKI frequency. Alternatively, crystal connected across CLKI CLKO, Z380 would operate half crystal frequency. clocking options controlled CLKsel input.
CLKO Crystal (output, active High). Crystal oscillator connection. This should left
open externally generated direct clock input CLKI pin.
CLKsel Clock Option Select (input, active High). This input should connected select direct clock option should connected crystal option. D15-D0 Data (input/outputs, active High, tri-state). This bi-directional 16-bit data
used data transfer between Z380 memory devices. Note that memory word transfer, even-addressed byte generally transferred D15-D8, odd-addressed byte D7-D0 (see /MSIZE description).
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Z380 Microprocessor
Evaluation Mode (input, active Low). This input should left unconnected nor-
operation. When driven logic Z380 conditions itself reset mode tri-states output drivers.
/HALT Halt Status (output, active Low, tri-state). Z380 standby mode option selected, Sleep instruction executed different than Halt instruction, HALT signal goes active indicate CPU's HALT state. standby mode option selected, this signal goes active only Halt instruction execution. /STNBY Standby Status (output, active Low, tri-state). Z380 standby mode
selected, executing sleep instruction stops clocking within Z380 BUSCLK IOCLK after which this signal asserted. Z380 then power standby mode, with operations suspended.
/INT3-0 Interrupt Requests (inputs, active Low). These signals four asynchronous maskable interrupt inputs. IOCLK Clock (output, active High, tri-state). This signal program controlled divided-down version BUSCLK. division factor two, four, eight with transactions interrupt-acknowledge transactions occurring relative IOCLK. /INTAK Interrupt Acknowledge Status (output, active Low, tri-state). This signal used
distinguish between interrupt acknowledge transactions. This signal High during read write transactions during interrupt acknowledge transactions.
/IORQ Input/Output Request (output, active Low, tri-state). This signal active during read write transactions interrupt acknowledge transactions. Machine Cycle (output, active Low, tri-state). This signal active during inter-
rupt acknowledge RETI transactions.
/IORD Input, Output Read Strobe (output, active Low, tri-state). This signal used strobe
data from peripherals during read transactions. addition, /IORD active during special RETI transaction heartbeat cycle protocol case.
/IOWR Input/Output Write Strobe (output, active Low, tri-state). This signal used strobe data into peripherals during write transactions. /LMCS Memory Chip Select (output, active Low, tri-state). This signal activated during memory read memory write transaction when accessing lower portion linear address space within first Mbytes, only this chip select function enabled. /MCS3-/MCS0 Mid-range Memory Chip Selects (output, active Low, tri-state). These sig-
nals individually active during memory read write transactions when accessing mid-range portions linear address space within first Mbytes. These signals individually enabled disabled.
/MRD Memory Read (output, active Low, tri-state). This signal indicates that
addressed memory location should place data data specified
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Z380 Microprocessor
BHEN /BLEN control signals. /MRD active from until during memory read transactions.
/MSIZE Memory Size (input, active Low). This input, from addressed memory location, indicates word size (logic High) byte size (logic Low). latter case, addressed memory should connected D15-D8 portion data bus, additional memory transaction will automatically generated complete word size data transfer. /MWR Memory Write (output, active Low, tri-state). This signal indicates that
addressed memory location should store data data bus, specified BHEN /BLEN control signals. /MWR active from until during memory write transactions.
/NMI Nonmaskable Interrupt(input, falling edge-triggered). This input higher priority
than maskable interrupt inputs /INT3-INT0.
/RESET Reset (input, active Low). This input must active minimum five BUSCLK periods initialize Z380 MPU. effect /RESET described detail Reset section. /TREFA Timing Reference (output, active Low, tri-state). This timing reference signal goes returns High during memory read, memory write refresh transaction. used control address multiplexer DRAM interface /RAS signal higher processor clock rates. /TREFC Timing Reference (output, activeLow, tri-state). This timing reference signal goes returns High during memory read, memory write refresh transaction. used /CAS signal DRAM accesses. /TREFR Timing Reference (output, active Low, tri-state). This timing reference signal goes returns High during memory read, memory write refresh transaction. used /RAS signal DRAM accesses. /UMCS Upper Memory ChipSelect (output, active Low, tri-state). This signal activated
during memory read, memory write, optionally refresh transaction when accessing highest portion linear address space within first Mbytes, only this chip select function enabled.
Power Supply. These eight pins carry power device. They must tied
same voltage externally.
Ground. These eight pins ground references device. They must tied same voltage externally. /WAIT Wait (input, active Low). This input sampled BUSCLK IOCLK, appropriate, insert Wait states into current transaction.
conditioning characteristics Z380 pins under various operation modes defined Table
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Z380 Microprocessor
Table Z380 Conditioning Characteristics Operation Mode Conditions
Names CLKI CLKO CLKSEL BUSCLK IOCLK A31-A0 D15-D0 /TREFR,/TREFA, /TREFC /MRD,/MWR /BHEN,/BLEN /LMCS,/UMCS, /MCS3-MCS0 /MSIZE,/WAIT /HALT,/STNBY /M1,/INTAK /IORQ,/IORD, /IOWR /BREQ /BACK /NMI,/INT3-/INT0 /RESET Normal /BREQ=1,/BACK=1, /EV=NC Input Output/No Connection Input Output Output Output Input/Output Output Output Output Output Input Output Output Output Input Output Input Input Connection Power Ground Relinquish /BREQ=0,/BACK=0, /EV=NC Input Output/No Connection Input Output Output Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Input Output Output Tri-state Input Output Input Input Connection Power Ground
Evaluation Input Connection Input Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Input Tri-state Tri-state Tri-state Input Tri-state Input Input Input Power Ground
EXTERNAL INTERFACE
kinds operations occur system bus: transactions requests. given time, device (either master) control known master. This section shows transaction request timing device. sake clarity, there more figures than actually necessary. This should reader rather than confuse. timing diagram figures, labelled STATUS encompasses /BHEN, /BLEN, chip select signals.
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Z380 Microprocessor
Transactions transaction initiated master responded some other device bus. Only transaction proceed time; kinds transactions occur: Memory, Refresh, I/O, Interrupt Acknowledge, RETI (Return from Interrupt), Halt. Z380 unique that memory transactions separate control signals. This allows memory interface optimized independently interface. Memory Transactions Memory transactions move instructions data from memory when Z380 performs memory access. Thus, they generated during program execution fetch instructions from memory fetch store memory data. They also generated store program status fetch program status during interrupt trap handling, used peripherals transfer information. memory transaction clock cycles long unless extended with wait states. Wait states inserted between each four states memory transaction BUSCLK cycle long wait state. external /WAIT input sampled only after internally-generated wait states inserted. Memory transactions transfer either bytes words. Z380 attempts transfer word byte-wide memory, /MSIZE signal should asserted force this transaction byte-wide dynamically. Z380 will then perform another memory transaction transfer byte that transferred during first transaction. Read memory transactions shown without wait states, with wait states between between between (Figures data driven memory being addressed, memory data latched immediately before rising edge BUSCLK which terminates
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Z380 Microprocessor
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Read Cycle, Waits
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Read Cycle, Wait
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Z380 Microprocessor
(Continued)
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Read Cycle, Wait
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Read Cycle, Wait
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Write memory transactions shown without wait states, with wait states between between between (Figures 7-10). /MWR strobe activated allow write data setup time memory since write data driven data beginning
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Write Cycle, Waits
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Write Cycle, Wait
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Write Cycle, Wait
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Write Cycle, Wait
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Refresh Transactions memory refresh transaction generated Z380 refresh controller occur immediately after final clock cycle other transaction. address during refresh transaction defined CAS-before-RASrefresh cycle assumed, which uses on-chip refresh address generator present DRAMs. Prior first refresh transaction, refresh setup cycle performed guarantee that /CAS precharge time met. This refresh setup cycle present only prior first refresh transaction burst (Figure 11). Refresh transactions shown without wait states, with wait states between between between (Figures 12-15). Note that during refresh cycle data continuously driven, /MRD /MWR remain inactive, /BHEN /BLEN active enable /CAS signals DRAMS, those Chip Select signals enabled DRAM refresh transactions active.
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Refresh Setup
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Z380 Microprocessor
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Refresh Cycle, Waits
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Refresh Cycle, Wait
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Refresh Cycle, Wait
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Refresh Cycle, Wait
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Z380 Microprocessor
Transactions transactions move data from external peripheral when Z380 performs access. transactions occur referenced IOCLK signal, when divided-down version BUSCLKsignal. BUSCLK divided factor from eight form IOCLK, under program control. example this division shown, four possible divisors, Figure Note that IOCLK divider synchronized (i.e., starts with known timing relationship) trailing edge /RESET. This discussed Reset Section.
BUSCLK
IOCLK (X2)
IOCLK (X4)
IOCLK (X6)
IOCLK (X8)
Figure IOCLK Timing
EXTERNAL INTERFACE (Continued)
Z380 unique that employs separate control signals accessing memory I/O. This allows interfaces optimized independent another. control signals allow direct connection members family peripherals Z8500 family peripherals. Note that because transactions start rising edge IOCLK, there BUSCLK cycles latency between execution unit request transaction transaction actually starting, where programmed clock divisor IOCLK. This implies that lowest possible divisor should always used IOCLK. transactions four IOCLK cycles long unless extended Wait states. Wait states inserted between third fourth IOCLK cycles transaction IOCLK cycle wait state. external /WAIT input sampled only after internally-generated wait states inserted.
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Z380 Microprocessor
Read transactions shown with without wait state (Figures 17-18). contents data latched immediately before falling edge IOCLK during last IOCLK cycle transaction.
IOCLK
ADDRESS
/WAIT
/IORQ
/IORD
/IOWR
/INTAK
Figure I/0Read Cycle, Waits
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Z380 Microprocessor
IOCLK
ADDRESS
/WAIT
/IORQ
/IORD
/IOWR /INTAK
Figure Read Cycle, Wait
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Write transactions shown with without wait state (Figures 19-20). data driven throughout transaction.
IOCLK
ADDRESS
/WAIT
/IORQ
/IORD /IOWR
/INTAK
Figure Write Cycle, Waits
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Z380 Microprocessor
ZILOG
MICROPROCE
IOCLK
ADDRESS
/WAIT
/IORQ
/IORD
/IOWR
/INTAK
Figure Write Cycle, Wait
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Interrupt Acknowledge Transactions interrupt acknowledge transaction generated Z380 response unmasked external interrupt request. Figure shows interrupt acknowledge transaction response /INT0 Figure shows interrupt acknowledge transaction response either /INT-3. Note that because transactions start rising edge IOCLK, there BUSCLK cycles latency between execution unit request transaction transaction actually starting (where programmed clock divisor IOCLK).
IOCLK
ADDRESS
DATA
/WAIT
/IORQ
/IORD
/IOWR
/INTAK
Figure Interrupt Acknowledge Cycle, /INT0
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Z380 Microprocessor
IOCLK
ADDRESS
/WAIT
/IORQ /IORD /IOWR /INTAK
Figure Interrupt Acknowledge Cycle, /INT3-1
interrupt acknowledge transaction /INT0 five IOCLK cycles long unless extended Wait states. /WAIT sampled separate points during transaction. /WAIT first sampled first IOCLK cycle during transaction. Wait states inserted here allow external daisy-chain between peripherals with longer time settle before interrupt vector requested. /WAIT then sampled fourth IOCLK cycle delay point which interrupt vector read Z380 MPU, after been requested. interrupt vector either eight sixteen bits, under program control, latched falling edge IOCLK last cycle interrupt acknowledge transaction. When using Mode interrupts, where Z380 fetches instruction from interrupting device, these fetches always eight bits wide transferred over D7-D0.
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Z380 Microprocessor
interrupt acknowledge transaction response /INT3-/INT1 also five IOCLK cycles long, unless extended wait states. waits sampled inserted similar locations interrupt acknowledge transaction /INT0. Note, however, only /INTAK signal active with /MI, /IORQ, /IORD /IOWR held inactive. either type INTACK transaction address driven with value which indicates type interrupt being acknowledged follows: A31-A6 one, A3-A0 except single zero corresponding maskable interrupt being acknowledged. Thus /INT3 acknowledge signaled being zero during interrupt acknowledge transaction, /INT2 acknowledge signalled being zero, etc. RETI Transactions RETI transaction generated whenever RETI instruction executed Z380 MPU. This transaction necessary because family peripherals designed watch instruction fetches take special action upon seeing RETI instruction (this only instruction that family peripherals watch for). Since Z380 fetches instructions using memory control signals, simulated RETI instruction fetch must placed with appropriate control signals. This shown Figure Again, note that because transactions start rising edge IOCLK, there BUSCLK cycles latency between execution unit request transaction transaction actually starting, where programmed clock divisor IOCLK.
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Z380 Microprocessor
IOCLK
ADDRESS
DATA
EDED
4D4D
/WAIT
/IORQ
/IORD
/IOWR
/INTAK
Figure Return From Interrupt Cycle
RETI transaction IOCLK cycles long unless extended Wait states, /WAIT sampled three separate points during transaction. /WAIT first sampled middle third IOCLK cycle allow longer/IORDLow-time requirements. /WAIT then sampled again during middle fifth IOCLK cycle allow longer internal daisy-chain settling time within peripheral. Wait states inserted here have effect separating what peripheral sees separate instruction fetch cycles. Finally, /WAIT sampled middle ninth IOCLK cycle, again allow longer /IORD Low-time requirements. Z380 drives data throughout RETI transaction, with EDEDH during first half transaction (the first byte RETI instruction EDH) with 4D4DH during second half transaction (the second byte RETI instruction 4DH).
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Z380 Microprocessor
HALT Transactions HALT transaction occurs whenever Z380 executes Halt instruction, with /HALT signal activated falling edge BUSCLK. standby mode enabled, executing Sleep instruction would also cause Halt transaction occur. While Halt state, Z380 continues drive address data buses, /HALT signal remains active until either interrupt request acknowledged reset received. Refresh transactions occur while halt state granted. timing entry into Halt state shown Figure while timing exiting from Halt state shown Figure
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/HALT
Figure HALT Entry
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Z380 Microprocessor
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/HALT /INT /NMI
Figure HALT Exit
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Z380 Microprocessor
Requests request initiated device that does have control bus. types request occur: request Interrupt request. When interrupt request made, answered according type. interrupt request, initiates interrupt acknowledge transaction requests, enters disconnect state, relinquishes bus, activates Acknowledge signal. Requests generate transactions bus, potential master (such controller) must gain control making request. request initiated driving /BREQ Low. Several requesters wired-OR /BREQ pin; priorities resolved externally CPU, usually priority daisy chain. asynchronous /BREQ signal generates internal /BUSREQ, which synchronous. /BREQ active beginning transaction, internal /BUSREQ causes /BACK signal asserted after current transaction completed. Z380 then enters Disconnect state gives control bus. Z380 control signals, except /BACK, /INTAK tri-stated. Note that release inhibited under program control allow Z380 exclusive access shared resource; this controlled SETC RESC instructions. Entry into Disconnect state shown Figure Z380 regains control after /BREQ deasserted. This shown Figure Interrupt Requests Z380 supports types interrupt requests, maskable /INT3-INT0 nonmaskable (/NMI). interrupt request line device that capable generating interrupt tied either /NMI maskable interrupt request lines, several devices connected interrupt request line with devices arranged priority daisy chain. However, because need family peripheral devices RETI instruction, only daisy chain Z80-family peripherals used. Z380 handles maskable nonmaskable interrupt requests somewhat differently, follows: High-to-Low transition /NMI input asynchronously edge-detected, internal latch set. beginning last clock cycle last internal machine cycle instruction, maskable interrupts sampled along with state latch. enabled maskable interrupt requested, next possible time (the next rising edge IOCLK) interrupt acknowledge transaction generated fetch interruptvector from interrupting device.For nonmaskable interrupt, interrupt acknowledge transaction generated; service routine always starts address 00000066H.
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Z380 Microprocessor
Transaction progress
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/BREQ
/BACK
/IORQ
/IORD
/IOWR
/INTAK
Figure Request/Acknowledge Cycle
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Z380 Microprocessor
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/BREQ /BACK
/IORQ
/IORD
/IOWR
/INTAK
Figure Request/Acknowledge Cycle
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Miscellaneous Timing There cases where specific transaction taking place which illustrated this section: idle cycle heartbeat cycle. Idle Cycles When transactions being performed bus, idle cycle occurs (Figure 16). control signals, both memory I/O, inactive during Idle cycle.
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure Idle Cycle
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Z380 Microprocessor
Heartbeat Cycle Z380 capable generating heartbeat cycle response write on-chip control register. This cycle most useful with family peripherals, where some members require transaction that looks like instruction fetch perform certain interrupt functions (Figure 29).
IOCLK
ADDRESS
Zeros
/WAIT
/IORQ
/IORD
/IOWR INTAK
Figure Heartbeat Cycle
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued)
Reset Timing timing entering exiting reset state shown Figures effects reset internal state Z380 detailed Reset section. synchronization IOCLK reset state shown Figure Note that IOCLK divisor maximum value (eight) /RESET only synchronized reset state.
Transaction progress BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/IOCTL3-0
/RESET
Figure Reset Entry
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Z380 Microprocessor
BUSCLK
ADDRESS
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/IOCTL3-0
/RESET
Figure Reset Exit
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Z380 Microprocessor
EXTERNAL INTERFACE (Continued
BUSCLK
/RESET
IOCLK
Figure IOCLK Reset Start-up
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Z380 Microprocessor
ARCHITECTURE
Central Processing Unit (CPU) Z380 binary-compatible extension Z180 architectures. High throughput rates Z380 achieved high clock rate, high bandwidth instruction fetch/execute overlap. Communicating external world through 8-or 16-bit data bus, Z380 full 32-bit machine internally, with 32-bit 32-bit registers. Modes Operation Z380 operate either Native Extended mode, controlled Select Register (SR). Native mode (the Reset configuration), address manipulations performed modulo 65536 bits). this mode Program Counter (PC) only increments across bits, address manipulation instructions (increment, decrement, add, subtract, indexed, stack relative, relative) only operate bits, Stack Pointer (SP) only increments decrements across bits. program counter highorder word left zeros, high-order words stack pointer register. Thus Native mode fully compatible with CPU's Kbyte address space. still possible address memory outside Kbyte address space data storage retrieved Native mode, however, direct addresses, indirect addresses, highorder word registers loaded with non-zero values. executed code interrupt service routines must reside lowest Kbytes address space. Extended mode, however, address manipulation instructions operate bits, allowing access entire Gbyte address space Z380 MPU. both Native Extended modes, Z380 drives bits address onto external address bus; only width manipulated addresses distinguish Native from Extended mode. Z380 implements instruction allow switching from Native Extended mode, once Extended mode, only Reset returns Z380 Native mode. This restriction applies because possibility "misplacing" interrupt service routines vector tables during translation from Extended mode back Native mode. addition Native Extended mode, which specific memory space addressing, Z380 operate either Word Long Word mode specific data load exchange operations. Word mode (the reset configuration), word load exchange operations manipulate 16-bit quantities. example, only low-order words source destination exchanged exchange operation, with high-order words unaffected. Long Word mode, bits source destination directives allow switching between Word Long Word mode; SETC (Set Control Long Word) RESC (Reset Control Long Word) perform global switch, while DDIR DDIR their variants decoder directives that select particular mode only instruction that they precede. Note that word data arithmetic opposed address manipulation arithmetic), rotate, shift logical operations always 16-bit quantities. They controlled either Native/Extended Word/Long Word selections. exceptions 16-bit
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Z380 Microprocessor
quantities are, course, those multiply divide operations with 32-bit products dividends. Lastly, word Input/Output operations performed 16-bit values. Address Spaces Z380 architecture supports five distinct address spaces corresponding different types locations that accessed CPU. These five address spaces are: register space, control register space, memory address space, address space (on-chip external). Register Space register space shown Figure consists registers register file. These registers used data address manipulation, extension register set, with four sets this extended register present Z380 CPU. Access these registers specified instruction, with active register selected bits Select Register (SR) control register space.
Sets Registers BCz' DEz' HLz' IXz' IYz' IXU' IYU' IXL' IYL'
Figure Register
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Z380 Microprocessor
Each register includes primary registers well alternate registers IX', IY'. These byte registers paired with with with with with with form word registers. These word registers extended bits with extension register. This register extension only accessible when using register 32-bit register (the Long Word mode) when swapping between most-significant least-significant word 32-bit register. Whenever instruction refers word register, implicit size controlled Word Long Word mode. Also included registers, well Control Register Space control register space consists 32-bit Select Register (SR), Figure accessed whole upper three bytes accessed individually YSR, XSR, DSR. addition, these upper three bytes loaded with same byte value. also PUSHed POPed cleared zeros Reset.
Reserved
IYBANK
Reserved
IXBANK
Reserved
MAINBANK
IEF1
Figure Select Register IYBANK Bank Select). This 2-bit field selects register used
registers. This field independently register selection other Z380 registers. Reset selects Bank IY'.
(IYPrime Register Select). This controls reports whether cur-
rently active register. selected when this cleared selected when this set. Reset clears this selects
IXBANK Bank Select). This 2-bit field selects register used
registers. This field independently register selection other Z380 registers. Reset selects Bank IX'.
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Z380 Microprocessor
(IXPrime Register Select). This controls reports whether cur-
rently active register. selected when this cleared selected when this set. Reset clears this selects
MAINBANK (Main Bank Select). This 2-bit field selects register used
BC', registers. This field independently register selection other Z380 registers. Reset selects Bank these registers.
(BC/DE/HL BC'/DE'/HL' Register Select). This controls reports whether
BC/DE/HL BC'/DE'/HL' currently active bank registers. BC/DE/HL selected when this cleared BC'/DE'/HL' selected when this set. Reset clears this bit, selecting BC/DE/HL.
(Extended Mode). This controls Extended/ Native mode selection Z380
CPU. This SETC instruction, once set, cleared only reset /RESET pin. When this set, Z380 Extended mode. Reset clears this Z380 Native mode.
(Long Word Mode). This controls Long Word/ Word mode selection
Z380 CPU. This SETC instruction cleared RESC instruction. When this set, Z380 Long Word mode; when this cleared, Z380 Word mode. Reset clears this bit. Note that individual instructions executed either Word Long Word load exchange mode, using DDIR DDIR decoder directives.
IEF1 (Interrupt Enable Flag). This master Interrupt Enable Z380 CPU. This instruction cleared instruction. When this set, interrupts enabled; when this cleared, interrupts disabled. Reset clears this bit. (Interrupt Mode). This 2-bit field controls interrupt mode /INT0 interrupt
request. These bits controlled instructions Reset clears both these bits, selecting Interrupt Mode
(Lock). This controls Lock/Unlock status Z380 CPU. This
SETC instruction cleared RESC instruction. When this set, requests accepted, providing exclusive access Z380 CPU. When this cleared Z380 will grant requests normal fashion. Reset clears this bit.
Prime Register Select). This controls reports whether currently active pair registers. selected when this cleared selected when this set. Reset clears this selects
Memory Address Space memory address space viewed string Gbyte numbered consecutively ascending order. 8-bit byte basic addressable element Z380 memory address space. However, there other addressable data elements; bits, 2-byte words, bytestrings, 4-byte words.
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Z380 Microprocessor
size data element being addressed depends instruction being executed well Word/Long Word mode. addressed specifying byte, within that byte. Bits numbered from right left, with least significant being (Figure 35). address multiple-byte entity same address byte with lowest memory address entity. Multiple-byte entities stored beginning with either even memory addresses. word (either 2-byte 4-byte entity) aligned address even; otherwise, unaligned. Multiple transactions, which required access multiple-byte entities, minimized alignment maintained. formats multiple-byte data types also shown Figure Note that when word stored memory, least significant byte precedes more significant byte word, architecture. Also, lower-addressed byte present upper byte external data bus.
Bits within byte:
16-bit word address Least Significant Byte Most Significant Byte Address Address
32-bit word address D7-0 (Least Significant Byte) D15-8 D23-16 D31-24 (Most Significant Byte) Address Address Address Address
Memory addresses: Even address (A0=0) Least Significant Byte
address (A0=1) Most Significant Byte
Figure Bit/Byte Ordering Conventions
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Z380 Microprocessor
ARCHITECTURE (Continued)
External Address Space External addresses generated instructions, except those reserved on-chip address space accesses, take variety forms (Table read write always transaction, regardless size type instruction. On-chip Address Space Z380 MPU's on-chip peripheral functions portion interrupt functions controlled several on-chip registers, which occupy On-chip Address Space. This on-chip address space accessed only with following reserved on-chip instructions.
OUT0 TSTIO
(n),
OTIM OTIMR OTDM OTDMR
When these instructions executed, Z380 outputs register address being accessed pseudo transaction BUSCLK cycles duration, with address signals A31-A8 zeros. pseudo transaction, control signals their inactive states.
Table External Addressing Options
Instruction dst,(C) dst,(n) INA(W) dst,(mn) DDIR INA(W) dst,(lmn) DDIR INA(W) dst,(klmn) Block Input (n),A (C),dst OUT0 (n),dst OUTA(W) (mn),dst DDIR OUTA(W) (lmn),dst DDIR OUTA(W) (klmn),dst Block output A31-A24 00000000 BC31-BC24 00000000 00000000 00000000 BC31-BC24 00000000 BC31-BC24 00000000 00000000 00000000 BC31-BC24 Address A23-A16 00000000 BC23-BC16 00000000 00000000 BC23-BC16 00000000 BC23-BC16 00000000 00000000 BC23-BC16 A15-A8 Contents BC15-BC8 00000000 BC15-BC8 Contents BC15-BC8 00000000 BC15-BC8 A7-A0 BC7-BC0 BC7-BC0 BC7-BC0 BC7-BC0
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Z380 Microprocessor
DATA TYPES
Z380 operate bits, Binary-Coded Decimal (BCD) digits bits), bytes bits), words bits bits), byte strings, word strings. Bits registers set, cleared, tested. digits, packed byte, manipulated with Decimal Adjust Accumulator instruction conjunction with binary addition subtraction) Rotate Digit instructions. Bytes operated 8-bit load, arithmetic, logical, shift rotate instructions. Words operated similar manner word load, arithmetic, logical, shift rotate instructions. Block move search operations manipulate byte strings word strings Kbytes words long. Block instructions have identical capabilities. Registers Z380 contains abundant register resources (Figure 33). given time, program immediate access both primary alternate registers selected register set. Changing register sets simple matter LDCTL instruction. Primary Working Registers working register divided into register files; primary file alternate (designated file. Each file contains 8-bit Accumulator (A), Flag register (F), general-purpose registers Only file active given time, although data inactive file still accessed. Upon reset, primary register file register active. Exchange instructions allow programmer exchange active file with inactive file. accumulator destination register 8-bit arithmetic logical operations. general-purpose registers paired (BC, HL), extended bits extension register, form three 32-bit general-purpose registers. register serves 16-bit 32-bit accumulator word operations. Flag Register Flag register contains flags that reset various operations. This register illustrated Figure various flags described below.
Figure Flag Register
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Z380 Microprocessor
Carry (C). This flag when instruction generates carry subtract instruction generates borrow. Certain logical, rotate shift instructions affect Carry flag. Add/Subtract (N). This flag used Decimal Adjust Accumulator instruction distinguish between subtract operations. flag subtract operations cleared operations. Parity/Overflow (P/V). During arithmetic operations this flag indicate two's
complement overflow. During logical rotate operations, this flag indicate even parity result cleared indicate parity.
Half Carry (H). This flag 8-bit arithmetic operation generates carry borrow
between bits 16-bit operation generates carry borrow between bits 32-bit operation generates carry borrow between bits This used correct result packed addition subtract operation.
Zero (Z). This flag result arithmetic logical operation zero. Sign (S). This flag stores state most significant accumulator.
Index Registers four index registers, IX', IY', each hold 32-bit base address that used Indexed addressing mode. Index registers also function general-purpose registers with upper lower byte lower bits being accessed individually. These byte registers called IXU, IXU', IXL' registers, IYU, IYU', IYL' registers. Interrupt Register Interrupt register used interrupt modes /INT0 generate 32-bit indirect address interrupt service routine. register supplies upper twentyfour sixteen bits indirect address interrupting peripheral supplies lower eight sixteen bits. Assigned Vectors mode /INT1-3 upper sixteen bits vector supplied register; bits 15-9 assigned vector base bits assigned vector unique each /INT1-3. Program Counter Program Counter (PC) used sequence through instructions currently executing program generate relative addresses. contains 32-bit address current instruction being fetched from memory. Native mode, effectively only bits long, carries from inhibited this mode. Extended mode, allowed increment across bits. Register register used general-purpose 8-bit read/write register. register associated with refresh controller contents changed only user.
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Z380 Microprocessor
Stack Pointer Stack Pointer (SP) used saving information when interrupt trap occurs supporting subroutine calls returns. Stack Pointer relative addressing allows parameter passing using Select Register Select Register (SR) controls register selection operating modes Z380 CPU. reserved bits future expansion; they will always read zeros should written with zeros future compatibility. shown Figure
Addressing Modes
Addressing modes used Z380 calculate effective address operand needed execution instruction. Seven addressing modes supported Z380 CPU. these seven, addition addressing modes (Stack Pointer Relative) remaining modes either existing extensions addressing modes.
Register. operand 8-bit registers IXU, IXL, IYU, IYL, L'); 16-bit 32-bit registers (BC, BC', DE', HL', IX', special registers Immediate. operand instruction itself effective address.
DDIR DDIR decoder directives allow specification 24-bit 32-bit immediate operands, respectively.
Indirect Register. contents register specify effective address operand. register primary register used memory accesses, also used. (For instruction, also used indirection.) register used space accesses. Direct Address. effective address operand location whose address
contained instruction. Depending instruction, operand either memory address space. Sixteen bits direct address norm, DDIR andDDIR decoder directives allow 24-bit 32-bit direct addresses, respectively.
Indexed. effective address operand location computed adding two's-complement signed displacement contained instruction contents register. Eight bits index norm, DDIR DDIR decoder directives allow 16-bit 24-bit indexes, respectively. Program Counter Relative. 16-or 24-bit displacement contained instruction added Program Counter generate effective address. This mode available only Jump Call instructions.
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Z380 Microprocessor
Stack Pointer Relative. effective address operand location computed
adding two's-complement signed displacement contained instruction contents Stack Pointer. Eight bits index norm, DDIR DDIR decoder directives allow 16-and 24-bit indexes, respectively.
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Z380 Microprocessor
INSTRUCTION
Z380 CPU's instruction superset CPU's; Z380 opcode compatible with CPU. Thus program executed Z380 without modification. instruction divided into seventeen groups function: instructions divided into following categories.
8-bit load group 16/32 load group Push/Pop group Exchanges, block transfers, searches 8-bit arithmetic logic operations General purpose arithmetic control Decoder Directive Instructions 16/32 arithmetic operations Multiply/Divide Instruction group 8-bit Rotates shifts 16-bit Rotates shifts 8-bit set, reset, test operations Jumps Calls, returns, restarts 8-bit input output operations External address space 8-bit input output operations Internal address space 16-bit input output operations
Instruction following summary Z380 instruction which shows assembly language mnemonic, operation, flag status, gives comments each instructions. Note: Mnemonic object code assignment newly added instructions (instructions Italic face) preliminary subject change without notice. Z380 Technical Manual will contain significantly more details programming use. list instructions, well encoding included Appendix this document.
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Z380 Microprocessor
Instruction Notation Symbols. following symbols used describe instruction set.
dd,qq,ss,tt,uu 8-bit constant 16-bit constant 8-bit offset. (2's complement) register 8-bit location addressing modes allowed particular instruction. 16-bit location addressing modes allowed particular instruction. Byte specified 16-bit location Byte specified 16-bit location Select Register Index register Index Register Extend (IXz IYz) Byte index register (IXU IYU) Byte index register (IXL IYL) Current Stack Pointer Port pointed register Condition Code Optional field Indirect Address Pointer Direct Address
INSTRUCTION (Continued)
Assignment value indicated symbol example,
indicates that source data added destination data result stored destination location. notation "dst (b)" used refer given location, "dst(m-n) used refer location destination. example, HL(7) specifies destination, HL(23-16) specifies location register.
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Z380 Microprocessor
Flags. register contains following flags followed symbols.
Sign flag Zero flag Half carry flag Parity/Overflow flag Add/Subtract flag Carry Flag flag affected according result operation.
flag unchanged operation. flag reset operation. flag operation. flag affected according overflow result operation. flag affected according parity result operation.
Condition Codes. following symbols describe condition codes.
Zero* Zero* Carry* carry* Sign Sign overflow Overflow Parity even Parity Positive Minus
*Abbreviated
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PS010002-0708
Z380 Microprocessor
Field Encoding convention opcode binary format shown following Tables. example, opcode format instruction (IX+12h), first find entry (XY+d),r. That entry opcode format
bottom each Table (between Table Notes), binary format following: r,r' Regs 0),IYU(x 0),IYL(x
form opcode first look field value register, which Then find field value register, which 001. Replace fields with value from table; replace value with real number. results are:
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Z380 Microprocessor
8-BIT LOAD GROUP
Symbolic Operation (HL) (XY+d) (HL) (XY+d) (HL) (XY+d) Flags Opcode Execute Bytes Time Notes
Mnemonic r,r' XYU,n XYL,n
r,(HL) r,(XY+d)
(HL),r (XY+d),r
(HL),n (XY+d),n
A,(BC) A,(DE) A,(nn)
(BC) (DE) (nn) (BC) (DE) (nn)
(BC),A (DE),A (nn),A
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Z380 Microprocessor
8-BIT LOAD GROUP (Continued)
Symbolic Operation Flags Opcode Execute Bytes Time Notes
Mnemonic XYU,s XYL,s s,XYU s,XYL
Regs 0),IYU(x 0),IYL(x
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions.
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16/32 LOAD GROUP
Symbolic Operation Flags Opcode Execute Bytes Time Notes L1,I
Mnemonic dd,nn
XY,nn
L1,I
HL,(nn)
(nn+1) (nn) (nn+1) (nn) (nn+1) (nn) (nn+1) (nn) (nn+1) (nn) (nn+1) (nn) (pp+1) (pp) (uu+1) (uu) (pp+1) (pp)
L1,I
dd,(nn)
L1,I
XY,(nn)
L1,I
(nn),HL
L1,I
(nn),dd
L1,I
(nn),XY
L1,I
W(pp),nn
L1,I
pp,(uu) (pp),uu SP,HL SP,XY pp,UU XY,pp IX,IY
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MICROPROCESSOR
16/32 LOAD GROUP (Continued)
Symbolic Operation (pp+1) (pp) (pp+1) (pp) (XY+d)h (XY+d)l (IY+d)h (IY+d)l (IX+d)h (IX+d)l (SP+d)h (SP+d)l (SP+d)h (SP+d)l (XY+d)h (XY+d)l (IX+d)h (IX+d)l (IY+d)h (IY+d)l Flags Opcode Execute Bytes Time Notes L1,I
Mnemonic IY,IX pp,XY (pp),XY XY,(pp) pp,(XY+d)
IX,(IY+d)
L1,I
IY,(IX+d)
L1,I
pp,(SP+d)
L1,I
XY,(SP+d)
(XY+d),pp
(IX+d),IY
(IY+d),IX
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Mnemonic (SP+d),pp
Symbolic Operation (SP+d)h (SP+d)l (SP+d)h (SP+d)l
Flags
Opcode
Execute Bytes Time Notes
(SP+d),XY
I,HL HL,I
Pair
Pair
pp,uu
Pair
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Long Word mode, this instruction loads bits; dst(31-0) src(31-0)
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PUSH/POP INSTRUCTIONS
Symbolic Operation (SP-2) (SP-1) SP-2 (SP-2) (SP-1) SP-2 (SP-2) (SP-1) SP-2 (SP-2) SR(7-0) (SP-1) SR(15-8) SP-2 (SP+1) (SP) SP+2 (SP+1) (SP) SP+2 SR(6-0) (SP) SR(15-8) (SP+1) SR(23-16) (SP+1) SR(31-24) (SP+1) SP+2 Flags Opcode Execute Bytes Time Notes N,L2,L4
Mnemonic PUSH
PUSH
PUSH
PUSH
L4,I
Pair
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Long Word mode, this instruction PUSHes register's extended portion (register with suffix) before pushing contents register stack. Long Word mode, this instruction POPs register's extended portion (register with suffix) after popping contents register stack. Long Word mode, PUSH PUSH instructions push 0000h onto stack place extended register portion. Long Word mode, instruction increments after POPing word data from stack. Long Word mode, this instruction POPs more word from stack loads into SR(31-16), instead duplicating (SP+1) location into SR(3116). Native mode, this instruction uses addresses modulo 65536. (10): case register pair, execute time clock less.
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EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS
Symbolic Operation SR(0) SR(0) DE(15-0) HL(15-0) BC(15-0) DE(15-0) BC(15-0) HL(15-0) SR(8) SR(8) (SP+1) (SP) (SP+1) (SP) (HL) pp(15-0) pp'(15-0) XY(15-0) XY'(15-0) pp(15-0) XY(15-0) IX(15-0) IY(15-0) SR(24) SR(24) SR(16) SR(16) SR(8) SR(8) SR(16) SR(16) SR(24) SR(24) pp(31-16) pp(15-0) XY(31-16) XY(15-0) (DE) (HL) DE+1 HL+1 BC(15-0) BC(15-0)-1 (DE) (HL) DE+1 HL+1 BC(15-0) BC(15-0)-1 Repeat until (DE) (HL) DE-1 HL-1 BC(15-0) BC(15-0)-1 Flags Opcode Execute Bytes Time Notes 3+r+w 3+r+w 3+r+w
Mnemonic DE,HL BC,DE BC,HL (SP),HL (SP),XY A,(HL) r,r' pp,pp'
XY,XY'
pp,XY IX,IY EXALL
EXXX EXXY SWAP SWAP
3+r+w
LDIR
(3+r+w)n
3+r+w
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EXCHANGE, BLOCK TRANSFER, BLOCK SEARCH GROUPS (Continued)
Symbolic Operation (DE) (HL) DE-1 HL-1 BC(15-0) BC(15-0)-1 Repeat until A-(HL) HL+1 BC(15-0) BC(15-0)-1 A-(HL) Flags Opcode Execute Bytes Time (3+r+w)n
Mnemonic LDDR
Notes
CPIR
CPDR
LDIW
LDIRW
HL+1 BC(15-0) BC(15-0)-1 Repeat until (HL) A-(HL) HL-1 BC(15-0) BC(15-0)-1 A-(HL) HL-1 BC(15-0) BC(15-0)-1 Repeat until (HL) (DE) (HL) (DE+1) (HL+1) DE+2 HL+2 BC(15-0) BC(15-0)-2 (DE) (HL) (DE+1) (HL+1) DE+2 HL+2 BC(15-0) BC(15-0)-2 Repeat until
(3+r)n
(3+r)n
(3+r+w)n N,L8(4)
(3+r+w)n N,L8(4)
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Mnemonic LDDW
Symbolic Operation
Flags
Opcode
Execute Bytes Time Notes 3+r+w N,L8(4)
LDDRW
(DE) (HL) (DE+1) (HL+1) DE-2 HL-2 BC(15-0) BC(15-0)-2 (DE) (HL) (DE+1) (HL+1) DE-2 HL-2 BC(15-0) BC(15-0)-2 Repeat until Regs
(3+r+w)nN,L8(4)
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. Long Word mode, this instruction exchanges 32-bits; src(31-0) dst(31-0) Long Word mode, this instruction transfers words modified instead Native mode, this instruction uses addresses modulo 65536.
(1): (2): (3): (4):
flag result BC-1 otherwise flag only completion instruction. Flag (HL), otherwise Source, Destination address, count value must even numbers.
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8-BIT ARITHMETIC LOGICAL GROUP
Symbolic Operation AA+r AA+n Flags Opcode Execute Bytes Time Notes
Mnemonic
(000) (000) A,(HL) (HL) (000) A,(XY+d) (000) A,XYU (000) A,XYL (000) (001) AA-s (010) (011) (100) (110) (101) (111) XYU, XYL, (HL), (IX+d), (IY+d) shown instruction. indicated bits replace (000) above. (100) (100) 2+r+w 4+r+w (100) (100) (100) mm-1 (101) XYU, XYL, (HL), (IX+d), (IY+d) shown instructions. indicated bits replace (100) with (101) operand. INCr (HL) (XY+d) rr+1 (HL) (HL)
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Mnemonic
Symbolic Operation
Flags
Opcode
Bytes
Execute Time Notes
(HL)
(HL)
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. (5): cycles execute Accumulator, three cycles execute other registers.
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GENERAL PURPOSE ARITHMETIC CONTROL GROUP
Symbolic Operation One's complement One's complement Two's complement 0-HL Two's complement 0000 H[7] FFFF H[7] Complement carry flag operation halted Sleep SR(5) IER(i) n(i) SR(5) n(0) SR(5) IER(i) n(i) SR(5) n(0) mode mode mode mode SR(31-24) SR(23-16) SR(15-8) SR(31-24) SR(23-16) SR(15-8) HL(15-0) SR(15-0) Flags Opcode Execute Bytes Time Notes
Mnemonic CPL[A] CPLW[HL] NEG[A] NEGW[HL] EXTS
EXTSW [HL] HALT
LDCTL SR,A
LDCTL SR,n
LDCTL HL,SR
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Mnemonic LDCTL SR,HL
Symbolic Operation
Flags
Opcode Bytes
Execute Time Notes
LDCTL LDCTL LDCTL
SR(15-8) HL(15-8) SR(0) HL(0) (LW) SR(31-16) HL(31-16) else SR(31-24) HL(15-8) SR(23-16) HL(15-8) SR(1) Lock mode SR(6) Long word mode SR(7) Extend mode SR(1) Reset Lock mode SR(6) Reset Long word mode Bank Test SR(16) SR(24) SR(0) SR(8) Mode test SR(7) SR(6) SR(1)
SETC SETC SETC RESC RESC BTEST
MTEST
Control Regs
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. Long Word mode, this instruction loads bits; dst(31-0) src(31-0) Long Word mode, this instruction operates 32-bits; A(7) then HL(31-16) 0000h else FFFFh Converts accumulator content into packed following subtract with packed operands. Interrupts sampled
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DECODER DIRECTIVE INSTRUCTIONS
Opcode Execute Time Notes
Mnemonic DDIR DDIR IB,W DDIR IW,W DDIR DDIR DDIR IB,LW DDIR IW,LW DDIR
Operation Operate following inst word mode. Operate following inst word mode. Fetching additional byte data. Operate following inst word mode. Fetching additional word data. Fetching additional byte data. Operate following inst Long Word mode. Operate following inst Long Word mode. Fetching additional byte data. Operate following inst word mode. Fetching additional word data. Fetching additional word data.
Bytes
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16/32 ARITHMETIC LOGICAL GROUP
Symbolic Operation Flags Opcode (000) Execute Bytes Time Notes
Mnemonic HL,dd HL,dd XY,qq XY,XY INC[W] INC[W] DEC[W] DEC[W] SP,nn
SP,nn
ADDW [HL,]pp
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16/32 ARITHMETIC LOGICAL GROUP (Continued)
Symbolic Operation Flags Opcode Execute Bytes Time Notes (000) (000) (000) (001) (010) (011) (100) (110) (101) (111)
Mnemonic ADDW [HL,]nn
ADDW [HL,]XY ADDW [HL,](XY+d)
HL+XY HL+(XY+d) HL+uu+CY HL-uu HL+(nn)
ADCW [HL,]uu SUBW [HL,]uu SBCW [HL,]uu ANDW [HL,]uu [HL,]uu XORW [HL,]uu [HL,]uu (nn)
(nn)
(nn)
(IX+d), (IY+d) shown ADDW instruction. indicated bits replace (000) above.
Pair
Pair
Pair
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Extend mode, this instruction operates 32-bits; src(31-0) src(31-0) dst(31-0)
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MULTIPLY/DIVIDE INSTRUCTION GROUP
Symbolic Operation HL(31-0) HL(15-0) pp(15-0) HL(31-0) HL(15-0) XY(15-0) HL(31-0) HL(15-0) Flags Opcode Execute Bytes Time Notes (010) (010) (010) (010) (011)
Mnemonic MULTW [HL,]pp
MULTW [HL,]XY
MULTW [HL,]nn
MULTW (XY+d)
HL(31-0) HL(15-0) (XY+d)
12+r
MULTUW
HL(31-0) HL(15-0)
MULTUW instructions, (nn), (XY+d) shown MULTW instruction with replacing (010) (010). Execute time time required MUTW with more clock.
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MULTIPLY/DIVIDE INSTRUCTION GROUP (Continued)
Symbolic Operation HL(15-0) HL(31-0)/pp HL(31-16) remainder HL(15-0) HL(31-0)/XY HL(31-16) remainder HL(15-0) HL(31-0)/nn HL(31-16) remainder Flags Opcode Execute Bytes Time Notes
Mnemonic DIVUW [HL,]pp
DIVUW [HL,]XY
DIVUW [HL,]nn
DIVUW [HL,](XY+d) HL(15-0) HL(31-0)/(XY+d) HL(31-16) remainder
22+r
Regs
Regs
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions.
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8-BIT ROTATE SHIFT GROUP
Symbolic Operation Rotate Left Circular Accumulator Rotate Left Accumulator Rotate Right Circular Accumulator Rotate Right Accumulator Rotate Left Circular register Rotate Left Circular Flags Opcode Execute Bytes Time Notes
Mnemonic RLCA RRCA
(000) (HL) (000) (XY+d) Rotate Left Circular (000) Rotate Left (010) Rotate Right Circular (001) Rotate Right (011) Shift Left Arithmetic (100) Shift Right Arithmetic (101) Shift Right Logical (111) Above instruction's format states shown RLC's. form opcode replace (000) RLCs with shown code. Rotate Left Digit between accumulator location (HL) Rotate Right Digit between accumulator location (HL) Regs
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. (6): contents upper half accumulator unaffected.
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16/32 ROTATE SHIFT GROUP
Symbolic Operation Rotate Left Circular Flags Opcode Bytes Execute Time Notes
Mnemonic RLCW
RLCW
Rotate Left Circular
RLCW (HL)
Rotate Left Circular
RLCW (XY+d)
Rotate Left Circular
Rotate Left RRCW Rotate Right Circular Rotate Right SLAW Shift Left Arithmetic SRAW Shift Right Arithmetic SRLW Shift Right Logical Instruction format states shown RLCW.
(000) (000) (000) (000) (010) (001) (011) (100) (101) (111) form opcode replace (000) RLCW with shown code.
Regs
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions.
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8-BIT SET, RESET, TEST GROUP
Symbolic Operation (HL)b (XY+d)b Flags Opcode Execute Bytes Time Notes
Mnemonic b,(HL) b,(XY+d)
b,(HL) b,(XY+d)
(HL)b (XY+d)b
(11) (11) (11) (10)
form opcode replace (11) with (10). r,(HL), (XY+d). notation indicates location b(0~7)
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction operate with DDIR Immediate instructions.
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JUMP GROUP
Symbolic Operation PC(15-0) PC(15-0) HL(15-0) PC(15-0) XY(15-0) condition true then otherwise continue continue continue continue continue Flags Opcode (ee-4)L (ee-4)H (ee-4)L (ee-4)H (ee-4)L (ee-4)H (ee-4)L (ee-4)H (ee-4)L (ee-4)H (eee-5)L (eee-5)M (eee-5)H (eee-5)L (eee-5)M (eee-5)H Execute Bytes Time Notes
Mnemonic
(HL) (XY) cc,nn
NC,e NZ,e
C,ee
continue
NC,ee
continue
Z,ee
continue
NZ,ee
continue
C,eee
continue
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Mnemonic NC,eee
Symbolic Operation continue
Flags
Opcode (eee-5)L (eee-5)M (eee-5)H (eee-5)L (eee-5)M (eee-5)H (eee-5)L (eee-5)M (eee-5)H (ee-4)L (ee-4)H (eee-5)L (eee-5)M (eee-5)H
Execute Bytes Time Notes
Z,eee
continue
NZ,eee
continue
DJNZ
DJNZ
BB-1 continue BB-1 continue BB-1 continue
DJNZ
Condition (Non-zero) (Zero) (Non-carry) (Carry) (Parity Odd), (Non-Overflow) (Parity Even), (Overflow) (Sign positive), sign) (Sign negative), (Sign)
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Native mode, this instruction uses addresses modulo 65536. Extend mode, this instruction loads 31-16 portion operand into PC(31-16). (7): signed two's complement number range [-126, 129], opcode provides effective address pc+e incremented prior addition (8): signed two's complement number range [-32765, 32770], ee-4 opcode provides effective address pc+e incremented prior addition (9): signed two's complement number range [-8388604, 8388611], eee-5 opcode provides effective address pc+e incremented prior addition
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CALL RETURN GROUP
Symbolic Operation (SP-1) (SP-2) SP-2 condition false continue otherwise same CALL (SP-1) (SP-2) SP-2 condition false continue otherwise same CALR (SP-1) (SP-2) SP-2 condition false continue otherwise same CALR (SP-1) (SP-2) SP-2 condition false continue otherwise same CALR (SP) SP+2 condition false continue otherwise same Return from Interrupt Flags Opcode Execute Bytes Time Notes (ee-4)L (ee-4)H (ee-4)L (ee-4)H (eee-5)L (eee-5)M (eee-5)H (eee-5)L (eee-5)M (eee-5)H
Mnemonic CALL
CALL cc,nn
2/4+w
CALR
N,X3,(11)
CALR cc,e
2/4+w N,X3,(11)
CALR
N,X3,(8)
CALR cc,ee
2/4+w N,X3,(8)
CALR
N,X3,(9)
CALR cc,eee
2/4+w N,X3,(9)
2/2+r
RETI
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Mnemonic RETN
Symbolic Operation Return from (SP-1) (SP-2) SP-2
Flags
Opcode
Bytes
Execute Time
Notes N,X4,(10) N,X3,X5
Condition (Non-zero) (Zero) (Non-carry) (Carry) (Parity Odd), (Non-Overflow) (Parity Even), (Overflow) (Sign positive), sign) (Sign negative), (Sign)
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. (8): (9): (10) (11): This instruction used with DDIR Immediate instructions. Native mode, this instruction uses addresses modulo 65536. Extended mode, this instruction pushes PC(31-16) into stack before pushing PC(15-0) into stack. Extended mode, this instruction pops PC(31-16) from stack after poping PC(15-0) from stack. Extended mode, this instruction loads into PC(31-16). Extended mode, return instructions pops from stack after poping from stack. signed two's complement number range [-32765, 32770], ee-4 opcode provides effective address pc+e incremented prior addition signed two's complement number range [-8388604, 8388611], eee-5 opcode provides effective address pc+e incremented prior addition RETN loads IFF2 IFF1. signed two's complement number range [-127, 128], opcode provides effective address pc+e incremented prior addition
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8-BIT INPUT OUTPUT GROUP
Symbolic Operation (nn) Flags Opcode Execute Bytes Time Notes
Mnemonic A,(n) r,(C) A,(nn)
INIR
INDR
(n),A (C),r (C),n
(HL) BB-1 (HL) Repeat until (HL) BB-1 (HL) Repeat until (nn)
2+i+w
(2+i+w)
2+i+w
(2+i+w)n
OUTA (nn),A
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Mnemonic OUTI
Symbolic Operation (HL) (HL) Repeat until (HL) Repeat until (HL) Repeat until
Flags
Opcode
Execute Bytes Time Notes 2+r+o
OTIR
2+r+o
OUTD
2+r+o
OTDR
2+r+o
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Native mode, this instruction address modulo 65536. (1): flag result BC-1 otherwise (2): flag only completion instruction.
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INPUT OUTPUT INSTRUCTIONS ON-CHIP SPACE
Symbolic Operation Changes Flag only. Flags Opcode Execute Bytes Time Notes
Mnemonic r,(n)
OUT0 (n),r
TSTIO
(HL) BB-1 (HL) CC+1 Repeat until (HL) CC-1 BB-1 (HL) CC-1 BB-1 Repeat until
OTIIM
2+r+o
(3),N
OTIIMR
2+r+o
(3),N
OTDM
2+r+o
(3),N
OTDMR
2+r+o
(3),N
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Native mode, this instruction address modulo 65536. (1): flag result BC-1 otherwise (2): flag only completion instruction.
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16-BIT INPUT OUTPUT GROUP
Symbolic Operation HL(15-0) (nn) Flags Opcode Execute Bytes Time Notes
Mnemonic pp,(C) INAW HL,(nn)
INIW
INIRW
INDW
INDRW
OUTW (C),pp OUTW (C),nn
(HL) (DE) BC(15-0) BC(15-0) HL+2 (HL) (DE) BC(15-0) BC(15-0) HL+2 Repeat until (HL) (DE) BC(15-0) BC(15-0) (HL) (DE) BC(15-0) BC(15-0) Repeat until
2+i+w
(2+i+w)n
2+i+w
(2+i+w)n
OUTAW (nn),HL
(nn) HL(15-0)
OUTIW
OTIRW
(DE) (HL) BC(15-0) BC(15-0) BC(15-0) BC(15-0) (DE) (HL) Repeat until
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16-BIT INPUT OUTPUT GROUP (Continued)
Symbolic Operation BC(15-0) BC(15-0) (DE) (HL) BC(15-0) BC(15-0) (DE) (HL) Repeat until Flags Opcode Execute Bytes Time Notes 2+r+o
Mnemonic OUTDW
OTDRW
2+r+o
Notes: Instructions Italic face Z380 instructions, instructions with underline Z180 original instructions. This instruction used with DDIR Immediate instructions. Native mode, this instruction uses addresses modulo 65536. result zero, flag set; otherwise reset. flag upon instruction completion only.
Instruction dst,(C) INA(W) dst,(mn) DDIR INA(W) dst,(lmn) DDIR INA(W) dst,(klmn) Block Input (n),A (C),dst OUTA(W) (mn),dst DDIR OUTA(W) (lmn),dst DDIR OUTA(W) (klmn),dst Block output
A31-A24 00000000 BC31-BC24 00000000 00000000 BBC31-BC24 00000000 BC31-BC24 00000000 00000000 BC31-BC24
Address A23-A16 00000000 BC23-BC16 00000000 BC23-BC16 00000000 BC23-BC16 00000000 BC23-BC16
A15-A8 Contents BC15-BC8 BC15-BC8 Contents BC15-BC8 BC15-BC8
A7-A0 BC7-BC0 BC7-BC0 BC7-BC0 BC7-BC0
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INTERRUPTS
Z380 MPU's interrupt structure provides compatibility with existing Z180 MPUs with following exception: undefined opcode trap's occurrence with respect Z380 instruction set, response improved Z180) make trap handling easier. Z380 also offers additional features enhance flexibility system design. five external interrupt inputs provided, /NMI nonmaskable interrupt. remaining inputs, /INT3-/INT0, four asynchronous maskable interrupt requests. Interrupt Acknowledge transaction, address outputs A31-A0 driven logic 1's. output among A3-A0 driven logic indicate maskable interrupt request being acknowledged. /INT0 being acknowledged, A3-A1, logic logic Interrupt modes through supported external maskable interrupt request /INT0. Modes have same schemes those Z180 MPUs. Mode similar mode except that 16-bit interrupt vectors expected from devices. Note that 8-bit 16-bit devices intermixed this mode having external pull resistors data signals D15-D8, example. external maskable interrupt requests /INT3-/INT1 handled assigned interrupt vectors mode. discussed Architecture section, Z380 operate either Native Extended Mode. Native Mode, PUSHing POPing stack save retrieve interrupted values interrupt handling done 16-bit sizes, stack pointer rolls over Kbyte boundary. Extended Mode, PUSHes POPs done 32-bit sizes, stack pointer rolls over Gbyte memory space boundary. Z380 provides Interrupt Register Extension, whose contents always outputted address signals A31-A16 when fetching starting addresses service routines from memory interrupt modes assigned vectors mode. Native Mode, such fetches automatically done 16-bit sizes Extended Mode, 32-bit sizes. These starting addresses should evenaligned memory locations. That their least significant bytes should have addresses with
Interrupt Priority Ranking
Z380 assigns fixed priority ranking handle interrupt sources, shown Table Table Interrupt Priority Ranking Priority Highest Lowest Interrupt Sources Trap (undefined opcode) /NMI /INT0 /INT1 /INT2 /INT3
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Interrupt Control
Z380 MPU's flags registers associated with interrupt processing listed Table discussed Architecture section, some registers reside on-chip address space accessed only with reserved on-chip instructions.
Table Interrupt Flags Registers Names Interrupt Enable Flags Interrupt Register Interrupt Register Extension Interrupt Enable Register Assigned Vectors Base Register Trap Break Register Mnemonics IEF1, IEF2 AVBR TRPBK Access Methods instructions instructions I,HL HL,I instructions (accessing both On-chip instructions, addr 00000017H, instructions On-chip instructions, addr 00000018H On-chip instructions, addr 00000019H
IEF1, IEF2
IEF1 controls overall enabling disabling onchip peripheral external maskable interrupt requests. IEF1 logic such interrupts disabled. purpose IEF2 correctly manage occurrence /NMI. When /NMI acknowledged, state IEF1 copied IEF2 then IEF1 cleared logic /NMI interrupt service routine, execution Return From Nonmaskable Interrupt instruction, RETN, automatically copies state IEF2 back IEF1. This means restore interrupt enable condition existing before occurrence /NMI. Table summarizes states IEF1 IEF2 resulting from various operations.
Table Operation Effects IEF1 IEF2 Operation /RESET Trap /NMI RETN /INT3-/INT0 RETI HL,I
Note: Change
IEF1 IEF2
IEF2 IEF1
Comments Inhibits interrupts except Trap /NMI. Disables interrupt nesting. IEF1 value copied IEF2, then IEF1 cleared. Returns from /NMI service routine. Disables interrupt nesting. Returns from service routine, device. Returns from service routine, non-Z80 device.
IEF2 value copied Flag.
Extend
8-bit Interrupt Register 16-bit Interrupt Register Extension cleared during reset.
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Interrupt Enable Register
IE3-IE0 (Interrupt Request Enable Flags). These flags individually indicate /INT3, /INT2, /INT1 /INT0 enabled. Note that these flags conditioned with enable disable interrupt instructions (with arguments).
IER: 00000017H Read Only Reset Value
Reserved bits 7-4. Read should write
Encoded Interrupt Requests Interrupt Requests Enable
Figure Interrupt Enable Register
Assigned Vectors Base Register
AB15-AB9 (Assigned Vectors Base). Interrupt Register Extension, together with AB15-AB9, define base address assigned interrupt vectors table memory space (Figure 26).
AVBR: 00000018H AB15 AB14 AB13 AB12 AB11 AB10 Reset Value Reserved Program Read Assigned Vectors Base
Reserved Read should write
Figure Assigned Vectors Base Register
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Trap Break Register
Reserved bits 7-2. Some these bits reserved breakpoint functions, including Break-on-Halt feature.
TRPBK: 00000019H
Refer Z380 specifications details. Read should write
Reset Value Trap Interrupt Vector Trap Instruction Fetch Reserved Program Read
Figure Trap Break Register
(Trap Instruction Fetch). goes active logic when undefined opcode fetched instruction stream detected. reset under program control writing with logic However, cannot written with logic
(Trap Interrupt Vector). goes active logic when undefined opcode returned vector interrupt acknowledge transaction mode reset under program control writing with logic However, cannot written with logic
Trap Interrupt
Z380 generates trap when undefined opcode encountered. trap enabled immediately after reset, maskable. This feature used increase software reliability implement extended instructions. undefined opcode fetched from instruction stream, returned vector interrupt acknowledge transaction interrupt mode When trap occurs, Z380 operates follows. Assigned Vectors Base Trap Register goes active, indicate source undefined opcode. undefined opcode fetched from instruction stream, starting address trap causing instruction pushed onto stack. (Note that starting address decoder directive preceding instruction encoding considered starting address instruction.) undefined opcode returned interrupt vector interrupt mode interrupted value pushed onto stack. states IEF1 IEF2 cleared. Z380 commences fetch execute instructions from address 00000000H. Note that instruction execution resumes address similar occurrence reset. Testing bits Assigned Vectors Base Trap Register will distinguish events. Even trap handling place, repeated restarts from address indicator possible illegal instructions system debugging.
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Nonmaskable Interrupt
nonmaskable interrupt input /NMI edge sensitive, with Z380 internally latching occurrence falling edge. When latched version /NMI recognized, following operations performed. interrupted (Program Counter) value pushed onto stack. state IEF1 copied IEF2, then IEF1 cleared. Z380 commences fetch execute instructions from address 00000066H.
Interrupt Mode Response Maskable interrupt /INT0
During interrupt acknowledge transaction, external device being acknowledged expected output vector onto lower portion data bus, D7-D0. interrupted value PUSHed onto stack IEF1 IEF2 reset logic disable further maskable interrupt requests. Z380 then reads entry from table residing memory loads into resume execution. address table entry composed Extend contents A31-A16, Register contents A15-A8 vector supplied device A7-A0. Note that table entry effectively starting address interrupt service routine designed device being acknowledged. table, composed starting addresses interrupt mode service routines, referred interrupt mode vector table. Each table entry should word-sized Z380 Native Mode longword-sized Extended Mode, either case even-aligned (least significant byte with address
Interrupt Mode Response Maskable Interrupt /INT0
During interrupt acknowledge transaction, external device being acknowledged expected output vector onto lower portion data bus, D7-D0. Z380 interprets vector instruction opcode, which usually single-byte Restart (RST) instructions that pushes interrupted (Program Counter) value onto stack resumes execution fixed memory location. However, Z380 will generate multiple transactions capture vectors that form multi-byte instruction. IEF1 IEF2 reset logic 0's, disabling further maskable interrupt requests. Note that unlike other interrupt responses, automatically PUSHed onto stack. Note also that trap occurs undefined opcode supplied device vector.
Interrupt Mode Response Maskable Interrupt /INT0
Interrupt mode similar mode except that 16-bit vector expected placed data D15-D0 device during interrupt acknowledge transaction. interrupted PUSHed onto stack. IEF1 IEF2 reset logic disable further maskable interrupt requests. starting address service routine fetched loaded into resume execution from memory location with address composed Extend contents A31-A16 vector supplied device A15-A0. Again starting address service routine word-sized Z380 Native Mode longword-sized Extend Mode, either case even-aligned.
Interrupt Mode Response Maskable Interrupt /INT0
interrupt acknowledge transaction generated, during which data contents ignored Z380 MPU. interrupted value PUSHed onto stack. IEF1 IEF2 reset logic disable further maskable interrupt requests. Instruction fetching execution restarts memory location 00000038H.
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Assigned Interrupt Vectors Mode Maskable interrupt INT3-/INT1
When Z380 recognizes external maskable interrupts generates Interrupt Acknowledge transaction which different than that /INT0. Interrupt Acknowledge transaction /INT3-/INT1 signal /INTAK active, with /MI, /IORQ, /IORD and/ IOWR inactive. interrupted value PUSHed onto stack. IEF1 IEF2 reset logic disabling further maskable interrupt requests. starting address interrupt service routine fetched from table entry loaded into resume execution. address table entry composed Extend contents A31-A16, bits Assigned Vectors Base Register A15-A9 assigned interrupt vector specific request being recognized A8-A0. assigned vectors defined Table Table Assigned Interrupt Vectors Interrupt Source /INT1 /INT2 /INT3 Assigned Interrupt Vector
RETI Instruction
family devices designed monitor Return from Interrupt opcodes instruction stream (RETI-EDH, 4DH), signifying current interrupt service routine. When detected, daisy chain within among device(s) resolves appropriate interrupt-under-service condition clears. Z380 reproduces opcode fetch transactions when RETI instruction executed. Note that Z380 outputs RETI opcodes onto both portions data (D15-D8 D7-D0) transactions.
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ON-CHIP PERIPHERAL FUNCTIONS
Z380 incorporates number functions ease interface with external devices with various types memories. Z380 MPU's programmed slower rate than memory bus. addition, heartbeat transaction generated that emulates instruction fetch cycle. Such transaction useful particular family device perform interrupt functions. Memory chip select signals activated access lowest Mbytes Z380 MPU's memory address space, with wait state insertions. Lastly, DRAM refresh function incorporated, with programmable refresh transaction burst size. above functions controlled several onchip registers. described Architecture section, these registers together with several other registers that control portion interrupt functions, occupy on-chip address space. This on-chip address accessed only following reserved on-chip instructions. Some on-chip peripherals capable generating interrupt requests, which always handled assigned interrupt vectors mode. OUT0 TSTIO (n), OTIM OTIMR OTDM OTDMR
When above instructions executed, Z380 outputs register address being accessed pseudo transaction BUSCLK cycles duration, with address signals A31-A8 logic pseudo transaction, control signals their inactive states. emphasized that Z380 adopts instruction specific scheme access on-chip registers, with their unique address space. This contrast mapping such registers with external peripherals common address space, done Z180 MPU.
Control Register
CR2-CR0 (I/O Clock Rate). BUSCLK divided down produce IOCLK defined following. divided-by-8 divided-by-2 divided-by-4 divided-by-6 divided-by-1 divided-by-1 divided-by-1 divided-by-1
Control
Z380 designed interface easily with external devices that either Z8500 product family supplying five control signals: /M1, /IORQ, /IORD, /IOWR /INTAK. addition, Z380 supplying IOCLK that divided down version BUSCLK. Programmable wait states inserted various transactions. External Interface section details transactions.
Note that clock divide rate specified, BUSCLK should used connect devices that require clock input, since Z380 outputs constant logic IOCLK. Reserved bits 7-3. Read should write
IOCR0: 00000011H
Reset Value Clock Reserved Program Read
Figure Control Register
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Control Register
When this phantom register IOCR1 with address 00000012H accessed with on-chip write instructions, heartbeat transaction that emulates instruction fetch performed bus. This transaction provides pulse which necessary part interrupt enable sequence product. on-chip write instruction, data being "written" value. case on-chip read with IOCR1 address, data returned unpredictable. states also inserted each opcode fetch transactions Return from Interrupt (RETI) instruction reproduced bus. When programmed with waits disabled. RTW1-RTW0 (RETI Waits). This binary field defines three wait states inserted between opcode fetch transactions Return from Interrupt instruction reproduced bus. DCW2-DCW0 (Interrupt Daisy Chain Waits). This binary field defines seven wait states inserted early portions interrupt acknowledge transactions, interrupt daisy chain through external devices settle.
Waits Register
OW2-IOW0 (I/O Waits). This binary field defines seven wait states inserted external read write transactions, latter portions interrupt transactions capture interrupt vectors. defined wait
IOWR: 0000000EH
IOW2 IOW1 IOW0 RTW1 RTW0 DCW2 DCW1 DCW0
Reset Value Interrupt Daisy Chain Waits Waits Waits
Figure Waits Register
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MEMORY CHIP SELECTS WAITS
Z380 offers schemes generate chip select signals access lowest Mbytes memory address space. first scheme provides chip select signals, with address space partitioned shown Figure second scheme provides three chip select signals, address space partitioning shown Figure Note that /MCS0 signal used indicate accesses entire mid-range memory second scheme. flexible wait state insertion scheme incorporated chip select logic. user program waits separately accesses lower, upper mid-range memory areas. chip select scheme effect, different wait states defined each midrange memory areas through
00FFFFFF
/UMCS
Upper Memory
00FFFFFF /UMCS Upper Memory
Unused
/MCS3
Mid-range Memory3 Mid-range Memory2 Mid-range Memory1 Mid-range Memory0
/MCS
Mid-range Memory
/MCS2
/MCS1
/MCS0
/LMCS
Lower Memory
Unused
00000000 Memory Chip Select Scheme
/LMCS 00000000
Lower Memory
Figure Chip Select Address Space
Memory Chip Select Scheme
Figure Chip Select Address Space
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Lower Memory Chip Select Control
This memory area lower boundary address 000000000H. user define size integer power two, starting Kbytes. example, lower memory area either Kbytes, Kbytes, Kbytes, etc., starting from address /LMCS signal enabled active during refresh transactions.
Lower Memory Chip Select Register
MA23-MA16 (Match Address Bits 23-16). match address logic corresponding address signal memory transaction compared logic condition /LMCS become active. match address logic corresponding address signal compared (don't care). example, MA23 determines should tested logic memory transactions. Note that order /LMCS active memory transaction, /LMCS function enabled Memory Selects Master Enable Register (described later), address signals A31-A24 logic address signals A23-A12 programmed address matching above registers have logic define lower memory area Kbytes, MA23-MA12 should programmed with area larger than Kbytes, MA23-MA12 that order) should programmed with contiguous followed contiguous This intended usage maintain lower memory area single block. Note also that /LMCS enabled refresh transactions independent value programmed into Memory Selects Master Enable Register.
LMCSR1: 00000001H
Lower Memory Chip Select Register
MA15-MA12 (Match Address Bits 15-12). match address logic corresponding address signal memory transaction compared logic condition /LMCS become active. match address logic corresponding address signal compared (don't care). example, MA12 determines should tested logic memory transactions. Reserved bits 3-1. Read should write (Enable Refresh transactions). this programmed logic one, /LMCS goes active during refresh transactions.
LMCSR0: 00000000H
MA15 MA14 MA13 MA12 -ERF
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16
Reset Value Enable Refresh Reserved Program Read Match Address Bits 15-12
Reset Value Match Address Bits 23-16
Figure Lower Memory Chip Select Register
Figure Lower Memory Chip Select Register
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Upper Memory Chip Select Control
upper boundary this memory area address 00FFFFFFH. user define area immediately below this boundary with size that integer power two, starting Kbytes. That upper memory area either Kbytes, Kbytes, Kbytes /UMCS signal enabled active during refresh transactions.
Upper Memory Chip Select Register
MA23-MA16 (Match Address Bits 23-16). match address logic corresponding address signal memory transaction compared logic condition /UMCS become active. mask address logic corresponding address signal compared (don't care). example, MA23 determines should tested logic memory transactions. Note that order for/UMCS active memory transaction, /UMCS function enabled Memory Selects Master Enable Register (described later), address signals A31-A24 logic address signals A23-A12 programmed address matching above registers have logic define upper memory area Kbytes, MA23-MA12 should programmed with area larger than Kbytes, MA23-MA12 that order) should programmed with contiguous followed contiguous This intended usage maintain upper memory area single block. Note also that /UMCS enabled refresh transactions independent value programmed into Memory Selects Master Enable Register.
Upper Memory Chip Select Register
MA15-MA12 (Match Address Bits 15-12). match address logic corresponding address signal memory transaction compared logic condition /UMCS become active. match address logic corresponding address signal compared (don't care). example, MA12 determines should tested logic memory transactions. Reserved bits 3-1. Read should write (Enable Refresh Transactions). this programmed logic /UMCS goes active during refresh transactions.
UMCSR1: 00000003H
UMCSR0: 00000002H MA15 MA14 MA13 MA12 Reset Value Enable Refresh Reserved Program Read Match Address Bits 15-12
MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 Reset Value Match Address Bits 23-16
Figure Upper Memory Chip Select Register
Figure Upper Memory Chip Select Register
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Mid-range Memory Chip Select(s) Control
chip select scheme user define base address total size mid-range memory area. /MCS0 signal would active lowest quarter portion area defined, starting from base address. Each /MCS1-/MCS3 signals would active, corresponding successively higher quarter portions total mid-range memory area. chip select scheme mid-range memory area between lower upper memory areas. /MCS3-/MCS0 signals individually enabled active refresh transactions.
Mid-range Memory Chip Select Register
MA23-MA16 (Match Address bits). chip select scheme match address logic corresponding address signal memory transaction compared with corresponding base address match, condition /MCS3-/MCS0 become active. match address logic corresponding address signal base address compared (don't care). example, MA23 determines should compared match with BA23. contents this register have effects chip select scheme
MMCSR1: 00000005H MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 Reset Value Match Address Bits 23-16
Mid-range Memory Chip Select Register
MA15-MA14 (Match Address Bits 15-14). chip select scheme match address logic corresponding address signal memory transaction compared with corresponding base address match, condition /MCS3-/MCS0 become active. match address logic corresponding address signal base address compared (don't care). example, MA14 determines should compared match with BA14. values MA15-MA14 have effects chip select scheme Reserved bits 5-4. Read should write ERF3-ERF0 (Enable Refresh Transactions). midrange memory chip select signals individually enabled active during refresh transactions. example, /MCS0 goes active refresh transactions ERF0 programmed logic
MMCSR0: 00000004H MA15 MA14 ERF3 ERF2 ERF1 ERF0 Reset Value Enable Refresh Transactions Reserved Bits Match Address Bits 15-14
Figure Mid-range Memory Chip Select Register
Mid-range Memory Chip Select Register
MMCSR2: 00000006H BA15 BA14
Reset Value
Figure Mid-range Memory Chip Select Register
Figure Mid-range Memory Chip Select Register
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BA23-BA14 (Base Address 23-14). chip select scheme address signals A23-A16 memory transaction compared with BA23-BA16 match, those bits programmed address matching Mid-range Memory Chip Select Register contents this register have effects chip select scheme Note that order /MCS3-/MCS0 active memory transaction chip select scheme ENM1 Memory Selects Master Enable Register (described later) logic address signals A31-A24 logic those bits programmed address matching, A23-A14 matching BA23-BA14. intended usage maintain mid-range memory area single block, MA23-MA14 that order) should programmed address matching with contiguous followed contiguous Note also that /MCS3-/MCS0 individually enabled active during refresh transactions, independent value programmed into Memory Selects Master Enable Register.
LMWR: 00000008H
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Waits Waits
Figure Lower Memory Waits Register
Upper Memory Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing upper memory area. T2W1-T2W0 Waits). This binary field defines three wait states inserted transactions accessing upper memory area. T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing upper memory area.
UMWR: 00000009H
MMCSR3: 00000007H
BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Reset Value
Figure Mid-range Memory Chip Select Register
Lower Memory Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing lower memory area. T2W1-T2W0 Wait States). This binary field defines three wait states inserted transactions accessing lower memory area. T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing lower memory area.
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Waits Waits
Figure Upper Memory Waits Register
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Mid-range Memory Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme entire mid-range memory area chip select scheme T2W1-T2W0 Waits). This binary field defines three wait states inserted transactions accessing mid-range memory area chip select scheme entire mid-range memory area chip select scheme T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme entire mid-range memory area chip select scheme
MMWR0: 0000000AH
Mid-Range Memory Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme T2W1-T2W0 Waits). This binary field defines three wait states inserted transactions accessing mid-range memory area chip select scheme T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme contents this register have effects chip select scheme
MMWR1: 0000000BH
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Reset Value Waits Waits Waits Waits Waits
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
Figure Mid-range Memory Waits Register
Figure Mid-range Memory Waits Register
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Mid-Range Memory Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme T2W1-T2W0 Waits). This binary field defines three wait states inserted transactions accessing mid-range memory area chip select scheme T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme contents this register have effects chip select scheme
Mid-range Memory Waits Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme T2W1-T2W0 Waits). This binary field defines three wait states inserted transactions accessing mid-range memory area chip select scheme T3W2-T3W0 Waits). This binary field defines seven wait states inserted transactions accessing mid-range memory area chip select scheme contents this register have effects chip select scheme
MMWR2: 0000000CH
MMWR3: 0000000DH
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Waits Waits
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Waits Waits
Figure Mid-Range Memory Waits Register
Figure Mid-range Memory Waits Register
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Memory Chip Selects Waits Master Control
memory chip selects their associated waits enabled disabled writing single register described following:
MSMER: 00000010H ENLM ENUM ENM1 ENM2
Memory Selects Master Enable Register
user reset desired bits this register without modifying states remaining bits, with defining reset function.
Reset Value Reset Control Reserved Enable Mid-range Memory Chip Select Scheme Waits Enable Mid-range Memory Chip Select Scheme Waits Enable Upper Memory Chip Select Waits Enable Lower Memory Chip Select Waits
Figure Memory Selects Master Enable Register
ENLM (Enable Lower Memory Chip Select Waits). This logic enables /LMCS signal active starting cycle time memory transaction accessing lower memory area. associated programmed wait states automatically inserted transaction. ENUM (Enable Upper Memory Chip Select Waits). This logic enables /UMCS signal active starting cycle time memory transaction accessing upper memory area. associated programmed wait states automatically inserted transaction. ENM1 (Enable Mid-range Memory Chip Select Scheme Waits). This logic enables /MCS3/MCS0 active starting cycle time memory transaction, depending which mid-range memory areas being accessed. corresponding programmed wait states automatically inserted transaction. ENM2 (Enable Mid-range Memory Chip Select Scheme Waits). This logic enables /MCS0 active starting cycle time memory transaction accessing mid-range memory area. corresponding programmed wait states automatically inserted transaction. Reserved bits 3-1. Read should write
(Set Reset Control). When writing Memory Selects Master Enable Register with bits that selected with logic set. When writing with bits that selected with logic cleared. either case, bits selected modified. always read logic Additional Comments. either chip select scheme, chip select waits functions enabled, their memory areas defined cause overlaps, precedence conflict resolution /LMCS, then /UMCS, then /MCS3-/MCS0. example, consider case where both lower mid-range memory area defined occupy same address space. With ENLM Memory Selects Master Enable Register (ENM1 either /LMCS goes active memory transaction that accesses overlapped address space. With ENLM ENM1 /MCS0 would active transaction instead. Regardless state address bus, chip select signals their inactive logic when corresponding enable bits Memory Selects Master Enable Register (MSMER) logic except during DRAM refresh transactions enabled, Z380 MPUs halt state, except during DRAM refresh transactions enabled, Z380 relinquishes system with /BREQ input active, Z380 power standby mode.
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DRAM Refresh
Z380 capable providing refresh transactions dynamic memories that have internal refresh address counters. user select often refresh requests should made MPU's External Interface Logic, well burst size (number refresh transactions) each request iteration. External Interface Logic grants these requests performing refresh transactions with CAS-before-RAS timing /TREFR, /TREFA /TREFC control signals. these transactions, /BHEN, /BLEN user specified chip select signal(s) driven active facilitate refreshing DRAM modules same time. user also specify waits inserted. Note that Z380 cannot provide refresh transactions when relinquishes system bus, with /BREQ input active. that situation, number missed refresh requests accumulated counter, when regains system bus, missed refresh transactions will performed.
Refresh Register
MR7-MR0 (Missed Requests Count). This count increments when refresh request made, maximum value 255. Refresh requests over maximum value would lost. When Z380 MPU's External Interface Logic completes each burst refresh transactions, count decrements user read count status, necessary, take corrective actions such adjusting burst size. When refresh function disabled, this count held
RFSHR1: 00000014H Only Reset Value Missed Requests Count
Refresh Register
RI7-RI0 (Request Interval). RI7-RI0 defines interval between refresh requests Z380 MPU's External Interface Logic. value specified this field denotes request interval BUSCLK periods. RI7-RI0 programmed request interval 1024 BUSCLK periods.
RFSHR0: 00000013H Reset Value Request Interval
Figure Refresh Register
Figure Refresh Register
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Refresh Register
RFEN (Refresh Enable). Enables refresh function when programmed logic Reserved Read should write BS5-BS0 (Burst Size). This field defines number refresh transactions refresh request made Z380 MPU's External Interface Logic. burst size ranges from with highest size specified with BS5-BS0 equal
RFSHR2: 00000015H RFEN Reset Value Burst Size Reserved Refresh Enable
Refresh Wait Register
T1W2-T1W0 Waits). This binary field defines seven wait states inserted refresh transactions. T1W1-T2W0 Waits). This binary field defines three wait states inserted refresh transactions. T3W2-T3W0 Waits). This binary field defines seven wait states inserted refresh transactions. Note that care should exercised defining refresh burst size request intervals avoid over-burdening system with refresh transactions. memory chip select signals selectively enabled active during refresh transactions, such enabling described Memory Chip Selects Waits section.
RFWR: 0000000FH
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0 Reset Value Waits Waits Waits
Figure Refresh Register
Figure Refresh Waits Register
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POWER STANDBY MODE
Z380 provides optional standby mode minimize power consumption during system idle time. this option enabled, executing Sleep instruction would stop clocking internal Z380 MPU, well BUSCLK IOCLK outputs. /STNBY signal goes active logic indicating Z380 entering standby mode. Z380 operations suspended, control signals driven inactive address driven logic Note that external crystal oscillator used drive Z380 MPU's CLKI input, /STNBY used stop operation. This means further reduce power dissipation overall system. standby mode exited asserting /RESET, /NMI, /INT3-/INT0 enabled), optionally, /BREQ inputs. standby mode option enabled, Sleep instruction interpreted executed different than HALT instruction, stopping from further instruction execution. this case, /HALT goes active logic indicate Z380 MPU's halt status.
Standby Mode Control Entering
STBY (Enable Standby Mode Option). Enables Z380 into power standby mode when Sleep instruction executed. BRXT (Bus Request Exit Standby Mode). BRXT logic standby mode exited asserting /BREQ. Reserved Bits 5-3. Read should write WM2-WM0 (Warm-up Time Selection). WM2-WM0 determines approximate running duration warm-up counter that provides delay before Z380 resumes clocking operations, from time interrupt request enabled) asserted exit standby mode. system where external crystal oscillator used drive Z380 MPU's input, appropriate warm-up time selected oscillator stabilize.
SMCR: 00000016H
STBY BRXT
Reset Value Warmup Time Selection Warmup
BUSCLK Cycles BUSCLK Cycles BUSCLK Cycles Reserved Program Read Request Exit Standby Mode Enable Standby Mode Option
Figure Standby Mode Control Register
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Standby Mode Exit With Request
Optionally, BRXT Standby Mode Control Register (SMCR) previously set, /STNBY goes logic when /BREQ input asserted, allowing external crystal oscillator that drives Z380 MPU's input restart. warm-up counter internal Z380 proceeds count, duration long enough oscillator stabilize, which selected with bits SMCR. When counter reaches end-count, clocking resumes within Z380 BUSCLK IOCLK outputs. Z380 relinquishes system after clocking resumes, with normal /BREQ, /BACK handshake procedure. Z380 regains system when /BREQ goes inactive, again going through normal handshake procedure. Note that clocking continues, Z380 halt state.
Release BUSCLK
Halt State
IOCLK
/STNBY
/BREQ
/BACK
ADDRESS
FFFFFFFFH
DATA CNTLS
Figure Standby Mode Exit with Request Timing
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Standby Mode Entering Timing
Figure shows standby mode entering timing example where IOCLK programmed BUSCLK divided-by-2. Note that clocking stops only after IOCLK changed logic
BUSCLK
IOCLK
/STNBY
ADDRESS
FFFFFFFFH
DATA
CNTLS
(/TREFR, /TREFA, /TREFC, /MRD, /MWR, /BHEN, /BLEN, /IOCTL3-0)
Figure Standby Mode Entering Timing
Standby Mode Exit With Reset
When /RESET asserted, /STNBY goes logic allowing external crystal oscillator that drives Z380 MPU's CLKI input restart. /RESET pulse provided should duration long enough oscillator stabilization. Z380 exits standby mode, when /RESET deasserted, goes through normal reset timing start instruction execution address 00000000H. Note that clocking resumes within Z380 BUSCLK IOCLK outputs soon after /RESET asserted, when crystal oscillator stabilized.
OPCODE FETCH BUSCLK
IOCLK
/STNBY
/RESET
ADDRESS
FFFFFFFFH
000000H
DATA
Figure Standby Mode Exit with Reset Timing
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Standby Mode Exit With External Interrupts
Standby mode exited asserting input /NMI. Asserting maskable interrupt inputs /INT3-/INT0 also exit standby mode, global interrupt flag IEF1 previously enabled logic those requests individually enabled, indicated Interrupt Enable Register. When exit conditions met, /STNBY goes logic allowing external crystal oscillator that drives Z380 MPU's input restart.
Z380 MPU's internal warm-up counter proceeds count, duration long enough oscillator stabilize, selected bits Standby Mode Control Register. When counter reaches end-count, clocking resumes within Z380 MPU, well BUSCLK IOCLK outputs. Z380 performs interrupt acknowledge procedure appropriate interrupt request that initiated standby mode exit.
Appropriate Acknowledge BUSCLK
IOCLK
/STNBY
/NMI
/INT3,2,1,0
ADDRESS
FFFFFFFFH
Figure Standby Mode Exit with External Interrupts Timing
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Standby Mode On-chip Crystal Oscillator
previous discussions have been focused situations where direct clock supplied Z380 MPU's CLKI input. Such clock sourced external crystal with oscillation circuit. case where crystal connected Z380 MPU's on-chip oscillator, standby functions described earlier apply. Items worth noting follows. When standby mode entered, feedback path on-chip oscillator disabled, reducing power consumption. user select warm-up time appropriate crystal being used, programming WM2-WM0 bits Standby Mode Control Register (SMCR).
Table Z380 On-chip Registers Register Lower Memory Chip Select Register Lower Memory Chip Select Register Upper Memory Chip Select Register Upper Memory Chip Select Register Midrange Memory Chip Select Register Midrange Memory Chip Select Register Midrange Memory Chip Select Register Midrange Memory Chip Select Register Lower Memory Waits Register Upper Memory Waits Register Midrange Memory Waits Register Midrange Memory Waits Register Midrange Memory Waits Register Midrange Memory Waits Register Waits Register Refresh Waits Register Memory Selects Master Enable Register Control Register Control Register Refresh Register Refresh Register Refresh Register Standby Mode Control Register Interrupt Enable Register Assigned Vectors Base Register Trap Break Register Mnemonic LMCS0 LMCS1 UMCS0 UMCS1 MMCS0 MMCS1 MMCS2 MMCS3 LMWR UMWR MMWR0 MMWR1 MMWR2 MMWR3 IOWR RFWR MSMER IOCR0 IOCR1 RFSHR RFSHR1 RFSHR2 SMCR AVBR TRPBK On-Chip Address 00000000H 00000001H 00000002H 00000003H 00000004H 00000005H 00000006H 00000007H 00000008H 00000009H 0000000AH 0000000BH 0000000CH 0000000DH 0000000EH 0000000FH 00000010H 00000011H 00000012H 00000013H 00000014H 00000015H 00000016H 00000017H 00000018H 00000019H
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RESET
Z380 placed dormant state when /RESET input asserted. operations terminated, including interrupt, request transaction that progress. IOCLK goes next BUSCLK rising edge, enters into BUSCLK divideddown-by-eight mode. address data buses tristated, control signals driven their inactive states. effect reset Z380 related registers depicted Table effect on-chip peripheral functions summarized Table /RESET input asynchronous BUSCLK, though sampled internally BUSCLK's falling edges. proper initialization Z380 MPU, must within operating specification BUSCLK must stable more than five cycles with /RESET held Low. /RESET input built-in Schmitt trigger buffer facilitate power-on reset generation through network. Note that user system devices external Z380 that clocked IOCLK, these devices require /RESET pulse width that spans over number IOCLK cycles (now BUSCLK/8) proper initialization. Z380 proceeds fetch first instruction BUSCLK cycles after /RESET deasserted, provided such deassertion meets proper setup hold times with reference falling edge BUSCLK, depicted Figure External Interface Section. Figure same section indicates synchronization IOCLK when /RESET deasserted. Again with proper setup hold times being met, IOCLK's first rising edge 11.5 BUSCLK cycles after /RESET deassertion, preceded minimum BUSCLK cycles where IOCLK Low. Note that /BREQ active when /RESET deasserted, Z380 would relinquish instead fetching first instruction. IOCLK synchronization would still take place described before.
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Table Effect Reset Z380 Related Registers Register Program Counter Stack Pointer Select Regist
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