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WirelessUSBData Sheet
Unigen Corp. Wireless Products Part Number Family: LETO-USB WirelessUSBRadio Devices UGQLUE4US50A Series Short Range Modules
Issue Date: June 2007 Revision: 1.10
Revision History
Rev.
History
Final Draft Prelim Release Updated
Issue Date
2006 2006 2007
Remarks
Update Reference Documents, Functional Description Preliminary Release, adds test data Updated electrical characteristics
THIS DOCUMENT PROVIDED WITH WARRANTIES WHATSOEVER, INCLUDING WARRANTY MERCHANTABILITY, NON-INFRINGEMENT, FITNESS PARTICULAR PURPOSE, WARRANTY OTHERWISE ARISING PROPOSAL, SPECIFICATION SAMPLE. Unigen Corporation disclaims liability, including liability infringement proprietary rights, relating information this document. license, expressed implied, estoppel otherwise, intellectual property rights granted herein. *Third-party brands, names, trademarks property their respective owners.
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Table Contents: Revision History.1 REFERENCE DOCUMENTATION: INTRODUCTION: FEATURES: DESCRIPTION: FUNCTIONAL BLOCK DIAGRAMS: ABSOLUTE MAXIMUM RATINGS: RECOMMENDED OPERATING CONDITIONS: ELECTRICAL CHARACTERISTICS: Table Electrical Characteristics RADIO PARAMETERS: AGENCY CERTIFICATIONS (PRE-SCAN): Table Regulatory Agency Certifications REGULATORY COMPLIANCE STATEMENT: FUNCTIONAL OVERVIEW: MECHANICAL CHARACTERISTICS: MECHANICAL DRAWINGS: ORDERING INFORMATION:* Typical Applications CONTACT INFORMATION:
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REFERENCE DOCUMENTATION:
Unigen LETO-USB (UGQLUE4US50A) WirelessUSBUSB devices Cypress Semiconductor CY7C64215 enCoRe full speed controller CYRF6936 2.4GHz DSSS Radio represented this document. detail provided information using LETO-USB digital electronic device only "companion" document Cypress Semiconductors' CYWRF6936 documentation above noted part. CY7C64215 enCoRe full speed controller CYRF6936 2.4GHz DSSS Radio 10-meter information technical detail (ex. register settings, timing, application interfaces, clocking power management, etc.) obtained from Cypress Semiconductor site contacting Cypress's authorized sales representatives. following list required documents locations known time publication that accompany this datasheet. CY7C64215 enCoRe full speed controller Datasheet CY7C64215.pdf ntents/cy7c64215_8.pdf CYRF6936 2.4GHz DSSS Radio Datasheet CYRF6936.pdf ntents/cyrf6936_8.pdf
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INTRODUCTION:
Unigen LETO-USB WirelessUSBLP meter range module represent convergence emerging wireless connectivity solutions "Plug-N-Play" ease operation. WirelessUSBTM, created Cypress Semiconductor, low-cost, 2.4GHz communication protocol designed commercial, industrial, consumer, computer product applications needing highly reliable data connectivity. LETO-USB device combine Cypress Semiconductor's wireless expertise with Unigen's module design, manufacturing, testing proficiency create production ready, pre-certified devices that easily integrated into existing, product designs. LETO-USB device offer immediate, drop-in design solutions native Operating System drivers seamlessly enumerate operate mouse, keyboard, gaming devices, other devices using specification communication with host systems.
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FEATURES:
full speed Complete Transceiver Radio module: CYRF6936 2.4GHz DSSS Radio SOC, Tuned Matching Network, 10ppm crystal, complete PCBA including trace antenna universal position interface header Operates 2.483GHz, unlicensed frequency range (ISM Industrial, Scientific Medical) Transmit power +4dBm Receive sensitivity -97dBm Transmission Range meters NLOS DSSS data rates kbps, GFSK data rate Mbps Auto Transaction Sequencer (ATS) intervention Framing, Length, CRC16, Auto Fast Startup Fast Channel Changes Separate 16-byte Transmit Receive FIFOs AutoRate- dynamic data rate reception Receive Signal Strength Indication (RSSI) Serial Peripheral Interface (SPI) control while sleep mode 4-MHz microcontroller interface Operating voltage from 3.0V 5.25V Sleep Current <20mA Operating current 35mA-62mA Internal setting (-5dBm) thru (+4dBm) Operating temperature from 70°C Small PCBA Design: 1.5" 0.66" 0.224" (38.1mm 16.8mm mm*) *board board height Device Approval: Part 300328-1, 489-1, Industry Canada RSS-210 standards additional regulatory test needed listed countries
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DESCRIPTION:
LETO-USB WirelessUSBdevices tightly integrated, low-cost, high-reliability 2.4GHz TX/RX communications devices with Human Interface Device (HID) class compliant products. LETO-USB devices Cypress Semiconductor CY7C64215 enCoRe full speed controller CYRF6936 2.4GHz DSSS Radio device LETO-USB devices complete radio solution requiring only integration into existing, device. LETO-USB devices 100% tested functional operation pre-screened Part compliance. devices supplied with integrated antenna. applications where integrated antenna unsuitable, model available that support using external coaxial antenna. Unigen recommends using 2dBi gain dipole antennae customers requiring external antenna. LETO-USB devices intended computer consumer product/device applications native class drivers enable compliant devices. most applications, additional host drivers required. devices suitable embedded and/or industrial applications well.
FUNCTIONAL BLOCK DIAGRAMS:
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CY7C64215 Simplified Block Diagram
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CYRF6936 Simplified Block Diagram
ABSOLUTE MAXIMUM RATINGS:
Symbol O/Hi-Z SDVD SDVR Definition Supply Voltage Storage Temperature Range Ambient Temperature with Power Applied Logic Inputs Outputs High-Z state Static Discharge Voltage Digital Static Discharge Voltage Latch-up Current Min. -0.5 -0.5 -0.5 Max. >2000 >1100 -200 Unit
+200
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These stress ratings only. Exposure stresses beyond these maximum ratings cause permanent damage affect reliability this module. Avoid using module outside recommended operating conditions defined below. This module sensitive should handled and/or used accordance with proper mitigation.
RECOMMENDED OPERATING CONDITIONS:
Symbol Description Supply Voltage Commercial Operating Temperature Range Ground Voltage Min. Value Typ.* Max. 5.25 Unit
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ELECTRICAL CHARACTERISTICS:
Symbol
VOH1 VOH2 (GSFK) (32-8DR) IDLE ISYNTH MTBF
Description
Supply Voltages Voltage Output High Condition Voltage Output High Condition Voltage Output Voltage Input High Voltage Input Input Leakage Current Average ICC, 1Mbps, slow channel Average ICC, 250kbps, fast channel Sleep Mode Radio off, XTAL Active During Synth Start During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Transmit (VCC 3.3VDC) During Receive (VCC 3.3VDC) During Receive (VCC 3.3VDC)
Condition(s)
Min.
Value Typ.* Max.
5.25
Unit
-100.0µA -2.0 PA=5, 2-way, 4bytes/10 PA=5, 2-way, 4bytes/10 disabled XOUT disabled (-35 dBm) (-30 dBm) (-24 dBm) (-18 dBm) (-13 dBm) dBm) dBm) dBm) off, Calculated 36.1 36.4 36.9 37.3 38.1 39.8 42.8 49.1 38.1 41.5
0.26 0.87 20.8 21.0 28.4 36.4 36.7 37.2 37.6 38.4 40.1 43.1 49.4 38.6 42.0
0.75
36.7 37.0 37.5 37.9 38.7 40.4 43.4 49.7 39.1 42.5 >87,600
Hours
Table Electrical Characteristics
Measured with 5.0VCC
Mean when transmitting 5-byte packet data bytes bytes protocol) every 10ms using Wireless 1-way protocol. Mean when transmitting 5-byte packet data bytes bytes protocol) every 10ms using Wireless 2-way protocol.
Notes permissible connect voltages above inputs through series resistor limiting input current timing guaranteed. Human Body Model (HBM). VREG depends battery input voltage. sleep mode, interface voltage reference VBAT. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including CRC16), changing receive mode, receiving handshake. Device sleep except during this transaction. guaranteed connected voltages higher than VIO.
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RADIO PARAMETERS:
Parameter Description Condition Frequency Range Radio Receiver 3.3V, fOSC= 12.000000MHz, 10-3 Sensitivity 125kbps 64-8DR 1E-3 Sensitivity 250kbps 32-8DR 1E-3 Sensitivity 1E-3 Sensitivity GFSK 1E-3, SLOW Gain Gain Maximum Received Signal RSSI Value PWRin >-60dBm RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Out-of-band Blocking Interference Signal Frequency 30MHz 12.75GHz Intermodulation dBm, 10MHz Receive Spurious Emission ResBW ResBW ResBW Radio Transmitter 3.3V) Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Power Control Range Power Range Control Step Size Seven steps, monotonic Frequency Deviation Code Pattern 10101010 Frequency Deviation Code Pattern 11110000 Error Vector Magnitude (FSK Error) Zero Crossing Error Occupied Bandwidth ResBW, -6dBc Initial Frequency Offset Transmission In-Band Spurious Second Channel Power MHz) Third Channel Power MHz) Non-Harmonically Related Spurs Harmonic Spurs Second Harmonic Third Harmonic Fourth Greater Harmonics Min. 2.400 Typ. 22.8 -31.7 ±125 2.497 Unit Count dB/Count
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Power Management Crystal Start Crystal Start Synth Settle Synth Settle Synth Settle Link turn-around time Link turn-around time Link turn-around time Link turn-around time Maximum Packet Length Maximum Packet Length
WirelessUSBData Sheet
XSIRQ EN=1 Slow channels Medium channels Fast channels GFSK kbps 125kbps <125kbps modes except
bytes bytes
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AGENCY CERTIFICATIONS (PRE-SCAN):
Agency
Test Performed
Radiated Spurious Emissions
Type
30-12.75MHz Transmit Mode 30-12.75MHz Transmit Mode 25,000 Spurious Emissions Bandwidth Bandwidth Output Power Power Spectral Density (PSD) Bandedge band Output Power, Power spectral density normal conditions Frequency Range normal conditions Output Power over extreme conditions Frequency Range over extreme conditions Conducted spurious emissions, 30MHz 12750MHz, transmit mode Conducted spurious emissions, 30MHz 12750MHz, receive/stand-by mode 12,750 -Spurious Emissions Transmit Mode 12,750 -Spurious Emissions Receive Mode
Limit
Part 15.209/15.247 15.247(a) RSS-210 15.247(b) 15.247(d) Part 15.209 /15.247( 15.247( 328-1 328-1 328-1 328-1 328-1 328-1 V1.2.1 V1.2.1
Result
PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS
Margin
-4.6dB 4804MHz -4.9 177.01MHz Results File 960kHz 1.175MHz 7.2dBm 3.06dBm Results File Results File Results File Results File
15.247
Radiated Emissions
Radio Performance Test
Results File Results File Results File Results File
Radiated Spurious Emissions
Table Regulatory Agency Certifications
REGULATORY COMPLIANCE STATEMENT:
device been pre-scanned against relevant requirements standards: 328, 489-17, part Industry Canada RSS-210. device certified regulatory authorities Canada complies with applicable essential requirements Radio Telecommunication Terminal Equipment (R&TTE) directive device thus incorporated into products sold worldwide with little additional testing module itself. product must meet appropriate technical
requirements that apply that product type re-certification radio module required Canada.
integrator responsible evaluating their product type essential performance requirements R&TTE directive (except those associated with module), declaring compliance then notifying member states prior marketing product (because module uses frequency band that harmonized EU). responsibility module integrator obtain necessary approval sell products incorporating this module other countries outside North America report measurements performed module compliance with rules standards used these submittal requirements many other markets around world based part whole standards prevalent North America EU).
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FUNCTIONAL OVERVIEW:
CY7C64215, enCoRe based flexible PSoC architecture full-featured, full-speed Mbps) part. Configurable analog, digital, interconnect circuitry enable high level integration host consumer, communication applications. CYRF6936 provides complete WirelessUSB antenna wireless MODEM. designed implement wireless device links operating worldwide 2.4-GHz frequency band. intended systems compliant with world-wide regulations covered ETSI 489-1 V1.41, ETSI 328-1 V1.3.1 (Europe), Part (USA Industry Canada) TELEC ARIB_T66_March, 2003 (Japan). contains 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), interface data transfer device configuration. radio supports discrete 1-MHz channels (regulations limit some these channels certain jurisdictions). baseband performs DSSS spreading/despreading, Start Packet (SOP), Packet (EOP) detection CRC16 generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates enabling implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems, which high data rates shorter distances and/or low-moderate interference environment, change lower data rates longer distances and/or high interference environments. addition, CYRF6936 Power Management Unit (PMU) which allows direct connection device battery voltage range 1.8V 3.6V. conditions battery voltage provide supply voltages required device, supply external devices. Data Transmission Modes supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS. mode, bits encoded each derived code symbol transmitted. mode, 2-bits encoded each derived code symbol transmitted. CYWUSB6934 mode). mode, encoded each derived code symbol transmitted. CYWUSB6934 standard modes.) Both 64-chip 32-chip Pseudo-Noise (PN) Codes supported. four data transmission modes apply data after SOP. particular length, data, CRC16 sent same mode. general, lower data rates reduce packet error rate given environment. Link Layer Modes CYRF6936 device supports following data packet framing features: Packets begin with 2-symbol Start Packet (SOP) marker. This required GFSK modes, optional mode supported mode; framing disabled then event inferred whenever successive correlations detected. SOP_CODE_ADR code used different from that used "body" packet desired different length. must configured same length both sides link. Length There options detecting packet. enabled, then length field should enabled. GFSK must enable length field. This first 8-bits after symbol, transmitted payload data rate. When length field enabled, Packet (EOP) condition inferred after reception number bytes defined length field, plus bytes CRC16 (when enabled-see below). alternative using length field infer condition from configurable number successive non-correlations; this option available GFSK mode only recommended enable when using mode.
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CRC16 device configured append 16-bit CRC16 each packet. CRC16 uses polynomial with added programmability seed. enabled, receiver will verify calculated CRC16 payload data against received value CRC16 field. seed value CRC16 calculation configurable, CRC16 transmitted calculated using either loaded seed value zero seed; received data CRC16 will checked against both configured zero CRC16 seeds. CRC16 detects following errors: error bits error matter apart, which column, number bits error matter where they are) error burst wide checksum itself
Figure shows example packet with SOP, CRC16 lengths fields enabled, Figure shows standard
packet. Figure 6-1. Example Packet Format
Figure 6-2. Example Packet Format
Packet Buffers data transmission reception utilizes 16-byte packet buffers-one transmission reception. transmit buffer allows complete packet 16-bytes payload data loaded burst transaction, then transmitted with further intervention. Similarly, receive buffer allows entire packet payload data bytes received with firmware intervention required until packet reception complete. CYRF6936 supports packets bytes, however, actual maximum packet length will depend accuracy clock each link data mode; interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load 16-bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, must fetch received data from FIFO periodically during packet reception prevent from overflowing. Auto Transaction Sequencer (ATS)
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CYRF6936 provides automated support transmission reception acknowledged data packets. When transmitting transaction mode, device automatically: starts crystal synthesizer enters transmit mode transmits packet transmit buffer transitions receive mode waits packet transitions transaction state when either packet received, timeout period expires Similarly, when receiving transaction mode, device automatically: waits receive mode valid packet received transitions transmit mode, transmits packet transitions transaction state (receive mode await next packet, etc.) contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action (providing packets bytes less used); transmit data simply needs load data packet transmitted, length, bit. Similarly, when receiving packets transaction mode, firmware simply needs retrieve fully received packet response interrupt request indicating reception packet. Backward Compatibility CYRF6936 fully interoperable with main modes first generation devices. 62.5-kbps mode supported selecting 32-chip mode. Similarly, 15.675-kbps mode supported selecting 64-chip mode. this way, suitably configured CYRF6936 device transmit data and/or receive data from first generation device. Disabling SOP, length, CRC16 fields required backwards compatibility. Data Rates combining code lengths data transmission modes described above, CYRF6936 supports following data rates: 1000-kbps (GFSK) 250-kbps (32-chip 8DR) 125-kbps (64-chip 8DR) 62.5-kbps (32-chip DDR) 31.25-kbps (64-chip DDR) 15.625-kbps (64-chip SDR)
Functional Block Overview
2.4-GHz Radio radio transceiver dual conversion architecture optimized power range/robustness. radio employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range steps. supply current device reduced output power reduced.
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WirelessUSBData Sheet
Typical Output Power (dBm)
Typical Range Observed Table Environment Typical Range (meters) NLOS Home/Office Note: Range observed PA=7, Fremont, Frequency Synthesizer Before transmission reception commence, necessary frequency synthesizer settle. settling time varies depending channel; fast channels provided with maximum settling time 100-s. "fast channels" (<100-s settling time) every channel, starting including (i.e., 0,3,6,9.69 72). Baseband Framer baseband framer blocks provide DSSS encoding decoding, generation reception CRC16 generation checking, well detection length field. Packet Buffers Radio Configuration Registers Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet CYWUSB6934). Configuration registers provided allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status, etc. Interface CYRF6936 interface supporting communications between application more slave devices (including CYRF6936). interface supports single-byte multi-byte serial transfers using either 4-pin 3-pin interfacing. communications interface consists Slave Select (SS), Serial Clock (SCK), Master OutSlave (MOSI), Master In-Slave (MISO), Serial Data (SDAT). communications follows: Command Direction (bit enables write transaction. enables read transactions. Command Increment (bit enables auto address increment. When set, address field automatically increments each data byte burst access, otherwise same address accessed. bits address. Eight bits data.
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device receives from application pin. Data from application shifted MOSI pin. Data application shifted MISO pin. active-low Slave Select (SS) must asserted initiate transfer. application initiate data transfers multibyte transaction. first byte Command/Address byte, following bytes data bytes shown Figure through Figure 7-4. communications interface burst mechanism, where first byte followed many data bytes desired. burst transaction terminated deasserting slave select communications interface single read burst read sequences shown Figure Figure 7-3, respectively. communications interface single write burst write sequences shown Figure Figure 7-5, respectively. This interface optionally operated 3-pin mode with MISO MOSI functions combined single bidirectional data (SDAT). When using 3-pin mode, user firmware should ensure that MOSI high impedance state except when MOSI actively transmitting data. device registers written read from byte time, several sequential register locations written/read single transaction using incrementing burst mode. addition single byte configuration registers, device includes register files; register files FIFOs written read from using non-incrementing burst transactions. function optionally multiplexed onto MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI high impedance state whenever high. interface dependent internal 12-MHz clock, registers therefore read from written while device sleep mode, 12-MHz oscillator disabled. interface pins have separate voltage reference (VIO), enabling device interface directly MCUs operating voltages below CYRF6936 supply voltage.
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Figure Transaction Format
WirelessUSBData Sheet
Figure Single Read Sequence
Figure Incrementing Burst Read Sequence
Figure Single Write Sequence
Figure Incrementing Burst Write Sequence
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Interrupts device provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active high active low, either CMOS open drain output. full description available interrupts found Section 9.0. CYRF6936 features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled/disabled. contents enable registers preserved when switching between transmit receive modes. more than interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without making polling status register(s) wait event, rather than using pin. Clocks 12-MHz crystal (30-ppm better) directly connected between XTAL without need external capacitors. digital clock function provided, with selectable output frequencies 0.75-, 1.5-, 12-MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. Below requirements crystal directly connected XTAL GND: Noise Amplifier (LNA) Received Signal Strength Indication (RSSI) gain receiver controlled directly clearing writing Noise Amplifier (LNA) RX_CFG_ADR register. When cleared, receiver gain reduced approximately allowing accurate reception very strong received signals (for example when operating receiver very close transmitter). Approximately receiver attenuation added setting Attenuation (ATT) bit; this allows data reception limited devices very short ranges. Disabling enabling recommended unless receiving from device using external When device receive mode RSSI_ADR register returns relative signal strength on-channel signal power. When receiving, device will automatically measure store relative strength signal being received 5-bit value. RSSI reading taken automatically when detected. addition, RSSI reading taken every time previous reading read from RSSI_ADR register, allowing background energy level given channel easily measured when RSSI read when signal being received. reading occur fast once every
Register Descriptions
registers read writable, except where noted. Registers written read from either individually sequential groups. Register Summary
Address 0x00 Mnemonic CHANNEL_ADR Used Channel Default[1] -1001000 Access[1] -bbbbbbb
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0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x26 0x27 0x28 TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR XOUT XOUT Used Used SEED SEED STRIM Used RSVD RSVD RSVD RSVD Used RSVD RXTX RSVD RSVD RSVD Used RXACK RSVD RSVD RSVD RSVD MISO Used Used Used Used LVIRQ Used RXOW Used RSVD SOPDET TXB15 IRQEN DATA CODE LENGTH TXB15 RXB16 IRQEN RXB16 Count LENGTH XSIRQ MISO PACTL Used Used HINT
WirelessUSBData Sheet
Length TXB8 IRQEN DATA MODE TXB8 RXB8 IRQEN HILO RXB8 CRC0 00000000 TXB0 IRQEN TXBERR IRQEN SETTING TXBERR RXBERR IRQEN Used RXBERR Code IRQEN IRQEN 00000011 -000101 IRQEN RXOW Data Mode IRQEN IRQEN -00000111 10010-10 -00000000 00000000 Used Used XOUT Used PACTL XOUT FREQ PACTL GPIO MISO STATE Used TH32 TH64 RSSI SEED SEED STRIM Used AWAKE RXDR TXACK RSVD RSVD RSVD STRIM Used RSVD RSVD 3PIN PACTL GPIO OUTV 10100000 000-100 00000000 0000-1-000000 10100101 -0100 -01010 0-100000 10100100 00000000 00000000 -11111111 11111111 0000000 -0000 Used RSVD RSVD RSVD 00000-0 00000000000000 00000000 00000000 00000000 bbbbbbbb bbbbbbbb -bbbbbb rrrrrrrrr -bbbbbb bbbbb-bb brrrrrrrr rrrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb Bbb-bbb bbbbbbbb bbbbrrrr bbbbbbbb bbbbbbbb -bbbb -bbbbb bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb bbbbbbbb -bbbb wwwww-w bbbbbbbbbbbbbbb wwwwwwww wwwwwwww wwwwwwww
TXB0 RXB1 IRQEN FAST TURN RXB1
Used CRC0 OVRD START RSVD RSVD RXCRC TXCRC RSVD RSVD RSVD
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0x29 0x32 0x35 0x39 RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR RSVD RSVD ABORT
WirelessUSBData Sheet
RSVD RSVD RSVD AUTO_CAL-TIME AUTO_CAL_OFFSET RSVD RSVD RSVD 00000000 00000011 00000000 00000000 wwwwwwww wwwwwwww wwwwwwww wwwwwwww
RSVD
RSVD
RSVD
RSVD
RSVD
SLOW
Register Files 0x20 TX_BUFFER_ADR 0x21 0x22 0x23 0x24 RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR
0x25 MFG_ID_ADR Notes read/write, read only, write only, used, default value undefined. SOP_CODE_ADR default 0x17FF9E213690C782. DATA_CODE_ADR default PREAMBLE_ADR default 0x333302.
Buffer File Buffer File Code File Data Code File Preamble File File
Buffer File Buffer File Code File Data Code File Preamble File File
-Note Note Note
wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
Mnemonic
CHANNEL_ADR
Address Channel
0x00
Function Bits
Used Used.
This field selects channel. 0x00 sets 2400 MHz; sets 2498 MHz. Values above 0x62 valid. default channel fast channel above frequency typically used non-overlapping WiFi systems. write this register will impact time takes synthesizer settle.
fast (100-us) medium (180-us) slow (270-us) Usable channels subject regulation Mnemonic Default Read/Write Function Bits TX_LENGTH_ADR Length This register sets length packet transmitted. length zero valid, will transmit packet with SOP, length CRC16 fields enabled), data field. Packet lengths more than bytes will require that some data bytes written after transmission packet begun. Typically, length updated prior setting maximum packet length packets bytes except framed 64-chip where maximum packet length bytes. Address 0x01
Maximum packet length limited delta between transmitter receiver crystals 60-ppm better.
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Mnemonic Default Read/Write Function TX_CTRL_ADR
WirelessUSBData Sheet
Address
0x02
TXB8 TXB0 TXBERR IRQEN IRQEN IRQEN IRQEN IRQEN Start Transmission. Setting this triggers transmission packet. Writing this flag effect. This cleared automatically packet transmission. transmit buffer loaded either before after setting this bit. data loaded after setting this bit, length time available load buffer depends starting state (sleep, idle synth), length code, length preamble, packet data rate. example, starting from idle mode fast channel mode with chip codes time abailable (synth start) (preamble) (SOP length) (length byte0 there bytes buffer transmission length field, TXBERR will occur transmission will abort.
Clear Buffer. Writing this register clears transmit buffer. Writing this effect. previous packet fewer bytes) retransmitted setting setting this bit. transmit packet loaded before/after been set, then this should before loading transmit packet buffer. Buffer Full Interupt Enable. TX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. TX_IRQ_STATUS_ADR description. Transmission Complete Interrupt Enable. IRQEN IRQEN must together. TX_IRQ_STATUS_ADR description. Transmit Error Interrupt Enable. IRQEN IRQEN must together. TX_IRQ_STATUS_ADR description.
Mnemonic Default Read/Write Function Used
TX_CFG_ADR Used
Address
0x03
Data Code Data Mode Setting Length Data Code Length. This selects length DATA_CODE_ADR code data portion packet. This ignored when data mode GFSK. chip codes. chip codes.
Bits Data Mode. This field sets data transmission mode. 1-Mbps GFSK. Mode. Mode. Mode. recommended that firmware sets SLOW register ANALOG_CTRL_ADR when using GFSK data rate mode. Bits Setting. This field sets transmit signal strength. dBm, dBm, dBm, dBm, dBm, dBm, -15dBm, dBm, dBm, dBm, dBm.
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Mnemonic Default Read/Write Function
TX_IRQ_STATUS_ADR
Address TXB8 TXB0 TXVERR
0x04
TXB15
state status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Status bits non-atomic (different flags change value different times response single event). Osciliator Stable Status. This when internal crystal oscillator settled (synthesizer sequence starts). Voltage Interrupt Status. This when voltage VBAT below threshold (see PWR_CTL_ADR). This interrupt automatically disabled whenever disabled. When enabled, this reflects voltage VBAT. Buffer Full Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Half Empty Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Empty Interrupt Status. This time that transmit buffer empty. Buffer Error Interrupt Status. triggered either events: When transmit buffer (TX_BUFFER_ADR) empty number bytes remaining transmitted greater than zero. When byte written transmit buffer buffer already full. This cleared setting TX_CTRL_ADR. Transmission Complete Interrupt Status. This triggered when transmission complete. transaction mode enabled then This interrupt triggered immediately after transmission last CRC16. transaction mode enabled, this interrupt Triggered transaction. Reading this register clears this bit. flags change value different times response single event. transaction mode enabled first read this register returns IRQ=1 IRQ=1 IRQ=0 then firmware must execute second read this register determine error occurred examining status TXE. There case when this triggered when there error transmission. first read this register returns then firmware must execute second read this register given transaction. received asserted instead IRQ. Transmit Error Interrupt Status. This triggered when there error transmission. This interrupt only applicable transaction mode. triggered whenever valid packet received within timeout period. Reading this register clears this bit. IRQ, above.
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Mnemonic Default Read/Write Function
RX_CTRL_ADR RSVD
Address
0x05
RXB16 RXB8 RXB1 RXBERR IRQENl IRQEN IRQEN IRQEN IRQEN IRQEN Start Receive. Setting this causes device transition receive mode. necessary, crystal oscillator synthesizer will start automatically ater this set. Firmware must never clear this bit. This must again until after self clears. recommended method exit receive mode when error occurred force STATE then dummy read RX_COUNT_ADR bytes from RX_BUFFER_ADR poll RSSI_ADR.SOP (bit until set. XACT_CFG_ADR RX_ABORT_ADR description. Reserved. Must zero. Buffer Full Interrupt Enable. RX_IRQ_STATUS description. Buffer Half Empty Interrupt Enable. RX_IRQ_STATUS_ADR description.
Buffer Empty Interrupt Enable. RXB1 IRQEN must when RXB8 IRQEN vice versa. RX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. RX_IRQ_STATUS_ADR description. Packet Reception Complete Interrupt Enable. RX_IRQ_STATUS_ADR description. Receive Error Interrupt Enable. RX_IRQ_STATUS_ADR description.
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Mnemonic Default Read/Write Function RX_CFG_ADR
WirelessUSBData Sheet
Address HILO RXOW
0x06
FAST TURN Used Status bits non-atomic (different flags change value different times response single event).
Automatic Gain Control (AGC) Enable. When this set, enabled, controlled circuit. When this cleared controlled manually using bit. Typical applications will clear this during initializination. recommended that this cleared (LNA) unless device will used system where receive data from device using external transmit signals dBm. Noise Amplifier (LNA) Manual Control. When (Bit cleared, this controls state receiver LNA; when set, this effect. Setting this enables LNA; clearing this disables LNA. Device current receive mode slightly Lower when disabled. Typical applications will this during initialization. Receive Attenuator Enable. Setting this enables receiver attenuator. receiver attenuator used de-sensi-tize receiver that only very strong signals received. This should only when disabled manually disabled. HILO. When FAST TURN set, this used select whether device will high frequency channel selected, frequency. When FAST TURN enabled this also controls highlow receiver should Left default value high side receive injection. Typical applications will clear this during initialization. Fast Turn Mode Enable. When this set, HILO determines whether device receives data transmitted above Synthesizer frequency below receiver synthesizer frequency. this mode allows very fast turn-around, because same synthesizer frequency used both transmit receive, thus eliminating synthesizer resetting period between transmit receive. Note that when this set, HILO cleared, received data bits automatically inverted compensate inversion data received "image" frequency. Typical applications will this during initialization. Overwrite Enable. When this set, detected while receive buffer empty, then existing contents receive Buffer lost, packet loaded into receive buffer. When this set, RXOW enabled. this cleared, Then receive buffer over-written packet, whenever receive buffer empty conditions Ignored, possible receive data until previously received packet been completely read from receive buffer. Valid Flag Enable. When this set, receive buffer store bytes data interleaved with valids (data0, valids0, data1, valids1.). Typically, this only when interoperability with first generation devices desired. RX_BUFFER_ADR more detail.
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Mnemonic Default Read/Write Function RX_IRQ_STATUS_ADR
WirelessUSBData Sheet
Address
0x07
SOPDET RXB16 RXB8 RXB1 RXBERRIRQ state Status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Status bits non-atomic (different flags change value different times response single event). particular, standard error handling only effective premature termination transmission exception does leave device inconsistent state. Receive Overwrite Interrupt Status. This triggered when receive buffer over-written packet being received before previous packet been read from buffer. This cleared writing value this register. This condition only possible when RXOWEN RX_CFG_ADR set. This must written firmware before packet read from receive buffer. Start packet detect. This whenever start packet symbol detected. Receiver Buffer Full Interrupt Status. This whevever receive buffer full, cleared otherwise. Receive Buffer Half Full Interrupt Status. This whenever there more bytes remaining receive buffer. Firmware Read exactly eight bytes when reading RXB8 IRQ. when Receive Buffer Empty Interrupt Status. This time that there more bytes receive buffer, cleared receive buffer empty. possible, rare cases, that last byte packet remain buffer even though RXB1 flag cleared. This ONLY happen last byte packet only packet data being read buffer while packet still being received. flag trustworthy under other conditions, bytes prior last. When using RXB1 unloading packet data during reception, user should sure check RX_COUNT_ADR value after IRQ/RXE unload last remaining bytes number bytes unloaded less than reported count, eventhough RXB1 set. Receive Buffer Error Interrupt Status. This triggered ways: When receive buffer empty there attempt read data. When receive buffer full more data received. This flag cleared when received. Packet Receive Complete Interrupt Status. This triggered when packet been received. transaction mode enabled, then this until after transmission ACK. transaction mode enabled then this soon valid packet received. This cleared when this register read. flags change value different times response single event. There cases when this triggered when there error reception. Therefore, firmware should examine IRQ, IRQ, determine receive status. first read this register returns then firmware must execute second read this register determine error occurred examining status IRQ. first read this register returns then firmware must execute second read this register given transaction. Receive Error Interrupt Status. This triggered when there error reception. triggered whenever packet received with CRC16, unexpected detected, packet type (data ACK) mismatch, packet dropped because receive buffer still empty when next packet starts. exact cause error determined reading RX_STATUS_ADR. This cleared when this register read.
RXOW
must
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Mnemonic Default Read/Write Function RX_STATUS_ADR
WirelessUSBData Sheet
Address CRC0 Code
0x08 Data Mode
expected that firmware does read this register until after self clears. Status bits non-atomic (different flags change value different times response single event) Packet Type. This when received packet packet, cleared when received packet standard packet. Receive Packet Type Error. This when packet type received what expected cleared when packet type received expected. example, data packet expected received, this will set. Unexpected EOP. This when detected before expected data length fields have been received. This cleared when pattern next packet been received. This includes case where there invalid bits detected length field length field forced Zero-seed This whenever last received packet zero seed. This when last received packet incorrect. Receive Code Length. This indicated DATA_CODE_ADR code length used last correctly received packet. 64-chip code, 32-chip code.
Receive Data Mode. These bits indicate data mode last correctly received packet. 1-Mbps GFSK DDR. Valed. These bits apply unframed packets.
Mnemonic Default Read/Write Function
RX_COUNT_ADR
Address Count
0x09
Count bits non-atomic (updated different times). Bits This register contains total number payload bytes received during reception current packet. After packet reception complete, this register will match value RX_LENGTH_ADR unless there packet error. This register cleared when RX_LENGTH_ADR automatically loaded, length enabled, after SOP. Count should read when RX_GO=1 during transaction.
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Mnemonic Default Read/Write Function RX_LENGTH_ADR
WirelessUSBData Sheet
Address
0x0A
Length
Lengths bits non-atomic (different flags change value different times response single event). Bits This register contains length field which updated with reception length field (shortly after start packet detected). there error received length field, 0x00 loaded instead, except when using GFSK datarate, error flagged.
Mnemonic Default Read/Write Function VBAT
PWR_CTRL_ADR LVIRQ Used
Address OUTV
0x0B
Power Management Unit (PMU) Enable. Setting this enables PMU. When disabled, enabled voltage above value Bits this register, VREG internally connected VBAT pin. enabled VBAT voltage below value OUTV, then will boost VREG voltage less than value OUTV.
Voltage Interrupt Enable. Setting this enables interrupt. When this interrupt enabled, VBAT voltage falls below threshold then voltage interrupt will generated. available when device sleep mode. event automatically disabled whenever disabled. Sleep Mode Enable. this set, will continue operate normally when device sleep mode. this set, Then disabled when device sleep mode. this case, VBAT below OUTV voltage set, when device enters sleep mode VREG voltage falls VBAT voltage VBAT voltage VREG capacitors discharge.
Bits Voltage Interrupt Threshold. This field sets voltage VBAT which triggered. 1.8V; 2.0V; 2.2v; OUTV voltage. Bits Output Voltage. This field sets minimum output voltage PMU. 2.4V; 2.5V; 2.6V; 2.7V. When active, voltage output VREG will never less than this voltage provided that total load VREG less Than specified maximum value, voltage VBAT greater than specified minimum value.
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Mnemonic Default Read/Write Function XTAL_CTRL_ADR XOUT
WirelessUSBData Sheet
Address XSIRQ Used Used FREQ
0x0C
Bits XOUT Function. This field selects between different functions XOUT pin. Clock frequency XOUT FREQ: Active Control: Radio data serial stream. this option selected configured 3-wire mode then MISO will output serial clock associated with this data stream: GPIO. disable this output, GPIO mode, GPIO state IO_CFG_ADR. Crystal Stable Interrupt Enable. This enables interrupt. When enabled, this interrupt generates event when crystal stabilized after device woken from sleep mode. This event cleared writing zero this bit.
Bits XOUT Frequency. This field sets frequency output XOUT when XOUT MHz; MHz, 3MHz, MHz, 0.75 MHz; other values defined.
Mnemonic Default Read/Write Function Function
Used
IO_CFG_ADR Channel
Address MISO XOUT PACTL PACTL GPIO 3PIN
0x0D GPIO
GPIO input, output mode must open drain, written corresponding output register bit. Drive Strength. Setting this configures open drain output. Clearing this configures standard CMOS output, with output drive voltage being equal voltage. Polarity. Setting this configures signal polarity active HIGH. Clearing this configures signal polarity active low. MISO Drive Strength. Setting this configures MISO open drain output. Clearing this configures MISO standard CMOS output, with output drive voltage being equal voltage. XOUT Drive Strength. Setting this configures XOUT open drain output. Clearing this configures XOUT standard CMOS output, with output drive voltage being equal voltage. PACTL Drive Strength. Setting this configures PACTL open drain output. Clearing this configures PACTL standard CMOS output, with output drive voltage being equal voltage. PACTL Function. When this PACTL available GPIO. Mode. When this cleared, interface acts standard 4-wire Slave interface. When this set, interface operates "3-Wire Mode" combining MISO MOSI same (SDAT), MISO available GPIO pin. Function. When this cleared, asserted when active; polarity this signal configurable POL. When this set, available GPIO pin, function multiplexed onto MOSI pin. this case signal state presented MOSI whenever signal inactive (HIGH). Usable channels subject regulation
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WirelessUSBData Sheet
Mnemonic Default Read/Write Function
XOUT
GPIO_CTRL_ADR MISO
Address PACTL XOUT MISO PACTL
0x0E
GPIO input, output mode must open drain, written corresponding output register bit. XOUT Output. When XOUT configured GPIO, state this sets output state XOUT pin. MISO Output. When MISO configured GPIO, state this sets output state MISO pin. PACTL Output. When PACTL configured GPIO, state this sets output state PACTL pin. Output. When configured GPIO, state this sets output state pin. XOUT Input. state this reflects voltage XOUT pin. MISO Input. state this reflects voltage MISO pin. PACTL Input. state this reflects voltage PACTL pin. Input. state this reflects voltage pin.
Mnemonic Default Read/Write Function
XACT_CFG_ADR
Address STATE
0x0F
Used
Acknowledge Enable. When this set, packet automatically transmitted whenever valid packet received; this case device considered transaction mode. After transmission packet, device automatically transitions STATE. When this cleared, device transitions directly STATE immediately after packet transmission. This affects both transmitting receiving devices. Force State. Setting this forces transition state STATE. setting desired STATE same time setting this device forced immediately transition from current state other state. This automatically cleared upon completion. Firmware MUST never force STATE while set, when already been received (packet reception already progress).
Bits Transaction State. This field defines mode which device transitions after receiving transmitting packet. Sleep Mode; Idle Mode; Synth Mode (TX); Synth Mode (RX); Mode. normal use, this field will typically when device transmitting packets, when device receiving packets. Note that when device transitions receive mode STATE, receiver must still armed setting before device begin receiving data. system only support packets <=16 bytes then firmware should examine determine status packet. system supports packets bytes ensure that STATE sleep, force RXF=1, perform receive operation, force RXF=0, necessary STATE back sleep. Bits Timeout. When device configured transaction mode, this field sets timeout period after transmission packet during which must correctly received order prevent transmit error condition from being detected. This
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timeout period expressed terms number SOP_CODE_ADR code lengths; set, then timeout period this value multiplied cleared then timeout this value multiplied 12x; SOP_CODE_ADR code length. ACK_TO must greater than Data Code Length (only 8DR) Preamble Length Code Length (x2).
Mnemonic Default Read/Write Function
FRAMING_CFG_ADR
Address
0x10
Enable. When this set, each transmitted packet begins with field, only packets beginning with valid field will received. this cleared, field will generated when packet transmitted, packet reception will begin whenever successive correlations against DATA_CODE_ADR code detected. Code Length. When this SOP_CODE_ADR code length chips. When this cleared SOP_CODE_ADR code length chips. Packet Length Enable. When this 8-bit value contained TX_LENGTH_ADR transmitted immediately after field. receive mode, bits immediately following field interpreted length packet. When this cleared packet length field transmitted. always sends packet length field (LEN setting ignored). GFSK requires user
Bits Correlator Threshold. This receive data correlator threshold used when attempting detect symbol. There single threshold SOP_CODE_ADR code. This threshold applied independently each SOP1 SOP2 fields. When set, bits this field used. When cleared, most significant disregarded. Typical applications configure SOP32 SOP64.
Mnemonic Default Read/Write Function Bits Bits Used.
Used
DATA32_THOLD_ADR Used
Address Used TH32
0x11
Used
Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) Typical applications configure TH32 05h.
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WirelessUSBData Sheet
Mnemonic Default Read/Write Function Bits Bits Used. Used
DATA64_THOLD_ADR Used Used
Address TH64
0x12
Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) Typical applications configure TH64 0Eh.
Mnemonic Default Read/Write Function
RSSI_ADR Used
Address RSSI
0x13
Received Signal Strength Indicator (RSSI) reading taken automatically when symbol detected. addition, RSSI reading taken whenever RSSI_ADR read. contents this register valid after device configured receive mode until either symbol detected, register (re)read. conversion occur often once every 12-s. approximate slope curve dB/count, guaranteed. desired measure background signal strength channel before packet been received then should perform "dummy" read this register, results which should discarded. This "dummy" read will cause RSSI measurement taken, therefore subsequent readings register will yield valid data. RSSI Reading. When set, this indicates that reading RSSI field taken when symbol detected. When cleared, this indicates that reading stored RSSI field triggered previous read this register. State. This indicates state when RSSI reading taken. When cleared, this indicates that disabled when RSSI reading taken; this indicates that enabled when RSSI reading taken.
Bits RSSI Reading. This field indicates instantaneous strength signal being received time that RSSI reading taken. larger value indicates stronger signal. signal strength measured signal configured channel, measured after stage.
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Mnemonic Default Read/Write Function EOP_CTRL_ADR
WirelessUSBData Sheet
Address HINT
0x14
set, then contents this register have effect. cleared, then this register used configure (end packet) condition detected. Hint Enable. When set, this will cause detected correlations have been detected number symbol periods HINT field last received bytes match calculated CRC16 previously received bytes. this mode reduces chance non-correlations middle packet from being detected condition.
Bits Hint Symbol Count. minimum number symbols consecutive non-correlations which last bytes checked against calculated CRC16 detect condition. Bits Symbol Count. condition deemed exist when number consecutive non-correlations detected.
Mnemonic Default Read/Write Function
CRC_SEED_LSB_ADR
Address
0x15
SEED
CRC16 seed allows different devices generate recognize different CRC16s same payload data. transmitter receiver randomly selected CRC16 seed, probability correctly receiving data intended different receiver 1/65535, even other transmitter/receiver using same SOP_CODE_ADR codes channel. Bits CRC16 Seed Least Significant Byte. starting value CRC16 calculation.
Mnemonic Default Read/Write Function Bits
CRC_SEED_MSB_ADR
Address
0x16
SEED CRC16 Seed Most Significant Byte. starting value CRC16 calculation.
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Mnemonic Default Read/Write Function Bits
TX_CRC_LSB_ADR
Address
0x17
Calculated CRC16 LSB. CRC16 that calculated last transmitted packet. This value only valid after packet transmission complete.
Mnemonic Default Read/Write Function Bits
TX_CRC_MSB_ADR
Address
0x18
Calculated CRC16 MSB. CRC16 that calculated last transmitted packet. This value only valid after packet transmission complete.
Mnemonic Default Read/Write Function Bits
RX_CRC_LSB_ADR
Address
0x19
Received CRC16 LSB. CRC16 field extracted from last received packet. This value valid whether CRC16 field matched calculated CRC16 received packet.
Mnemonic Default Read/Write Function Bits
RX_CRC_MSB_ADR
Address
0x1A
Received CRC16 MSB. CRC16 field extracted from last received packet. This value valid whether CRC16 field matched calculated CRC16 received packet.
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WirelessUSBData Sheet
Mnemonic Default Read/Write Function Bits
TX_OFFSET_LSB_ADR STRIM
Address
0x1B
least significant bits synthesizer offset value. This 12-bit complement signed number which used offset transmit frequency device ±1.5 MHz. positive value increases transmit frequency, negative value reduces transmit frequency. value increases transmit frequency 732.6 value decreases transmit frequency 732.6 value 0x0555 increases transmit frequency MHz; value 0xAAB decreases transmit frequency MHz. Typically, this register loaded with 0x55 during initialization. Typically this feature used avoid need change synthesizer frequency when switching between frequency offset from synthesizer frequency; therefore, transmitting with offset allows same synthesizer frequency used both transmit receive.
Synthesizer offset effect receive frequency.
Mnemonic Default Read/Write Function Bits Bits Used Used
TX_OFFSET_MSB_ADR Used Used Used
Address STRIM
0x1C
most significant bits synthesizer trim value. Typically, this register loaded with 0x05 during initialization. MODE_OVERRIDE_ADR RSVD Address AWAKE Used Used 0x1D
Mnemonic Default Read/Write Function Bits
RSVD
Reserved. Must zero. Manually Initiate Synthesizer. Setting this forces synthesizer start. Clearing this effect. this operate correctly, oscillator must running before this set. Force Awake. Force device sleep mode. Setting both bits this field forces oscillator keep running times regardless STATE setting. Clearing both these bits disables this function. Used. Reset. Setting this forces full reset device. Clearing this effect.
Bits
Bits
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Mnemonic Default Read/Write Function
RX_OVERRIDE_ADR RXTX RXACK RXDR
Address RXCRC
0x1E Used
CRC0
This register provides ability over-ride some automatic features device. When this set, device uses transmit synthesizer frequency rather than receive synthesizer frequency given channel when automatically entering receive mode. When this enabled, transmission packet delayed Force Expected Packet Type. When this set, device receive mode, device configured receive packet data rate defined TX_CFG_ADR. Force Receive Data Rate. When this set, receiver will ignore data rate encoded symbol, will receive data data rate defined TX_CFG_ADR. Reject packets with zero-seed CRC16. Setting this causes receiver reject packets with zero-seed, accept only packets with CRC16 that matches seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. CRC16 checker disabled. packets with CRC16 enabled received, CRC16 will treated payload data stored receive buffer. Accept CRC16. Setting this causes receiver accept packets with CRC16 that match seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. sent regardless condition received CRC16. Used.
Mnemonic Default Read/Write Function
TX_OVERRIDE_ADR
Address RSVD TXACK OVRD TXCRC RSVD
0x1F
This register provides ability over-ride some automatic features device. When this set, device uses receive synthesizer frequency rather than transmit synthesizer frequency given channel when automatically entering transmit mode. Force Preamble. When this set, device will transmit continuous repetition preamble pattern (see PREAMBLE_ADR) after set. This mode useful some regulatory approval procedures. Firmware should MODE_OVERRIDE_ADR exit this mode.
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Reserved. Must zero.
WirelessUSBData Sheet
Transmit Packet. When this set, device sends packet when set. Override. TX_CFG_ADR determine data rate CRC16 used when transmitting packet. Disable Transmit CRC16. When set, CRC16 field present transmitted packets. Reserved. Must zero. Data Invert. When this transmit bitstream inverted.
Mnemonic Default Read/Write Function
RSVD
XTAL_CFG_ADR RSVD
Address RSVD RSVD START RSVD RSVD
0x26 RSVD
This register provides ability over-ride some automatic features device. Reserved. Must zero Crystal Startup Delay. Setting this bit, sets crystal startup delay 150uSec handle warm restarts crystal. Firmware MUST this during initialization. Bits Reserved. Must zero.
Mnemonic Default Read/Write Function RSVD
CLK_OVERRIDE_ADR RSVD RSVD RSVD RSVD
Address RSVD
0x27 RSVD
This register provides ability over-ride some automatic features device. Bits Reserved. Must zero Force Receive Clock. Streaming applications MUST this during receive mode, otherwise this cleared. Reserved. Must zero.
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Mnemonic Default Read/Write Function CLK_EN_ADR RSVD
WirelessUSBData Sheet
Address RSVD RSVD RSVD RSVD
RSVD
0x28 RSVD
This register provides ability over-ride some automatic features device. Bits Reserved. Must zero Force Receive Clock Enable. Streaming applications MUST this during initialization. Reserved. Must zero.
Mnemonic Default Read/Write Function RSVD
RX_ABORT_ADR RSVD ABORT RSVD RSVD
Address RSVD RSVD
0x29 RSVD
This register provides ability over-ride some automatic features device. Bits Reserved. Must zero Receive Abort Enable. Typical applications will disrupt pending receive first setting this bit, otherwise this cleared.
Reserved. Must zero.
Mnemonic Default Read/Write Function
AUTO_CAL_TIME_ADR
Address
0x32
AUTO_CAL_TIME
This register provides ability over-ride some automatic features device. Bits Auto Time. Firmware MUST write this register during initialization.
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Mnemonic Default Read/Write Function AUTO_CAL_OFFSET_ADR
WirelessUSBData Sheet
Address
0x35
AUTO_CAL_OFFSET
This register provides ability over-ride some automatic features device. Bits Auto Offset. Firmware MUST write this register during initialization.
Mnemonic Default Read/Write Function
RSVD
ANALOG_CTRL_ADR RSVD
Address RSVD RSVD RSVD RSVD
0x39 SLOW
This register provides ability over-ride some automatic features device. Bits Reserved. Must zero Receive Invert. When set, incoming receive data inverted. Firmware MUST this when interoperability with JUNO (CYUSB6934/35) desired. Slow. When set, synth setting time channels same slow channels. recommended that firmware this When using GFSK data mode.
Register Files Files written read from using non-incrementing burst read write transactions. most cases accessing file destructive; file must completely read/written, otherwise contents altered. When accessing file registers, bytes presented least significant byte first.
Mnemonic Length Default TX_BUFFER_ADR Bytes Address 0x20
transmit buffer FIFO. Writing this file adds byte packet being sent. Writing more bytes this file than packet length TX_LENGTH_ADR will have effect, these bytes will lost. FIFO accumulates data until reset TX_CTRL_ADR. previously sent packet, bytes less, transmitted TX_GO without resetting FIFO. contents TX_BUFFER_ADR affected transmission Auto ACK.
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Mnemonic Length Default RX_BUFFER_ADR Bytes
WirelessUSBData Sheet
Address
0x21
receive buffer FIFO. Received bytes read from this file register time that empty, when reading from this file register before packet been completely received care must taken ensure that error packets (for example with CRC16) handled correctly. When receive buffer configured overwritten packets (the alternative packets discarded receive buffer empty), similar care must taken verify after packet been read from buffer that part overwritten newly received packet while this file register being read. When RX_CFG_ADR set, bytes this file register alternate-the first byte read data, second byte valid flag each first byte, third byte data, fourth byte valid flags, etc. modes valid flag correlation coefficient exceeded correlator threshold, cleared not. mode, valid flags byte indicates whether correlation coefficient corresponding received symbol exceeded threshold. seven LSBs contain number erroneous chips received data.
Mnemonic Length Default
SOP_CODE_ADR Bytes
0x17FF9E213690C782
Address
0x22
When using chip SOP_CODE_ADR codes, only first four bytes this register used; order complete file write process, these four bytes must followed four bytes "dummy" data. However, class codes known "multiplicative codes" used; there chip codes with good auto-correlation cross-correlation properties where least significant chips themselves have good autocorrelation cross-correlation properties when used 32-chip codes. this case same eight-byte value loaded into this file used both chip chip symbols. When reading this file, eight bytes must read; fewer than eight bytes read from file, contents file will have been rotated number bytes read. This applies writes, well. Recommended Codes:
0x91CCF8E291CC373C 0x0FA239AD0FA1C59B 0x2AB18FD22AB064EF 0x507C26DD507CCD66 0x44F616AD44F6E15C 0x46AE31B646AECC5A 0x3CDC829E3CDC78A1 0x7418656F74198EB9 0x49C1DF6249C0B1DF 0x72141A7F7214E597
Mnemonic Length Default DATA_CODE_ADR Bytes
Address
0x23
GFSK mode, this file register ignored. 64-SDR mode, only first eight bytes used. 32-DDR mode, only eight bytes used. format these eight bytes: where represents unused locations. Example: where "B86BC0DC" represents AAAAAAAA, "00000000" represents unused locations, "B2BB092B" represents BBBBBBBB, "00000000" represents unused locations. 64-DDR modes, sixteen bytes used.
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WirelessUSBData Sheet
When reading this file, sixteen bytes must read; fewer than sixteen bytes read from file, contents file will have been rotated number bytes read. This applies writes, well. Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation cross-correlation properties, recommended that such sequences used; default value this register such sequence. typical applications, devices same DATA_CODE_ADR codes, devices systems addressed using different SOP_CODE_ADR codes; such cases never necessary change contents this register from default value. Typical applications should default code.
Mnemonic Length Default
PREAMBLE_ADR Bytes
0x333302
Address
0x24
byte number repetitions preamble sequence that transmitted. preamble disabled writing 0x00 this byte. byte Least significant eight chips preamble sequence byte Most significant eight chips preamble sequence using 64-SDR communicate with CYWUSB69xx devices, number repetitions four optimum performance When reading this file, three bytes must read; fewer than three bytes read from file, contents file will have been rotated number bytes read. This applies writes, well.
Mnemonic Length Default
MFG_ID_ADR Bytes
Address
0x25
minimize ~190A current consumption (default), execute "dummy" single-byte write this address with zero data stage after contents have been read. Non-zero enable reading fuses. Zero disable reading fuses.
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WirelessUSBData Sheet
Characteristics
Interface
Parameter SCK_CYC
Description Clock Period Clock High Time Clock Time Input Data Set-up Time Input Data Hold Time Output Data Valid Time Output Data Tri-state (MOSI from Slave Select Deassert) Slave Select Set-up Time before first positive edge SCK[14] Slave Select Hold Time after last negative edge Slave Select Minimum Pulse Width Slave Select Set-up Time Hold Time Minimum pulse width
238.1
Typ.
Max.
Unit
SCK_HI SCK_LO DAT_SU DAT_HLD DAT_VAL DAT_VAL_TRI SS_SU SS_HLD SS_PW SCK_SU SCK_HLD RESET
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Timing
WirelessUSBData Sheet
Notes values guaranteed voltage exceed VIO. CLOAD must start time goes low, otherwise success transactions guaranteed.
Test Loads Waveforms Digital Pins
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WirelessUSBData Sheet
MECHANICAL CHARACTERISTICS:
Item Description
Material Layers Connector Type Number Flammability Rating UGQLUE4US Dimensions Antenna Cable Connector User Serviceable Parts
Specification
FR-4 UL94 1.5" 0.66" 0.224" (38.1mm 16.8mm mm*) *board board height None
MECHANICAL DRAWINGS:
Physical Dimensions:
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WirelessUSBData Sheet
ORDERING INFORMATION:*
Typical Applications
Unigen Product Group Wireless Form Factor Process Tech WirelessUSB Tech Voltage Antenna
(CYRF6936)
50=5.0Vdc
Blank=Mini Coaxial Integ Antenna
*Module based Cypress Semiconductor CYRF6936-48 WirelessUSBLP 2.4GHz DSSS Radio device.
Contact your Unigen Sales Representative additional information visit NexusWireless Products section site (www.unigen.com).
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WirelessUSBData Sheet
CONTACT INFORMATION: CORPORATE HEADQUARTERS
Unigen Corporation 45388 Warm Springs Boulevard Fremont, 94539 Telephone: Fax: Email: Web: Customer Comment:
1.510.688.2088 1.510.661.2788 Support@unigen.com www.unigen.com 1.800.826.0808
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CY7C64215
enCoReIII Full Speed Controller
Features
Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-bit Accumulate 5.25V Operating Voltage Temperature Range: +70°C Advanced Peripherals (enCoReIII Blocks) Analog enCoRe Block Provides: 14-bit ADCs Digital enCoRe Blocks Provide: 8-bit PWMs Full-Duplex UART Multiple Masters Slaves Connectable GPIO Pins Complex Peripherals Combining Blocks Full-Speed Mbps) Four Unidirectional Endpoints Bidirectional Control Endpoint Compliant Dedicated Byte Buffer External Crystal Required Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations 25-mA Sink GPIO Pull-up, Pull-down, High- Strong, Open Drain Drive Modes GPIO Configurable Interrupt GPIO Precision, Programmable Clocking Internal 24-/48-MHz Oscillator Internal Oscillator Watchdog Sleep 0.25% Accuracy with External Components Additional System Resources Slave, Master, Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoCDesigner) Full-Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
enCoRe Core
Figure 1-1. enCoRe Block Diagram Cypress Semiconductor Corporation Document 38-08036 Rev. Champion Court Jose, 95134-1709 408-943-2600 Revised September 2005
CY7C64215
Applications
Sleep timer WDT. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into enCoRe III. systems, will self-tune ±0.25% accuracy communication. enCoRe GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
devices Mice (Optomechanical, Optical, Trackball) Keyboards Joysticks Gaming Game Pads Console Keyboards General Purpose Barcode Scanners Terminal Consumer Electronics Toys Remote Controls Serial
Digital System
Digital System composed digital enCoRe blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references.
Port Port Port Port Port Port Port
enCoRe Functional Overview
enCoRe based flexible PSoC architecture full-featured, full-speed Mbps) part. Configurable analog, digital, interconnect circuitry enable high level integration host consumer, communication applications. This architecture allows user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included both 28-pin SSOP 56-pin packages. enCoRe architecture, illustrated Figure 1-1, comprised four main areas: enCoRe Core, Digital System, Analog System, System Resources including full-speed port. Configurable global busing allows device resources combined into complete custom system. enCoRe CY7C64215 have seven ports that connect global digital analog interconnects, providing access digital blocks analog block.
Digital Clocks From Core
System
Analog System
DIGITAL SYSTEM
Digital enCoRe Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
GIE[7:0] GIO[7:0]
GlobalDigital Interconnect
GOE[7:0] GOO[7:0]
enCoRe Core
enCoRe Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. utilizes interrupt controller with vectors, simplify programming real-time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, SRAM data storage, EEPROM emulated using Flash. Program Flash utilizes four protection levels blocks bytes, allowing customized software protection. enCoRe incorporates flexible internal clock generators, including 24-MHz (internal main oscillator) accurate over temperature voltage. 24-MHz also doubled digital system. lowpower (internal low-speed oscillator) provided
Figure 3-1. Digital System Block Diagram Digital peripheral configurations include those listed below. Full-Speed Mbps) PWMs (8-bit) UART 8-bit with selectable parity master slave slave multi-master digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller.
Analog System
Analog System composed configurable block, comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very
Document 38-08036 Rev.
Page
CY7C64215
flexible customized support specific application requirements. enCoRe analog function supports Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Analog blocks arranged column three, which includes (Continuous Time B01) (Switched Capacitor ASC10 ASD20 ASD11 ASC21) blocks, shown Figure 3-2.
xcep
AGNDIn RefIn Analog
decimator, voltage detection, power-on reset. Brief statements describing merits each resource follow. Full-Speed Mbps) with configurable endpoints bytes RAM. external components required except series resistors. Wider than commercial temperature operation (-10°C +85°C). multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, assist both general math well digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. HAPI interface 8-bit width accommodate data transfer with external microcontroller similar device.
I0[1:0] I1[1:0]
enCoRe Device Characteristics
enCoRe devices have digital blocks analog blocks. following table lists resources available specific enCoRe device. Table 3-1. enCoRe Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size Flash Size
Part Number
CY7C64215 -28PVXC
ital RefHi efer andg
CY7C64215 -56LFXC
Getting Started
face
Figure 3-2. Analog System Block Diagram 3.3.1 Analog Multiplexer System
Analog connect every GPIO ports 0-5. Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. split into sections simultaneous dual-channel processing. additional analog input multiplexer provides second path bring Port pins analog array.
quickest path understanding enCoRe silicon reading this data sheet using PSoC Designer Integrated Development Environment (IDE). This data sheet overview enCoRe integrated circuit presents specific pin, register, electrical specifications. enCoRe based architecture CY8C24794. in-depth information, along with detailed programming information, reference PSoCMixed-Signal Array Technical Reference Manual. up-to-date Ordering, Packaging, Electrical Specification information, reference latest enCoRe device data sheets http://www.cypress.com.
Additional System Resources
Development Kits
System Resources provide additional capability useful complete systems. Additional resources include multiplier, Document 38-08036 Rev.
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store Page
CY7C64215
contains development kits, compilers, accessories enCoRe development. Cypress Online Store site http://www.cypress.com, click Online Store shopping cart icon bottom page, click (Universal Serial Bus) view current list available items.
5.1.1
PSoC Designer Software Subsystems
Device Editor
Development Tools
Device Editor subsystem allows user select different onboard analog digital components called user modules using enCoRe blocks. Examples user modules ADCs, SPIM, UART, PWMs. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. PSoC Designer sets power-on initialization tables selected enCoRe block configurations creates source code application framework. framework contains software operate selected components and, project uses more than operating configuration, contains routines switch between different sets enCoRe block configurations time. PSoC Designer print configuration sheet given project configuration during application programming conjunction with Device Data Sheet. Once framework generated, user application-specific code flesh framework. It's also possible change selected components regenerate framework. 5.1.2 Application Editor
PSoC Designer Microsoft® Windows®-based, integrated development environment enCoRe III. PSoC Designer application runs Windows 4.0, Windows 2000, Windows Millennium (Me), Windows (Refer PSoC Designer Functional Flow diagram below.) PSoC Designer helps customer select operating configuration enCoRe III, write application code that uses enCoRe III, debug application. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, CYASM macro assembler CPUs. PSoC Designer also supports high-level language compiler developed specifically devices family.
PSoCDesigner
Graphical Designer Interface
Context Sensitive Help
Commands
Application Editor edit your language Assembly language source code. also assemble, compile, link, build. Assembler. macro assembler allows assembly code merged seamlessly with code. link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compiler. language compiler available that supports enCoRe family devices. Even have never worked language before, product quickly allows create complete programs enCoRe devices. embedded, optimizing compiler provides features tailored enCoRe architecture. comes complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. 5.1.3 Debugger
Results
portable Design Database Device Database Application Database Project Database User odules Library PSoC Configuration Sheet
PSoCDesigner Core Engine
Manufacturing Information File
ulation
In-Circuit Emulator
Device Programm
PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing designer test program physical system while providing internal view enCoRe device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. 5.1.4 Online Help System
Figure 5-1. PSoC Designer Subsystems
online help system displays online, context-sensitive help user. Designed procedural quick reference, Document 38-08036 Rev. Page
CY7C64215
each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started. with point-and-click simplicity. Next, build signal chains interconnecting user modules each other pins. this stage, also configure clock source connections enter parameter values directly selecting values from drop-down menus. When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides high-level user module functions.
5.2.1
Hardware Tools
In-Circuit Emulator
low-cost, high-functionality Cube available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal will operate with enCoRe devices.
DeviceEditor
User Module Selection Placement Parameter -ization Source Code Generator
Designing with User Modules
development process enCoRe device differs from that traditional fixed-function microprocessor. configurable analog digital hardware blocks give enCoRe architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called enCoRe Blocks, have ability implement wide variety user-selectable functions. Each block several registers that determine function connectivity other blocks, multiplexers, buses pins. Iterative development cycles permit adapt hardware well software. This substantially lowers risk having select different part meet final design requirements. speed development process, PSoC Designer Integrated Development Environment (IDE) provides library pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties. User Module library contains peripherals: ADCINC, PWM8, UART, SPIM, SPIS, LCD, I2CHW, I2CM USBFS. Each user module establishes basic register settings that implement selected function. also provides parameters that allow tailor precise configuration your particular application. example, Pulse Width Modulator User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit designer establish pulse width duty cycle. User modules also provide tested software development time. user module application programming interface (API) provides high-level functions control respond hardware events run-time. also provides optional interrupt service routines that adapted needed. functions documented user module data sheets that viewed directly PSoC Designer IDE. These data sheets explain internal operation user module provide performance specifications. Each data sheet describes each user module parameter documents setting each register controlled user module. development process starts when open project bring Device Editor, graphical user interface (GUI) configuring hardware. pick user modules need your project them onto PSoC blocks Document 38-08036 Rev.
Generate Application
ApplicationEditor
Project Manager Source Code Editor Build Manager
Build
Debugger
Interface Storage Inspector Event Breakpoint Manager
Figure 6-1. User Module Source Code Development Flows next step write your main program, subroutines using PSoC Designer's Application Editor subsystem. Application Editor includes Project Manager that allows open project source code files (including generated code files) from hierarchal view. source code editor provides syntax coloring advanced edit features both assembly language. File search capabilities include simple string searches recursive "grep-style" patterns. single mouse click invokes Build Manager. employs professional-strength "makefile" system automatically analyze file dependencies compiler assembler necessary. Project-level options control optimization strategies used compiler linker. Syntax errors displayed console window. Double clicking error message takes directly offending line source code. When correct, linker builds file image suitable programming. Page
CY7C64215
last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE CUBE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Acronym
Description
IPOR PPOR PSoC SRAM
internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor static random access memory
Document Conventions
Acronyms Used
following table lists acronyms that used this document.
Acronym Description
alternating current analog-to-digital converter application programming interface central processing unit continuous time external crystal oscillator
Units Measure
EEPROM electrically erasable programmable read-only memory GPIO full scale range general purpose graphical user interface human body model in-circuit emulator
units measure table located Electrical Specifications section. Table 11-1 page lists abbreviations used measure enCoRe devices.
Numeric Naming
Hexidecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexidecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (e.g., 01010100b' `01000011b'). Numbers indicated decimal.
Document 38-08036 Rev.
Page
CY7C64215
56-Pin Part Pinout
CY7C64215 enCoRe device available 56-pin package which listed illustrated following table. Every port (labeled with "P") capable Digital However, capable Digital
Table 8-1. 56-Pin Part Pinout (MLF*)
Type Digital Analog Power Power
CY7C64215 56-Pin enCoRe Device
Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] Description Direct switched capacitor block input. Direct switched capacitor block input.
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP-SCLK. Ground connection.
Serial Data (SDA), ISSP-SDATA.
Type Digital Analog Power Power
P4[6] P2[0] Direct switched capacitor block input. P2[2] Direct switched capacitor block input. P2[4] External Analog Ground (AGND) input.
LEGEND Analog, Input, Output, Analog Input. package center that must connected ground (Vss).
Document 38-08036 Rev.
SCL, SDA, SCL,
Supply voltage.
Name P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5]
Description External Voltage Reference (VREF) input. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Ground connection. Analog column input, integration input Analog column input column output, integration input P0[3] Analog column input column output. P0[1] Analog column input. P2[7] P2[5]
P7[7] P7[0] SDA, P1[0] P1[2] P1[4] P1[6]
P1[7] P1[5] P1[3] P1[1]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]
P2[5], P2[7], P0[1], P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6], P2[4],
(Top View)
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
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CY7C64215
28-Pin Part Pinout
CY7C64215 enCoRe device available 28-pin package which listed illustrated following table. Every port (labeled with "P") capable Digital However, capable Digital
Table 9-1. 28-Pin Part Pinout (SSOP)
Type Digital Analog Name Description Power Ground connection P0[7] Analog column input, integration input IO,M P0[5] Analog column input column output, integration input IO,M P0[3] Analog column input column output. P0[1] Analog column input. P2[5] P2[3] Direct switched capacitor block input. P2[1] Direct switched capacitor block input. P1[7] Serial Clock (SCL). P1[5] Serial Data (SDA). P1[3] P1[1] Serial Clock (SCL), ISSP-SCLK. Power Ground connection Power Supply voltage. P1[0] Serial Data (SDA), ISSP-SDATA. P1[2] P1[4] P1[6] P2[0] Direct switched capacitor block input. P2[2] Direct switched capacitor block input. P2[4] External Analog Ground (AGND) input. P0[0] Analog column input. P0[2] Analog column input column output. P0[4] Analog column input column output. P0[6] Analog column input. Power Vdd] Supply voltage.
CY7C64215 28-Pin enCoRe Device
AI,P0[7] AIO,P0[5] AIO,P0[3] AI,P0[1] P2[5] AI,P2[3] AI,P2[1] P1[7] SCL, I2CSDA,P1[5] P1[3] I2CSCL, P1[1]
SSOP
P0[6],AI P0[4],AI P0[2],AI P0[0],AI P2[4] P2[2],AI P2[0],AI P1[6] P1[4] P1[2] P1[0],I2CSDA
LEGEND Analog, Input, Output, Analog Input. package center that must connected ground (Vss).
10.0 Register Reference
10.1 Register Conventions
10.1.1 Abbreviations Used
10.2 Register Mapping Tables
enCoRe device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank
Note following register mapping tables, blank fields Reserved should accessed.
register conventions specific this section listed following table.
Convention Description
Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific Page
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10.3 Register Bank Table: User Space
Addr (0,Hex) Access Name Addr (0,Hex) Access PMA0_DR PMA1_DR PMA2_DR PMA3_DR PMA4_DR PMA5_DR PMA6_DR PMA7_DR USB_SOF0 USB_SOF1 USB_CR0 USBIO_CR0 USBIO_CR1 EP1_CNT1 EP1_CNT EP2_CNT1 EP2_CNT EP3_CNT1 EP3_CNT EP4_CNT1 EP4_CNT EP0_CR EP0_CNT EP0_DR0 EP0_DR1 EP0_DR2 EP0_DR3 EP0_DR4 PRT7DR EP0_DR5 PRT7IE EP0_DR6 PRT7GS EP0_DR7 PRT7DM2 DBB00DR0 AMX_IN DBB00DR1 AMUXCFG DBB00DR2 DBB00CR0 ARF_CR DBB01DR0 CMP_CR0 DBB01DR1 ASY_CR DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 TMP_DR0 DCB03DR1 TMP_DR1 DCB03DR2 TMP_DR2 DCB03CR0 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access Name Addr (0,Hex) Access
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
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10.4 Register Bank Table: Configuration Space
Addr Addr Access Name (1,Hex) (1,Hex) PRT0DM0 PMA0_WA PRT0DM1 PMA1_WA PRT0IC0 PMA2_WA PRT0IC1 PMA3_WA PRT1DM0 PMA4_WA PRT1DM1 PMA5_WA PRT1IC0 PMA6_WA PRT1IC1 PMA7_WA PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PMA0_RA PRT4DM1 PMA1_RA PRT4IC0 PMA2_RA PRT4IC1 PMA3_RA PRT5DM0 PMA4_RA PRT5DM1 PMA5_RA PRT5IC0 PMA6_RA PRT5IC1 PMA7_RA PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN CMP_GO_EN DBB01IN CMP_GO_EN1 DBB01OU AMD_CR1 ALT_CR0 DCB02FN DCB02IN DCB02OU DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. Name Access Addr (1,Hex) ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name Access Name USBIO_CR2 USB_CR1 Addr Access (1,Hex)
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5
CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
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11.0 Electrical Specifications
This section presents electrical specifications CY7C64215 enCoRe III. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com. Specifications valid 70°C 100°C, except where noted. Specifications devices running greater than valid 70°C 82°C.
5.25
4.75 Voltage
3.00
Frequency
Figure 11-1. Voltage versus Frequency
following table lists units measure that used this section.
Table 11-1. Units Measure Symbol Kbit µVrms Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol Unit Measure microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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11.1 Absolute Maximum Ratings
Min. Typ. Unit Notes Higher storage temperatures will reduce data retention time. +6.0 Max. +100
Table 11-2. Absolute Maximum Ratings Parameter Description TSTG Storage Temperature
VIO2 IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative -0.5 Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage 2000 Latch-up Current
Human Body Model ESD.
11.2
Operating Temperature
Min. Typ. Max. Unit Notes
Table 11-3. Operating Temperature Parameter Description Ambient Temperature Junction Temperature
temperature rise from ambient junction package specific. "Thermal Impedance" page user must limit power consumption comply with this requirement.
11.3
11.3.1
Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 70°C, 3.0V 3.6V 70°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-4. Chip-Level Specifications Parameter Description Supply Voltage Min. Typ. Max. Unit Notes 5.25 specifications, Table 11-12 page Conditions 5.0V, 25°C, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. Conditions 3.3V, 25°C, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 0.367 kHz, analog power off. Conditions with internal slow speed oscillator, 3.3V, 55°C, analog power off. Conditions with internal slow speed oscillator, 3.3V, 55°C 70°C, analog power off.
IDD5
Supply Current, (5V)
IDD3
Supply Current, (3.3V)
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.[1] Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.[1]
ISBH
Note: Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This should compared with devices that have similar functions enabled.
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11.3.2 General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 70°C, 3.0V 3.6V 70°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-5. GPIO Specifications Parameter Description Pull-Up Resistor Pull-Down Resistor High Output Level Min. Typ. Max. Unit Notes 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 0.75 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 5.25. 5.25. Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C.
Output Level
COUT
11.3.3
Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Full-Speed Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 70°C, 3.0V 3.6V 70°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-6. Full-Speed Mbps) Specifications Parameter Description Interface Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High-Z State Data Line Leakage REXT External Series Resistor VUOH Static Output High, Driven Min. Typ. Max. Unit Notes
(D+) (D-)
VUOHI VUOL VCRS
Static Output High, Idle Static Output Driver Output Impedance D+/D- Crossover Voltage
3.3V. series with each pin. Ground. Internal pull-up enabled. Ground. Internal pull-up enabled. Ground. Internal pull-up enabled. Including REXT Resistor.
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11.3.4 Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 70°C, 3.0V 3.6V 70°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-7. Analog Output Buffer Specifications Parameter VOSOB TCVOSOB VCMOB ROUTOB Description Min. Typ. Max. Unit Notes Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift µV/°C Common-Mode Input Voltage Range Output Resistance Power Power High VOHIGHOB High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Output Voltage Swing (Load ohms Vdd/2) Power Power High ISOB Supply Current Including Bias Cell Load) Power Power High PSRROB Supply Voltage Rejection Ratio (0.5 1.3) VOUT (Vdd 2.3). Table 11-8. 3.3V Analog Output Buffer Specifications Description Min. Typ. Max. Unit Notes Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift µV/°C Common-Mode Input Voltage Range Output Resistance Power Power High VOHIGHOB High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Output Voltage Swing (Load ohms Vdd/2) Power Power High ISOB Supply Current Including Bias Cell Load) Power Power High PSRROB Supply Voltage Rejection Ratio (0.5 1.0) VOUT (0.5 0.9). Parameter VOSOB TCVOSOB VCMOB ROUTOB
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11.3.5 Analog Reference Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 70°C, 3.0V 3
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