NTSC/PAL/SECAM 4x10 Digital Video Decoder With Macrovision Detection,
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TVP5146
NTSC/PAL/SECAM 4x10 Digital Video Decoder With Macrovision Detection, YPbPr/RGB Inputs, Line Comb Filter SCART Support
Digital Audio Video
SLES084A
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Contents
Section Title Page 2-10 2-11 2-11 2-16 2-16 2-17 2-17 2-17 2-19 2-19 2-20 2-21 2-21 2-22 2-22 Introduction Detailed Functionality Applications Related Products Ordering Information Functional Block Diagram Terminal Assignments Terminal Functions Functional Description Analog Processing Converters 2.1.1 Video Input Switch Control 2.1.2 Analog Input Clamping 2.1.3 Automatic Gain Control 2.1.4 Converters Digital Video Processing 2.2.1 Decimation Filter 2.2.2 Composite Processor 2.2.3 Luminance Processing 2.2.4 Component Video Processor 2.2.5 Color Space Conversion Clock Circuits Real-Time Control (RTC) Output Formatter 2.5.1 Fast Switches SCART 2.5.2 Separate Syncs 2.5.3 Embedded Syncs Host Interface 2.6.1 Reset Address Selection 2.6.2 Operation 2.6.3 VBUS Access 2.6.4 Timing Requirements Data Processor 2.7.1 FIFO Ancillary Data Video Stream 2.7.2 Data Output Reset Initialization Adjusting External Syncs 2.10 Internal Control Registers
2.11
Register Definitions 2.11.1 Input Select Register 2.11.2 Gain Control Register 2.11.3 Video Standard Register 2.11.4 Operation Mode Register 2.11.5 Autoswitch Mask Register 2.11.6 Color Killer Register 2.11.7 Luminance Processing Control Register 2.11.8 Luminance Processing Control Register 2.11.9 Luminance Processing Control Register 2.11.10 Luminance Brightness Register 2.11.11 Luminance Contrast Register 2.11.12 Chrominance Saturation Register 2.11.13 Chroma Register 2.11.14 Chrominance Processing Control Register 2.11.15 Chrominance Processing Control Register 2.11.16 Component Saturation Register 2.11.17 Component Contrast Register 2.11.18 Component Saturation Register 2.11.19 Component Brightness Register 2.11.20 AVID Start Pixel Register 2.11.21 AVID Stop Pixel Register 2.11.22 HSYNC Start Pixel Register 2.11.23 HSYNC Stop Pixel Register 2.11.24 VSYNC Start Line Register 2.11.25 VSYNC Stop Line Register 2.11.26 VBLK Start Line Register 2.11.27 VBLK Stop Line Register 2.11.28 Fast-Switch Control Register 2.11.29 Fast-Switch SCART Delay Register 2.11.30 SCART Delay Register 2.11.31 Delay Register 2.11.32 Control Register 2.11.33 Register 2.11.34 Sync Control Register 2.11.35 Output Formatter Register 2.11.36 Output Formatter Register 2.11.37 Output Formatter Register 2.11.38 Output Formatter Register 2.11.39 Output Formatter Register 2.11.40 Output Formatter Register 2.11.41 Clear Lost Lock Detect Register 2.11.42 Status Register 2.11.43 Status Register
2-27 2-27 2-28 2-28 2-29 2-29 2-30 2-30 2-31 2-31 2-31 2-32 2-32 2-32 2-33 2-33 2-33 2-34 2-34 2-34 2-35 2-35 2-35 2-36 2-36 2-36 2-36 2-37 2-37 2-37 2-38 2-38 2-38 2-39 2-39 2-40 2-40 2-41 2-42 2-43 2-44 2-44 2-45 2-46
2.11.44 2.11.45 2.11.46 2.11.47 2.11.48 2.11.49 2.11.50 2.11.51 2.11.52 2.11.53 2.11.54 2.11.55 2.11.56 2.11.57 2.11.58 2.11.59 2.11.60 2.11.61 2.11.62 2.11.63 2.11.64 2.11.65 2.11.66 2.11.67 2.11.68 2.11.69 2.11.70 2.11.71 2.11.72 2.11.73 2.11.74 2.11.75 2.11.76 2.11.77 2.11.78 2.11.79 2.11.80 2.11.81 2.11.82 2.11.83 2.11.84 2.11.85
Gain Status Register Video Standard Status Register GPIO Input Register GPIO Input Register Vertical Line Count Register Coarse Gain Register Coarse Gain Register Coarse Gain Register Coarse Gain Register Fine Gain Pb_B Register Fine Gain Y_G_Chroma Register Fine Gain R_Pr Register Fine Gain CVBS_Luma Register Version Register White Peak Processing Register Increment Speed Register Increment Delay Register Chip Register Chip Register Filter Mask Registers Filter Control Register FIFO Word Count Register FIFO Interrupt Threshold Register FIFO Reset Register FIFO Output Control Register Line Number Interrupt Register Pixel Alignment Register Line Start Register Line Stop Register Global Line Mode Register Full Field Enable Register Full Field Mode Register VBUS Data Access With VBUS Address Increment Register VBUS Data Access With VBUS Address Increment Register FIFO Read Data Register VBUS Address Access Register Interrupt Status Register Interrupt Status Register Interrupt Status Register Interrupt Status Register Interrupt Mask Register Interrupt Mask Register
2-46 2-47 2-47 2-48 2-48 2-49 2-49 2-50 2-50 2-51 2-51 2-52 2-52 2-52 2-53 2-54 2-54 2-54 2-54 2-55 2-56 2-57 2-58 2-58 2-58 2-58 2-59 2-59 2-59 2-59 2-60 2-60 2-60 2-60 2-61 2-61 2-62 2-63 2-64 2-65 2-66 2-67
2.11.86 Interrupt Clear Register 2.11.87 Interrupt Clear Register 2.12 VBUS Register Definitions 2.12.1 Closed Caption Data Register 2.12.2 Data Register 2.12.3 VITC Data Register 2.12.4 V-Chip Rating Block Register 2.12.5 V-Chip Rating Block Register 2.12.6 V-Chip Rating Block Register 2.12.7 V-Chip MPAA Rating Data Register 2.12.8 General Line Mode Line Address Register 2.12.9 VPS/Gemstar Data Register 2.12.10 FIFO Read Register 2.12.11 Interrupt Configuration Register Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions 3.2.1 Crystal Specifications Electrical Characteristics 3.3.1 Electrical Characteristics 3.3.2 Analog Processing Converters 3.3.3 Timing Example Register Settings Example 4.1.1 Assumptions 4.1.2 Recommended Settings Example 4.2.1 Assumptions 4.2.2 Recommended Settings Example 4.3.1 Assumptions 4.3.2 Recommended Settings Application Information Application Example Designing With PowerPAD Mechanical Data
2-68 2-69 2-70 2-70 2-70 2-71 2-71 2-71 2-72 2-72 2-73 2-74 2-74 2-75
List Illustrations
Figure 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 Title Functional Block Diagram Terminal Assignments Diagram Analog Processors Converters Digital Video Processor Block Diagram Composite S-Video Processor Block Diagram Color Low-Pass Filter Frequency Response Color Low-Pass Filter With Filter Frequency Response, NTSC Square Pixel Sampling Color Low-Pass Filter With Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling Color Low-Pass Filter With Filter Characteristics, Square Pixel Sampling Chroma Trap Filter Frequency Response, NTSC Square Pixel Sampling Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling Chroma Trap Filter Frequency Response, ITU-R BT.601 Sampling Chroma Trap Filter Frequency Response, Square Pixel Sampling Luminance Edge-Enhancer Peaking Block Diagram Peaking Filter Response, NTSC Square Pixel Sampling Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling Peaking Filter Response, Square Pixel Sampling Component Gain, Offset, Limit CbCr Component Gain, Offset, Limit Reference Clock Configurations Timing Vertical Synchronization Signals 525-Line System Vertical Synchronization Signals 625-Line System Horizontal Synchronization Signals 10-Bit 4:2:2 Mode Horizontal Synchronization Signals 20-Bit 4:2:2 Mode VSYNC Position With Respect HSYNC VBUS Access Page 2-10 2-12 2-13 2-14 2-15 2-16 2-18
2-26 2-27
Reset Timing 2-21 Teletext Filter Function 2-57 Clocks, Video Data, Sync Timing Host Port Timing Application Example
List Tables
Table 2-10 2-11 2-12 Title Terminal Functions Output Format Summary Line Frequencies, Data Rates, Pixel/Line Counts Sequence Host Interface Terminal Description Address Selection Supported Systems Ancillary Data Format Sequence Data Output Format Reset Sequence Register Summary VBUS Register Summary Analog Channel Video Mode Selection Page 2-10 2-11 2-16 2-17 2-17 2-19 2-20 2-21 2-21 2-23 2-26 2-27
viii
Introduction
TVP5146 device high quality, single-chip digital video decoder that digitizes decodes popular baseband analog video formats into digital component video. TVP5146 decoder supports analog-to-digital (A/D) conversion component YPbPr signals, well conversion decoding NTSC, PAL, SECAM composite S-video into component YCbCr. This decoder includes four 10-bit 30-MSPS converters (ADCs). Preceding each device, corresponding analog channel contains analog circuit that clamps input reference voltage applies programmable gain offset. total video input terminals configured combination RGB, YPbPr, CVBS, S-video video inputs. Component, composite, S-video signals sampled square-pixel ITU-R BT.601 clock frequency, line-locked, then decimated pixel rate. CVBS decoding utilizes five-line adaptive comb filtering both luma chroma data paths reduce both cross-luma cross-chroma artifacts. chroma trap filter also available. CVBS S-video inputs, user control video characteristics such contrast, brightness, saturation, host port interface. Furthermore, luma peaking (sharpness) with programmable gain included, well patented chroma transient improvement (CTI) circuit. built-in color space converter applied decoded component data. following output formats selected: 20-bit 4:2:2 YCbCr 10-bit 4:2:2 YCbCr. TVP5146 decoder generates synchronization, blanking, field, active video window, horizontal vertical syncs, clock, genlock (for downstream video encoder synchronization), host interrupt programmable logic signals, addition digital video outputs. TVP5146 decoder includes methods advanced vertical blanking interval (VBI) data retrieval. data processor (VDP) slices, parses, performs error checking teletext, closed caption (CC), other data. built-in FIFO stores lines teletext data, with proper host port synchronization, full-screen teletext retrieval possible. TVP5146 decoder pass through output formatter sampled luma data host-based processing. decoder provides option concurrent processing pixel-locked CVBS RGB/YPbPr input formats. main blocks TVP5146 decoder include: Robust sync detection weak noisy signals well trick modes separation 2-D, 5-line, adaptive comb chroma trap filter Fast-switch input pixel-by-pixel switching between CVBS YPbPr/RGB component video inputs (SCART support) Four 10-bit, 30-MSPS converters with analog preprocessors [clamp automatic gain control (AGC)] Luminance processor Chrominance processor Component processor Clock/timing processor power-down control Software-controlled power-saving standby mode Output formatter host port interface data processor
Macrovision copy protection detection circuit (Type separate color stripe detection) 3.3-V tolerant digital ports
Detailed Functionality
Four 30-MSPS, 10-bit channels with programmable gain control Supports NTSC 4.43), 60), SECAM CVBS, S-video Supports analog component YPbPr/RGB video formats with embedded sync analog video input terminals multisource connection User-programmable video output formats 10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs 10-bit 4:2:2 YCbCr with separate syncs 20-bit 4:2:2 YCbCr with separate syncs sampled data active video during vertical blanking period Sliced data during vertical blanking period active video period (full field mode)
HSYNC/VSYNC outputs with programmable position, polarity, width, (field output Component video processing Gain (contrast) offset (brightness) adjustments Automatic component video detection (525/625) Color space conversion from YCbCr
Composite S-video processing Adaptive 2-D, 5-line, adaptive comb filter composite video inputs; chroma trap available Automatic video standard detection (NTSC/PAL/SECAM) switching Luma-peaking with programmable gain Patented circuit Patented architecture locking weak, noisy, unstable signals Single 14.31818-MHz reference crystal standards (ITU-R.BT601 square pixel) Line-locked internal pixel sampling clock generation with horizontal- vertical-lock signal outputs Genlock output [real-time control (RTC] format) downstream video encoder synchronization
Certified Macrovision copy protection detection
Macrovision trademark Macrovision Corporation. Other trademarks property their respective owners.
data processor Teletext (NABTS, WST) extended data service (EDS) Wide screen signaling (WSS) Copy generation management system (CGMS) Video program system (VPS/PDC) Vertical interval time code (VITC) Gemstar electronic program guide compatible mode Register readback (CGMS), VPS/PDC, VITC, Gemstar sliced data
host port interface Reduced power consumption: 1.8-V digital core, 3.3-V digital I/O, 1.8-V analog core with power-save power-down modes 80-terminal TQFP PowerPAD package
Applications
Digital TV/monitors DVD-R video cards Video capture/video editing Video conferencing
Related Products
TVP5150A/TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector, (SLES098)
Ordering Information
PACKAGED DEVICES 70°C 80-TERMINAL PLASTIC FLAT-PACK PowerPADTVP5146PFP
Gemstar trademark Gemstar-TV Guide International. PowerPAD trademark Texas Instruments.
Functional Block Diagram
Copy Protection Detector Analog Front VI_1_A VI_1_B VI_1_C VI_2_A CVBS/ VI_2_B VI_2_C VI_3_A CVBS/ Pr/R/C VI_3_B VI_3_C ADC3 ADC2 Composite S-Video Processor ADC1 CVBS/Y Separation 5-line Adaptive Comb Luma Processing Chroma Processing Output Formatter Component Processor Color Space Conversion YCbCr Data Slicer
CVBS/Y/G
CVBS/ Pb/B/C
YCbCr Y[9:0] C[9:0]
Pb/B Pr/R
Gain/Offset
CVBS/Y VI_4_A
ADC4
GPIO Sampling Clock Timing Processor With Sync Detector
Host Interface
XTAL1
XTAL2
VS/VBLK
AVID
GLCO
DATACLK
Figure 1-1. Functional Block Diagram
RESETB
HS/CS
PWDN
Terminal Assignments
PACKAGE (TOP VIEW)
VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD
VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD
C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO DGND DVDD IOGND IOVDD DGND DVDD
CH4_A33VDD CH4_A33GND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND INTREQ DVDD DGND PWDN RESETB FSS/GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK
Figure 1-2. Terminal Assignments Diagram
Terminal Functions
Table 1-1. Terminal Functions
TERMINAL NAME Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A Clock Signals DATACLK XTAL1 XTAL2 Digital Video Digital video output CbCr, LSB. Unused outputs left unconnected. Also, these terminals programmable general-purpose I/O. 8-bit mode, LSBs ignored. needs pulldown resistor (see Figure 5-1). Line-locked data output clock External clock reference input. connected external oscillator with 1.8-V compatible clock signal 14.31818-MHz crystal oscillator. External clock reference output. connected XTAL1 driven external single-ended oscillator. VI_1_x: Analog video input CVBS/Pb/B/C VI_2_x: Analog video input CVBS/Y/G VI_3_x: Analog video input CVBS/Pr/R/C VI_4_A: Analog video input CVBS/Y composite, S-video, composite component video inputs combination thereof) supported. inputs must ac-coupled. recommended coupling capacitor possible input configurations listed input select register subaddress (see Section 2.11.1). NUMBER DESCRIPTION
C_[9:0]/ GPIO
Y_[9:0]
Digital video output Y/YCbCr, LSB. 8-bit mode, LSBs ignored. Unused outputs left unconnected.
Miscellaneous Signals FSS/GPIO Fast-switch (blanking) input. Switching signal between synchronous component video (YPbPr/RGB) composite video input. Programmable general-purpose GLCO/I2CA INTREQ PWDN RESETB Genlock control output (GLCO) During reset, this terminal input used program address LSB. Interrupt request Power-down input: Power down Normal mode Reset input, active
Table 1-1. Terminal Functions (Continued)
TERMINAL NAME Host Interface Power Supplies AGND A18GND_REF A18VDD_REF CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD DGND DVDD IOGND IOVDD PLL_A18GND PLL_A18VDD Sync Signals HS/CS/GPIO VS/VBLK/GPIO FID/GPIO AVID/GPIO Horizontal sync output digital composite sync output Programmable general-purpose Vertical sync output (for modes with dedicated VSYNC) VBLK output Programmable general-purpose Odd/even field indicator output. This terminal needs pulldown resistor (see Figure 5-1). Programmable general-purpose Active video indicator output Programmable general-purpose Analog ground. Connect analog ground. Analog 1.8-V return Analog power reference clock input data NUMBER DESCRIPTION
Analog 1.8-V return
Analog power. Connect
Analog 3.3-V return
Analog power. Connect
Digital return Digital power. Connect Digital power return Digital power. Connect less reduced noise. Analog power return Analog power. Connect
Functional Description
Analog Processing Converters
Figure shows functional diagram analog processors ADCs. This block provides analog interface video inputs. accepts inputs performs source selection, video clamping, video amplification, conversion, gain offset adjustments center digitized video signal.
TVP5146 Analog Front
VI_1_A VI_1_B VI_1_C
Clamp
10-Bit
VI_2_A VI_2_B VI_2_C
Clamp
10-Bit
Line-Locked Sampling Clock
VI_3_A VI_3_B VI_3_C
Clamp
10-Bit
VI_4_A
Clamp
10-Bit
Figure 2-1. Analog Processors Converters
2.1.1
Video Input Switch Control
TVP5146 decoder analog channels that accept video inputs. user configure internal analog video switches interface. analog video inputs used different input configurations, some which are: selectable individual composite video inputs four selectable S-video inputs three selectable analog YPbPr/RGB video inputs CVBS input selectable analog YPbPr/RGB video inputs, S-video inputs, CVBS inputs
input selection performed input select register subaddress (see Section 2.11.1).
2.1.2
Analog Input Clamping
internal clamping circuit restores ac-coupled video signal fixed level. clamping circuit provides line-by-line restoration video sync level fixed reference voltage. selection between bottom clamp performed automatically TVP5146 decoder.
2.1.3
Automatic Gain Control
TVP5146 decoder uses four programmable gain amplifiers (PGAs), channel. scale signal with voltage-input compliance 0.5-VPP 2-VPP full-scale 10-bit output code range. 4-bit code sets coarse gain with individual adjustment channel. Minimum gain corresponds code (2-VPP full-scale input, -6-dB gain) while maximum gain corresponds code (0.5 full scale, +6-dB gain). TVP5146 decoder also 12-bit fine gain controls each channel applies independently coarse gain controls. composite video, input video signal amplitude vary significantly from nominal level VPP. TVP5146 decoder adjust setting automatically: enabled adjust signal amplitude such that maximum range reached without clipping. Some nonstandard video signals contain peak white levels that saturate ADC. these cases, automatically cuts back gain avoid clipping. then TVP5146 decoder read gain currently being used. TVP5146 comprises front-end before separation back-end after separation. back-end restores optimum system gain whenever amplitude reference such composite peak (which only relevant before separation) forces front-end gain low. front-end back-end algorithms four amplitude references: sync height, color burst amplitude, composite peak, luma peak. specific amplitude references being used front-end back-end algorithms independently controlled using white peak processing register located subaddress 74h. TVP5146 gain increment speed gain increment delay controlled using increment speed register located subaddress increment delay register located subaddress 79h, respectively.
2.1.4
Converters
ADCs have resolution bits operate MSPS. channels receive identical clock from on-chip phase-locked loop (PLL) frequency between MHz. reference voltages generated internally.
Digital Video Processing
Figure block diagram TVP5146 digital video decoder processor. This processor receives digitized video signals from ADCs performs composite processing CVBS S-video inputs, YCbCr signal enhancements CVBS S-video inputs, YPbPr/RGB processing component video inputs. also generates horizontal vertical syncs other output control signals such genlock CVBS S-video inputs. Additionally, provide field identification, horizontal vertical lock, vertical blanking, active video window indication signals. digital data output programmed formats: 20-bit 4:2:2 with external syncs 10-bit 4:2:2 with embedded/separate syncs. circuit detects pseudosync pulses, pulses, color striping Macrovision-encoded copy-protected material. Information present interval retrieved either inserted ITU-R BT.656 output ancillary data stored internal FIFO and/or registers retrieval host port interface.
Copy Protection Detector
Data Processor
Slice Data Y[9:0] Output Formatter C[9:0]
Decimation Decimation Decimation Decimation XTAL1 XTAL2 RESETB PWDN DATACLK
CVBS/Y/G CVBS/Y Composite Processor YCbCr
Pb/B Pr/R Component Processor YCbCr
VS/VBLK Timing Processor HS/CS GLCO AVID Host Interface
Figure 2-2. Digital Video Processor Block Diagram
2.2.1
Decimation Filter
input signals oversampled factor MHz). outputs first pass through decimation filters that reduce data rate pixel rate. decimation filter half-band filter. Oversampling decimation filtering effectively increase overall signal-to-noise ratio
2.2.2
Composite Processor
Figure block diagram TVP5146 digital composite video processing circuit. This circuit receives digitized composite S-video signal from ADCs performs separation (bypassed S-video input), chroma demodulation PAL/NTSC SECAM, signal enhancements. 10-bit composite video multiplied subcarrier signals quadrature demodulator generate color difference signals signals then sent low-pass filters achieve desired bandwidth. adaptive 5-line comb filter separates from based unique property color phase shifts from line line. chroma remodulated through quadrature modulator subtracted from line-delayed composite video generate luma. This form separation completely complementary, thus there loss information. However, some applications, desirable limit bandwidth avoid crosstalk. that case, notch filters turned accommodate some viewing preferences, peaking filter also available luma path. Contrast, brightness, sharpness, hue, saturation controls programmable through host port.
CVBS/Y Line Delay
Peaking
Delay
SECAM Luma
NTSC/PAL Remodulation Contrast Brightness Saturation Adjust Notch Filter
CVBS
SECAM Color Demodulation
Color
Notch Filter
Burst Accumulator
Burst Accumulator
5-Line Adaptive Comb Filter Notch Filter Notch Filter Delay
CVBS/C NTSC/PAL Demodulation
Color
Delay
Figure 2-3. Composite S-Video Processor Block Diagram
2.2.2.1 Color Low-Pass Filter
High filter bandwidth preserves sharp color transitions produces crisp color boundaries. However, video sources that have asymmetrical side bands, desirable limit filter bandwidth avoid crosstalk. color low-pass filter bandwidth programmable enable three notch filters. Figure through Figure represent frequency responses wideband color low-pass filters.
Amplitude NTSC 1.29 ITU-R BT.601 1.42 1.55 Amplitude
Filter Filter Filter 1.29 Filter
Frequency
Frequency
Figure 2-4. Color Low-Pass Filter Frequency Response
Figure 2-5. Color Low-Pass Filter With Filter Frequency Response, NTSC Square Pixel Sampling
Filter Filter 1.55 Filter Filter 1.13
Amplitude Filter Filter 1.41 Filter Filter 1.03
Amplitude
Frequency
Frequency
Figure 2-6. Color Low-Pass Filter With Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling
Figure 2-7. Color Low-Pass Filter With Filter Characteristics, Square Pixel Sampling
2.2.2.2 Separation
separation done using adaptive 5-line (5-H delay) comb filters chroma trap filter. comb filter selectively bypassed luma chroma path. comb filter bypassed luma path, then chroma trap filters used which shown Figure through Figure 2-11. TI's patented adaptive comb filter algorithm reduces artifacts such hanging dots color boundaries. detects properly handles false colors high frequency luminance images, such multiburst pattern circle pattern. Adaptive comb filtering recommended mode operation.
Amplitude Amplitude Frequency Notch Filter Notch Filter Notch Filter Notch Filter Frequency Notch Filter Notch Filter Notch Filter Notch Filter
Figure 2-8. Chroma Trap Filter Frequency Response, NTSC Square Pixel Sampling
Amplitude Frequency Notch Filter Notch Filter Amplitude Notch Filter
Figure 2-9. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling
Frequency Notch Filter Notch Filter Notch Filter
Notch Filter
Notch Filter
Figure 2-10. Chroma Trap Filter Frequency Response, ITU-R BT.601 Sampling
Figure 2-11. Chroma Trap Filter Frequency Response, Square Pixel Sampling
2.2.3
Luminance Processing
digitized composite video signal passes through either luminance comb filter chroma trap filter, either which removes chrominance information from composite signal generate luminance signal. luminance signal then into input peaking circuit. Figure 2-12 illustrates basic functions luminance data path. case S-video, luminance signal bypasses comb filter chroma trap filter directly circuit. High-frequency components luminance signal enhanced peaking filter (sharpness). Figure 2-13, Figure 2-14, Figure 2-15 show characteristics peaking filter four different gain settings that programmable host port.
Gain
Peak Detector
Bandpass Filter
Peaking Filter
Delay
Figure 2-12. Luminance Edge-Enhancer Peaking Block Diagram
Amplitude Gain Frequency Frequency Gain Amplitude Gain Peak 2.40 Gain Gain Gain Gain Peak 2.64 Gain
Figure 2-13. Peaking Filter Response, NTSC Square Pixel Sampling
Figure 2-14. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling
Gain Amplitude Gain Gain Frequency Peak 2.89 Gain
Figure 2-15. Peaking Filter Response, Square Pixel Sampling
2.2.3.1 Color Transient Improvement
Color transient improvement (CTI) enhances horizontal color transients delay modulation both color difference signals. operation must performed only YCbCr-formatted data. color difference signal transition points maintained, edges enhanced signals which have bandwidth-limited color components (for example, CVBS S-video).
2.2.4
Component Video Processor
component video processing block supports user-selectable contrast, brightness, saturation adjustment YCbCr output formats. YCbCr output formats, gain offset values applied luma data path order pixel values correct output range (for 10-bit Ymin Ymax 940), provide means adjusting contrast brightness. digital contrast (gain) brightness (offset) factors vary from 255. contrast control adjusts amplitude range output centered midpoint output code range. limit block limits output ITU-R BT.601 range (Ymin Ymax) extended range, depending user setting.
Offset
Limit
Gain
Figure 2-16. Component Gain, Offset, Limit
CbCr components, saturation (gain) factor applied CbCr inputs order them CbCr output code range provide saturation control. Similarly, limit block limit CbCr outputs valid range: Cb,Crmin Cb,Crmax
CbCr Limit CbCr
Gain
Figure 2-17. CbCr Component Gain, Offset, Limit
2.2.5
Color Space Conversion
0.299 0.587 0.114 -0.172 0.339 0.511 0.511 0.428 0.083
formulas YCbCr conversion given
Clock Circuits
internal line-locked generates system pixel clocks. 14.31818-MHz clock required drive PLL. This input TVP5146 decoder 1.8-V level terminal (XTAL1), crystal 14.31818-MHz fundamental resonant frequency connected across terminals (XTAL2). parallel resonant circuit used shown Figure 2-18, then external capacitors must have following relationship: CSTRAY, where CSTRAY terminal capacitance with respect ground. Figure 2-18 shows reference clock configurations. TVP5146 decoder generates DATACLK signal used clocking data.
TVP5146 14.31818-MHz Clock
TVP5146
14.31818-MHz Crystal
XTAL1
XTAL1
XTAL2
XTAL2
Figure 2-18. Reference Clock Configurations
Real-Time Control (RTC)
Although TVP5146 decoder line-locked system, color burst information used determine accurately color subcarrier frequency phase. This ensures proper operation with nonstandard video signals that follow exactly required frequency multiple between color subcarrier frequency video line frequency. frequency control word internal color subcarrier subcarrier reset transmitted terminal (GLCO) optional system (for example, video encoder). frequency control word 23-bit binary number. instantaneous frequency color subcarrier calculated from following equation: ctrl sclk
where FPLL frequency subcarrier PLL, Fctrl 23-bit frequency control word, Fsclk times pixel frequency. Figure 2-19 shows detailed timing diagram.
Valid Sample Reserved
Invalid Sample
23-Bit Increment
Start NOTE: Reset active low, Sequence PAL:1 (R-Y) line normal, (R-Y) line inverted, NTSC: change
Figure 2-19. Timing
Output Formatter
output formatter sets data formatted output TVP5146 output buses. Table shows available output modes. Table 2-1. Output Format
TERMINAL NAME TERMINAL NUMBER 10-Bit 4:2:2 YCbCr Cb9, Cb8, Cb7, Cb6, Cb5, Cb4, Cb3, Cb2, Cb1, Cb0, 20-Bit 4:2:2 YCbCr Cb9, Cb8, Cb7, Cb6, Cb5, Cb4, Cb3, Cb2, Cb1, Cb0,
2-10
Table 2-2. Summary Line Frequencies, Data Rates, Pixel/Line Counts
STANDARDS sampling NTSC-J, NTSC-4.43 PAL-M PAL-60 PAL-B, PAL-N PAL-Nc SECAM Square sampling NTSC-J, NTSC-4.43 PAL-M PAL-60 PAL-B, PAL-N PAL-Nc SECAM 12.2727 12.2727 12.2727 12.2727 14.75 14.75 14.75 14.75 3.579545 4.43361875 3.57561149 4.43361875 4.43361875 4.43361875 3.58205625 4.406250 4.250000 15.73426 15.73426 15.73426 15.73426 15.625 15.625 15.625 15.625 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 3.579545 4.43361875 3.57561149 4.43361875 4.43361875 4.43361875 3.58205625 4.406250 4.250000 15.73426 15.73426 15.73426 15.73426 15.625 15.625 15.625 15.625 PIXELS LINE ACTIVE PIXELS LINE LINES FRAME PIXEL FREQUENCY (MHz) COLOR SUBCARRIER FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz)
2.5.1
Fast Switches SCART
TVP5146 decoder supports SCART interface used European audio/video equipment carry composite video, S-video, video same cable. event that composite video video present simultaneously video terminals assigned SCART interface, TVP5146 decoder assumes they pixel synchronous each other. timing both composite video video obtained from composite source, derived clock used sample video well. fast-switch input terminal allows switching between these input video sources pixel-by-pixel basis. fast switch hard switch; there alpha blending between both sources.
2.5.2
Separate Syncs
VBLK independently software programmable pixel count. This allows possible alignment internal pixel count line count. default settings 525-line 625-line video outputs given examples below. changes same transient time when trailing edge vertical sync occurs. polarity programmable interface.
2-11
525-Line First Field Video
Start Stop
VBLK
VBLK Start
VBLK Stop
Second Field Video
Start Stop
VBLK
VBLK Start NOTE: Line numbering conforms ITU-R BT.470
VBLK Stop
Figure 2-20. Vertical Synchronization Signals 525-Line System
2-12
625-Line First Field Video
Start Stop
VBLK
VBLK Start
VBLK Stop
Second Field Video
Start Stop
VBLK
VBLK Start NOTE: Line numbering conforms ITU-R BT.470
VBLK Stop
Figure 2-21. Vertical Synchronization Signals 625-Line System
2-13
DATACLK
Y[9:0]
Horizontal Blanking
Start
Stop
AVID AVID Stop DATACLK Mode NTSC NTSC Pixel Clock AVID Start
NOTE: ITU-R BT.656 10-bit 4:2:2 timing with pixel clock reference
Figure 2-22. Horizontal Synchronization Signals 10-Bit 4:2:2 Mode
2-14
DATACLK
Y[9:0]
Horizontal Blanking
CbCr[9:0]
Horizontal Blanking
Start AVID
Stop
AVID Stop NOTE: AVID rising edge occurs clock cycles early. DATACLK Mode NTSC NTSC NOTE: 20-bit 4:2:2 timing with pixel clock reference Pixel Clock
AVID Start
Figure 2-23. Horizontal Synchronization Signals 20-Bit 4:2:2 Mode
2-15
First Field
Second Field
10-Bit (PCLK Mode NTSC NTSC
Pixel Clock)
20-Bit (PCLK
Pixel Clock)
Figure 2-24. VSYNC Position With Respect HSYNC
2.5.3
Embedded Syncs
Standards with embedded syncs insert codes into data stream rising falling edges AVID. These codes contain bits which also define vertical timing. Table gives format codes. equals always indicates EAV. equals always indicates SAV. alignment line field counter varies depending standard. bits protection bits: Table 2-3. Sequence
(MSB) Preamble Preamble Preamble Status word
Host Interface
Communication with TVP5146 decoder host interface. standard consists signals, serial input/output data (SDA) line serial input clock line (SCL), which carry information between devices connected bus. third signal (I2CA) used slave address selection. Although system multimastered, TVP5146 decoder functions slave device only.
2-16
Because kept open-drain logic-high output level when driven, user must connect positive supply voltage pullup resistor board. slave-address select signal, terminal (I2CA), enables TVP5146 decoders tied same controlling least significant device address. Table 2-4. Host Interface Terminal Description
SIGNAL I2CA TYPE DESCRIPTION Slave address selection Input clock line Input/output data line
2.6.1
Reset Address Selection
TVP5146 decoder respond possible chip addresses. address selection made reset externally supplied level I2CA terminal. TVP5146 decoder samples level terminal power trailing edge RESETB configures address I2CA terminal internal pulldown resistor pull terminal zero. Table 2-5. Address Selection
(I2CA) (default) B9/B8 BB/BA
terminal strapped DVDD 2.2-k resistor, device address
2.6.2
Operation
1011 1000 Subaddress Send data
Data transfers occur using following illustrated formats. Read from control registers
1011 1000 Subaddress 1011 1001 Receive data
start condition stop condition Acknowledge generated slave Acknowledge generated master, multiple-byte read master with each byte except last byte Subaddrress Subaddress byte Data Data byte, more than byte data transmitted (read write), subaddress pointer automatically incremented. address Example showing that I2CA default mode. Write (B8h), read (B9h)
2.6.3
VBUS Access
TVP5146 decoder additional internal registers accessible through indirect access internal 24-bit address wide VBUS. Figure 2-25 shows VBUS registers access.
2-17
Registers
VBUS Registers 0000h
HOST Processor
VITC VBUS Data VBUS[23:0] VBUS Address FIFO Line Mode
051Ch 0520h 052Ch 0600h
0700h 1904h FFFFh
VBUS Write Single Byte
Send Data
Multiple Bytes
Send Data
Send Data
VBUS Read Single Byte
Read Data
Multiple Bytes
Read Data
Read Data
NOTE: Examples default address. Acknowledge generated slave Acknowledge generated master
Figure 2-25. VBUS Access
2-18
2.6.4
Timing Requirements
TVP5146 decoder requires delays accesses accommodate internal processor timing. accordance with specifications, TVP5146 decoder holds clock line (SCL) indicate wait period master. master designed check clock line held-low condition, then maximum delays must always inserted where required. These delays variable length; maximum delays indicated following diagram: Normal register
1011 1000 Subaddress Send data Wait
Data Processor
TVP5146 data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code (VITC), video program system (VPS), copy generation management system (CGMS) data, electronic program guide (Gemstar) 1x/2x. Table shows supported system. These services acquired programming enable reception more data standard(s) VBI. programmed line-per-line basis enable simultaneous reception different formats, line. results stored FIFO and/or registers. Because high data bandwidth, teletext results stored FIFO only. TVP5146 decoder provides fully decoded V-CHIP data dedicated registers subaddresses 800540h-800543h (see Sections 2.12.4 through 2.12.7). Table 2-6. Supported Systems
SYSTEM Teletext Teletext Teletext NABTS Teletext NABTS Closed caption Closed caption WSS-CGMS VITC VITC (PDC) V-CHIP (decoded) Gemstar Gemstar User STANDARD SECAM NTSC NTSC-J NTSC NTSC NTSC NTSC NTSC NTSC Programmable LINE NUMBER 6-23 (Fields 6-22 (Fields 10-21 (Fields 10-21 (Fields (Fields (Fields (Fields (Fields 6-22 10-20 (Field NUMBER BYTES bits bits with frame byte Programmable
2-19
2.7.1
FIFO Ancillary Data Video Stream
Sliced data output ancillary data video stream ITU-R BT.656 mode. data output Y[9:2] terminals during horizontal blanking period. Table shows header format sequence ancillary data inserted into video stream. This format also used store data into FIFO. size FIFO bytes. Therefore, FIFO store lines teletext data with NTSC NABTS standard. Table 2-7. Ancillary Data Format Sequence
BYTE (MSB) Data error Match DID2 Match DID1 (LSB) DID0 Data (DID) Secondary data (SDID) Number 32-bit data (NN) Internal data (IDID0) Video line [9:8] Internal data (IDID1) Data byte Data byte Data byte Data byte Data byte Check Fill byte word word Ancillary data preamble DESCRIPTION
Video line [7:0]
Data Data Data Data Data CS[7:0]
4N+7
DID:
Even parity D0-D5
NEP: Negated even parity
91h: Sliced data lines first field 53h: Sliced data line first field 55h: Sliced data lines second field 97h: Sliced data line second field This field holds data format taken from line mode register bits [2:0] corresponding line. Number Dwords beginning with byte through 4N+7. Note this value number Dwords where each Dword bytes. Transaction video line number [7:0] Transaction video line number [9:8] Match flag Match flag error detected block. error detected. D0-D7 first data through last data byte. Fill bytes make multiple bytes from byte last fill byte. teletext modes, byte sync pattern byte. Byte first data byte.
SDID: IDID0: IDID1:
Fill byte:
2-20
2.7.2
Data Output
TVP5146 decoder output video data twice sampling rate external slicing. This transmitted ancillary data block, although somewhat differently from sliced data transmitted FIFO format described Section 2.7.1. samples transmitted during active portion line. data uses ITU-R BT.656 format having only luma data. chroma samples replaced luma samples. TVP5146 decoder inserts four-byte preamble 000h 3FFh 3FFh 180h before data start. There checksum bytes fill bytes this mode. Table 2-8. Data Output Format
BYTE (MSB) Data Data n-5. Data n-4. Data pixel rate luma data (i.e., NTSC 601: 1707) (LSB) data preamble DESCRIPTION
Reset Initialization
Reset initiated power time terminal (RESETB) brought low. Table describes status TVP5146 terminals during immediately after reset. Table 2-9. Reset Sequence
SIGNAL NAME Y[9:0], C[9:0], DATACLK RESETB, PWDN, SDA, SCL, FSS, AVID, GLCO, INTREQ DATACLK DURING RESET Input Input Input Output RESET COMPLETED High-impedance Input Output High-impedance
POWER (3.3
(min)
(min) Normal Operation
RESETB (Terminal
Reset (min)
(Terminal
Invalid Cycle
Valid
Figure 2-26. Reset Timing
2-21
TVP5146 requires that terminal (C_1/GPIO) held LOW. using 20-/16-bit mode using this terminal GPIO, then this terminal must pulled through 2.2-k pulldown resistor (see Figure 5-1). unused, this terminal shorted ground. (Note: using 20-/16-bit mode only using MSBs, possible short terminal GND, current IOVDD will increase mA.) After reset, user must write following commands TVP5146:
STEP SUBADDRESS 0xE8 0xE9 0xEA 0xE0 0xE8 0xE9 0xEA 0xE0 0xE0 DATA 0x02 0x00 0x80 0x01 0x60 0x00 0xB0 0x01 0x00
Afterward, user programs device usual.
Adjusting External Syncs
proper sequence program following external syncs NTSC, PAL-M, NTSC 443, PAL60 (525-line modes): video standard NTSC (register 02h) HSYNC, VSYNC, VBLK, AVID external syncs (registers through 24h)
PAL, PAL-N, SECAM (625-line modes): video standard (register 02h) HSYNC, VSYNC, VBLK, AVID external syncs (registers through 24h)
autoswitch, video standard autoswitch (register 02h)
2.10 Internal Control Registers
TVP5146 decoder initialized controlled internal registers that define operating parameters entire decoder. Communication between external controller TVP5146 decoder through standard host port interface, described earlier. Table 2-10 shows summary these registers. Detailed programming information each register described following sections. Additional registers accessible through indirect procedure involving access internal 24-bit address wide VBUS. Table 2-11 shows summary VBUS registers. NOTE: write reserved registers. Reserved bits defined register must written with unless otherwise noted.
2-22
Table 2-10. Register Summary
REGISTER NAME Input select gain control Video standard Operation mode Autoswitch mask Color killer Luminance processing control Luminance processing control Luminance processing control Luminance brightness Luminance contrast Chrominance saturation Chroma Chrominance processing control Chrominance processing control Reserved Component saturation Component contrast Component saturation Reserved Component brightness Reserved AVID start pixel AVID stop pixel HSYNC start pixel HSYNC stop pixel VSYNC start line VSYNC stop line VBLK start line VBLK stop line NOTE: Read only Write only Read write Reserved register addresses must written SUBADDRESS 16h-17h 18h-19h 1Ah-1Bh 1Ch-1Dh 1Eh-1Fh 20h-21h 22h-23h 24h-25h 055h 325h 000h 040h 004h 007h 001h 015h DEFAULT
2-23
Table 2-10. Registers Summary (Continued)
REGISTER NAME Reserved Fast-switch control Reserved Fast-switch SCART delay Reserved SCART delay delay control Reserved Sync control Output formatter Output formatter Output formatter Output formatter Output formatter Output formatter Clear lost lock detect Status Status gain status Reserved Video standard status GPIO input GPIO input Vertical line count Reserved coarse gain coarse gain coarse gain coarse gain fine gain Pb_B fine gain Y_G_Chroma fine gain Pr_R fine gain CVBS_Luma Reserved version Reserved white peak processing Reserved NOTE: Read only Write only Read write Reserved register addresses must written
SUBADDRESS 26h-27h 2Fh-30h 3Ch-3Dh 42h-43h 44h-45h 4Ah-4Bh 4Ch-4Dh 4Eh-4Fh 50h-51h 52h-6Fh 71h-73h 75h-77h
DEFAULT
900h 900h 900h 900h
2-24
Table 2-10. Registers Summary (Continued)
REGISTER NAME increment speed increment delay Reserved Chip Chip Reserved filter mask filter mask filter mask filter mask filter mask filter mask filter mask filter mask filter mask filter mask filter control FIFO word count FIFO interrupt threshold Reserved FIFO reset FIFO output control line number interrupt pixel alignment Reserved line start line stop global line mode full field enable full field mode Reserved VBUS data access with VBUS address increment VBUS data access with VBUS address increment FIFO read data Reserved VBUS address access Reserved Interrupt status Interrupt status NOTE: Read only Write only Read write Reserved register addresses must written
SUBADDRESS 7Ah-7Fh 82h-B0h C2h-C3h C4h-D5h DBh-DFh E3h-E7h E8h-E9h EBh-EFh
DEFAULT
01Eh
0000h
2-25
Table 2-10. Registers Summary (Continued)
REGISTER NAME Interrupt status Interrupt status Interrupt mask Interrupt mask Interrupt clear Interrupt clear Reserved NOTE: Read only Write only Read write Reserved register addresses must written SUBADDRESS F8h-FFh DEFAULT
Table 2-11. VBUS Register Summary
REGISTER NAME Reserved closed caption data data Reserved VITC data Reserved V-Chip data Reserved general line mode line address Reserved VPS/Gemstar data Reserved FIFO read Reserved Interrupt configuration Reserved SUBADDRESS 0000h-80 051Bh 051Ch-80 051Fh 0520h-80 0526h 0527h-80 052Bh 052Ch-80 0534h 0535h-80 053Fh 0540h-80 0543h 0544h-80 05FFh 0600h-80 0611h 0612h-80 06FFh 0700h-80 070Ch 070Dh-90 1903h 1904h 1905h-B0 005Fh 0060h 0061h-FF FFFFh 00h, DEFAULT
NOTE: Writing value reserved register cause erroneous operation TVP5146 decoder. recommended access data to/from reserved registers.
2-26
2.11 Register Definitions
2.11.1 Input Select Register
Subaddress Default
Input select [7:0]
Table 2-12. Analog Channel Video Mode Selection
MODE CVBS INPUT(S) SELECTED VI_1_A (default) VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A S-video VI_2_A(Y), VI_1_A(C) VI_2_B(Y), VI_1_B(C) VI_2_C(Y), VI_1_C(C) VI_2_A(Y), VI_3_A(C) VI_2_B(Y), VI_3_B(C) VI_2_C(Y), VI_3_C(C) VI_4_A(Y), VI_1_A(C) VI_4_A(Y), VI_1_B(C) VI_4_A(Y), VI_1_C(C) VI_4_A(Y), VI_3_A(C) VI_4_A(Y), VI_3_B(C) VI_4_A(Y), VI_3_C(C) VI_1_A(B), VI_2_A(G), VI_3_A(R) VI_1_B(B), VI_2_B(G), VI_3_B(R) VI_1_C(B), VI_2_C(G), VI_3_C(R) YPbPr VI_1_A(Pb), VI_2_A(Y), VI_3_A(Pr) VI_1_B(Pb), VI_2_B(Y), VI_3_B(Pr) VI_1_C(Pb), VI_2_C(Y), VI_3_C(Pr) SCART VI_1_A(B), VI_2_A(G), VI_3_A(R), VI_4_A(CVBS) VI_1_B(B), VI_2_B(G), VI_3_B(R), VI_4_A(CVBS) VI_1_C(B), VI_2_C(G), VI_3_C(R), VI_4_A(CVBS) VI_1_A(Pb), VI_2_A(Y), VI_3_A(Pr), VI_4_A(CVBS) VI_1_B(Pb), VI_2_B(Y), VI_3_B(Pr), VI_4_A(CVBS) VI_1_C(Pb), VI_2_C(Y), VI_3_C(Pr), VI_4_A(CVBS) INPUT SELECT [7:0]
input terminals configured support composite, S-video, component YPbPr/RGB SCART listed Table 2-12. Users must follow this table properly S-video component applications because only terminal configurations listed Table 2-12 supported.
2-27
2.11.2 Gain Control Register
Subaddress Default Reserved chroma luma
must written this bit. must written this bit. chroma: Controls automatic gain chroma/B/R/PbPr channel: Manual luma manual, chroma forced manual) Enabled auto gain, applies gain value acquired from sync channel S-video component mode. When luma set, this state valid. (default) luma: Controls automatic gain embedded sync channel CVBS, S-video, component video: Manual gain, coarse fine gain frozen previous gain value when this Enabled auto gain applies only embedded sync channel (default) These settings only affect analog front-end (AFE). brightness contrast component, CVBS affected these settings.
2.11.3 Video Standard Register
Subaddress Default Reserved Video standard [2:0]
Video standard [2:0]: CVBS S-Video Autoswitch mode (default) NTSC (Combination-N) NTSC 4.43 SECAM Component Video Autoswitch mode (default) Component Component Reserved Reserved Reserved Reserved Reserved
NOTE: PAL60 included autoswitch mode. With autoswitch code running, user force decoder operate particular video standard mode writing appropriate value into this register. Changing these bits causes register settings reinitialized. NOTE: Sampling rate (either square pixel ITU-R BT.601) (sampling rate) output formatter register subaddress (see Section 2.11.35).
2-28
2.11.4 Operation Mode Register
Subaddress Default Reserved Power save
Power save: Normal operation (default) Power-save mode. Reduces clock speed internal processor switches ADCs. interface active current operating settings preserved.
2.11.5 Autoswitch Mask Register
Subaddress Default Reserved SECAM NTSC 4.43 (Nc) NTSC
Autoswitch mode mask: Limits video formats between which autoswitch possible. SECAM: Autoswitch does include SECAM Autoswitch includes SECAM (default) NTSC 4.43: Autoswitch does include NTSC 4.43 (default) Autoswitch includes NTSC 4.43 (Nc) PAL: Autoswitch does include (Nc) (default) Autoswitch includes (Nc) PAL: Autoswitch does include (default) Autoswitch includes PAL: Reserved Autoswitch includes (default) NTSC: Reserved Autoswitch includes NTSC (default) NOTE: Bits must always
2-29
2.11.6 Color Killer Register
Subaddress Default Reserved Color killer threshold [4:0]
Automatic color killer
Automatic color killer: Automatic mode (default) Reserved Color killer enabled, terminals forced zero color state. Color killer disabled Color killer threshold [4:0]: 1111 (maximum) 0000 (default) 0000 (minimum)
2.11.7 Luminance Processing Control Register
Subaddress Default Reserved Pedestal present Reserved
Luminance signal delay [3:0]
Pedestal present: pedestal present analog video input signal (default) Pedestal present analog video input signal raw: Disabled (default) Enabled During duration vertical blanking defined VBLK start stop line registers subaddresses through (see Sections 2.11.26 2.11.27), chroma samples replaced luma samples. This feature used support processing performed external device during VBI. order this bit, output format must 10-bit ITU-R BT.656 mode. Luminance signal delay [3:0]: Luminance signal delays with respect chroma signal pixel clock increments. 0111 Reserved 0110 6-pixel delay 0001 1-pixel delay 0000 delay (default) 1111 -1-pixel delay 1000 -8-pixel delay
2-30
2.11.8 Luminance Processing Control Register
Subaddress Default Reserved Reserved
Luma filter select [1:0]
Peaking gain (sharpness) [1:0]
Luma filter selected [1:0]: Luminance adaptive comb enabled (default CVBS) Luminance adaptive comb disabled (trap filter selected) Luma comb/trap filter bypassed (default S-video, component mode, SECAM) Reserved Peaking gain (sharpness) [1:0]: (default)
2.11.9 Luminance Processing Control Register
Subaddress Default Reserved
Trap filter select [1:0]
Trap filter select [1:0] selects four trap filters produce luminance signal removing chrominance signal from composite video signal. stopband chroma trap filter centered chroma subcarrier frequency with stopband bandwidth controlled control bits. Trap filter stopband bandwidth (MHz): Filter select [1:0] (default) NTSC ITU-R BT.601 1.2129 0.8701 0.7183 0.5010 NTSC Square pixel 1.1026 0.7910 0.6712 0.4554 ITU-R BT.601 1.2129 0.8701 0.7383 0.5010 Square pixel 1.3252 0.9507 0.8066 0.5474
2.11.10 Luminance Brightness Register
Subaddress Default Brightness [7:0]
Brightness [7:0]: This register works CVBS S-video luminance. 1111 1111 (bright) 1000 0000 (default) 0000 0000 (dark)
2-31
2.11.11 Luminance Contrast Register
Subaddress Default Contrast [7:0]
Contrast [7:0]: This register works CVBS S-video luminance. 1111 1111 (maximum contrast) 1000 0000 (default) 0000 0000 (minimum contrast)
2.11.12 Chrominance Saturation Register
Subaddress Default Saturation [7:0]
Saturation [7:0]: This register works CVBS S-video chrominance. 1111 1111 (maximum) 1000 0000 (default) 0000 0000 color)
2.11.13 Chroma Register
Subaddress Default [7:0]
[7:0] (does apply component video): This register works CVBS S-video chrominance. 0111 1111 +180 degrees 0000 0000 degrees (default) 1000 0000 -180 degrees
2-32
2.11.14 Chrominance Processing Control Register
Subaddress Default Reserved Color reset Chrominance adaptive comb enable Reserved
Automatic color gain control [1:0]
Color reset: Color subcarrier reset (default) Color subcarrier reset Chrominance adaptive comb enable: This effective composite video only. Enabled (default) Disabled Automatic color gain control (ACGC) [1:0]: ACGC enabled (default) Reserved ACGC disabled, ACGC nominal value ACGC frozen previous value
2.11.15 Chrominance Processing Control Register
Subaddress Default Reserved compensation
Chrominance filter select [1:0]
compensation: Disabled Enabled (default) WCF: Wideband chroma filter Disabled Enabled (default) Chrominance filter select [1:0]: Disabled Notch Notch (default) Notch Figure through Figure 2-11 characteristics.
2.11.16 Component Saturation Register
Subaddress Default
saturation [7:0]
saturation [7:0]: This register works only with YPbPr component video. video, user must gain registers. 1111 1111 (maximum) 1000 0000 (default) 0000 0000 (minimum)
2-33
2.11.17 Component Contrast Register
Subaddress Default contrast [7:0]
contrast [7:0]: This register works only with YPbPr component video. video, user must gain registers. 1111 1111 (maximum) 1000 0000 (default) 0000 0000 (minimum)
2.11.18 Component Saturation Register
Subaddress Default
saturation [7:0]
saturation [7:0]: This register works only with YPbPr component video. video, user must gain registers. 1111 1111 (maximum) 1000 0000 =128 (default) 0000 0000 (minimum)
2.11.19 Component Brightness Register
Subaddress Default
brightness [7:0]
brightness [7:0]: This register works only with YPbPr component video. 1111 1111 (maximum) 1000 0000 (default) 0000 0000 (minimum)
2-34
2.11.20 AVID Start Pixel Register
Subaddress Default Subaddress Reserved 16h-17h 055h AVID active Reserved
AVID start [7:0] AVID start [9:8]
AVID active: AVID active VBLK (default) AVID inactive VBLK AVID start [9:0]: AVID start pixel number, this absolute pixel location from HSYNC start pixel default NTSC (55h) NTSC (56h) (58h) (67h)
TVP5146 decoder updates AVID start only when AVID start byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets. AVID start pixel register also controls position code.
2.11.21 AVID Stop Pixel Register
Subaddress Default Subaddress Reserved 18h-19h 325h
AVID stop [7:0] AVID stop [9:8]
AVID stop [9:0]: AVID stop pixel number. number pixels active video must even number. This absolute pixel location from HSYNC start pixel default NTSC (325h) NTSC (2D6h) (328h) (2B8h)
TVP5146 decoder updates AVID stop only when AVID stop byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets. AVID start pixel register also controls position code.
2.11.22 HSYNC Start Pixel Register
Subaddress Default 1Ah-1Bh 000h
Default (000h)
Subaddress Reserved
HSYNC start [7:0] HSYNC start [9:8]
HSYNC start pixel [9:0]: This absolute pixel location from HSYNC start pixel TVP5146 decoder updates HSYNC start only when HSYNC start byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets.
2-35
2.11.23 HSYNC Stop Pixel Register
Subaddress Default Subaddress Reserved 1Ch-1Dh 040h
HSYNC stop [7:0] HSYNC stop [9:8]
HSYNC stop [9:0]: This absolute pixel location from HSYNC start pixel TVP5146 decoder updates HSYNC stop only when HSYNC Stop byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets.
2.11.24 VSYNC Start Line Register
Subaddress Default Subaddress Reserved 1Eh-1Fh 004h
VSYNC start [7:0] VSYNC start [9:8]
VSYNC start [9:0]: This absolute line number. TVP5146 decoder updates VSYNC start only when VSYNC start byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets. NTSC: default 004h, PAL: default 001h
2.11.25 VSYNC Stop Line Register
Subaddress Default Subaddress Reserved 20h-21h 007h
VSYNC stop [7:0] VSYNC stop [9:8]
VSYNC stop [9:0]: This absolute line number. TVP5146 decoder updates VSYNC stop only when VSYNC stop byte written user changes these registers, TVP5146 decoder retains values different modes until this decoder resets. NTSC: default 007h, PAL: default 004h
2.11.26 VBLK Start Line Register
Subaddress Default Subaddress Reserved 22h-23h 001h
VBLK start [7:0] VBLK start [9:8]
VBLK start [9:0]: This absolute line number. TVP5146 decoder updates VBLK start line only when VBLK start byte written user changes these registers, TVP5146 decoder retains values different modes until this decoder resets. NTSC: default 001h, PAL: default (26Fh)
2-36
2.11.27 VBLK Stop Line Register
Subaddress Default Subaddress Reserved 24h-25h 015h
VBLK stop [7:0] VBLK stop [9:8]
VBLK stop [9:0]: This absolute line number. TVP5146 decoder updates VBLK stop only when VBLK stop byte written user changes these registers, then TVP5146 decoder retains values different modes until this decoder resets. NTSC: default (15h), PAL: default (17h)
2.11.28 Fast-Switch Control Register
Subaddress Default Mode [2:0] Reserved Reserved edge Reserved Polarity
Mode [2:0]: Select fast-switch modes CVBS SCART Reserved Reserved Reserved Reserved Reserved Composite only (default) Component only edge: sampled rising falling edge sampling clock Rising edge Falling edge (default) Polarity FSS: YCbCr/RGB CVBS (4A) CVBS (4A) (default) YCbCr/RGB
2.11.29 Fast-Switch SCART Delay Register
Subaddress Default Reserved delay [4:0]
delay [4:0]: Adjusts delay between component RGB/YPbPr 1111 pixel delay 0001 pixel delay 0000 delay (default) 1111 pixel delay 0000 pixel delay
2-37
2.11.30 SCART Delay Register
Subaddress Default Reserved SCART delay [4:0]
SCART delay [4:0]: Adjusts delay between CVBS component (RGB) video 1111 pixel delay 0001 pixel delay 0000 delay (default) 1111 pixel delay 0000 pixel delay
2.11.31 Delay Register
Subaddress Default Reserved delay [2:0]
delay [2:0]: Sets delay channel with respect Cb/Cr block pixel delay pixel delay delay (default) pixel delay pixel delay
2.11.32 Control Register
Subaddress Default coring [3:0] gain [3:0]
coring [3:0]: 4-bit coring limit control value, unsigned linear control range from ±60, step size 1111 0001 0000 (default) gain [3:0]: 4-bit gain control values, unsigned linear control range from 15/16, step size 1/16 1111 15/16 0001 1/16 0000 disabled (default)
2-38
2.11.33 Register
Subaddress Default Reserved Genlock [2:0]
Genlock [2:0]: Reserved Reserved Reserved Reserved Reserved mode Reserved Reserved
2.11.34 Sync Control Register
Subaddress Default Reserved Polarity Polarity Polarity VS/VBLK HS/CS
Polarity FID: determines polarity terminal First field high, second field (default) First field low, second field high Polarity determines polarity terminal Active (default) Active high Polarity determines polarity terminal Active (default) Active high VS/VBLK: terminal outputs vertical sync (default) terminal outputs vertical blank HS/CS: terminal outputs horizontal sync (default) terminal outputs composite sync
2-39
2.11.35 Output Formatter Register
Subaddress Default Sampling rate YCbCr code range CbCr code Reserved Output format [2:0]
Sampling rate (changing this causes register settings reinitialized): ITU-R BT.601 sampling rate (default) Square pixel sampling rate YCbCr code range: ITU-R BT.601 coding range ranges from 940. range from 960.) Extended coding range range from 1016) (default) CbCr code: Offset binary code complement 512) (default) Straight binary code complement) Output format [2:0]: 10-bit 4:2:2 pixel rate) with embedded syncs (ITU-R BT.656) (default) 20-bit 4:2:2 (pixel rate) with separate syncs Reserved 10-bit 4:2:2 with separate syncs 100-111= Reserved NOTE: 10-bit mode also used output mode when (VBI raw) luminance processing control register subaddress (see Section 2.11.7).
2.11.36 Output Formatter Register
Subaddress Default Reserved Y[9:0] enable Reserved polarity Clock enable
Y[9:0] enable: Y[9:0] C[9:0] output enable Y[9:0] C[9:0] high impedance (default) [9:0] C[9:0] active polarity: Data clocked falling edge DATACLK (default) Data clocked rising edge DATACLK Clock enable: DATACLK outputs high-impedance (default). DATACLK outputs enabled.
2-40
2.11.37 Output Formatter Register
Subaddress Default [1:0] AVID [1:0] GLCO [1:0] [1:0]
[1:0]: terminal function select logic output. logic output. fast-switch input SCART support. logic input (default). AVID [1:0]: AVID terminal function select AVID logic output. AVID logic output. AVID active video indicator output. AVID logic input (default). GLCO [1:0]: GLCO terminal function select GLCO logic output. GLCO logic output. GCLO genlock output. GCLO logic input (default). [1:0]: terminal function select logic output. logic output. output. logic input (default).
2-41
2.11.38 Output Formatter Register
Subaddress Default VS/VBLK [1:0] HS/CS [1:0] [1:0] [1:0]
VS/VBLK [1:0]: terminal function select logic output. logic output. VS/VBLK vertical sync vertical blank output corresponding (VS/VBLK) sync control register subaddress (see Section 2.11.34). logic input (default). HS/CS [1:0]: terminal function select logic output. logic output. HS/CS horizontal sync composite sync output corresponding (HS/CS) sync control register subaddress (see Section 2.11.34). logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). functions only available 10-bit output mode.
2-42
2.11.39 Output Formatter Register
Subaddress Default [1:0] [1:0] [1:0] [1:0]
[1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default) [1:0]: terminal function select logic output. logic output. Reserved logic input (default). functions only available 10-bit output mode.
2-43
2.11.40 Output Formatter Register
Subaddress Default [1:0] [1:0] [1:0] [1:0]
[1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). [1:0]: terminal function select logic output. logic output. Reserved logic input (default). functions only available 10-bit output mode.
2.11.41 Clear Lost Lock Detect Register
Subaddress Default Reserved Clear lost lock detect
Clear lost lock detect: Clear (lost lock detect) status register subaddress (see Section 2.11.42). effect (default) Clears status register
2-44
2.11.42 Status Register
Subaddress
Read only
Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status
Peak white detect status: Peak white detected. Peak white detected. Line-alternating status: Nonline-alternating Line-alternating Field rate status: Lost lock detect: lost lock since this cleared Lost lock since this cleared. Color subcarrier lock status: Color subcarrier locked. Color subcarrier locked. Vertical sync lock status: Vertical sync locked. Vertical sync locked. Horizontal sync lock status: Horizontal sync locked. Horizontal sync locked. TV/VCR status:
2-45
2.11.43 Status Register
Subaddress
Read only
Reserved Weak signal detection switch polarity Field sequence status Reserved
Macrovision detection [2:0]
Weak signal detection: weak signal Weak signal mode switch polarity first line field: switch zero. switch one. Field sequence status: Even field field Macrovision detection [2:0]: copy protection pulses/pseudo syncs present (type 2-line colorstripe only present pulses/pseudo syncs 2-line colorstripe present (type Reserved Reserved 4-line colorstripe only present pulses/pseudo syncs 4-line colorstripe present (type
2.11.44 Gain Status Register
Subaddress 3Ch-3Dh
Read only
Subaddress Coarse gain [3:0] Fine gain [7:0] Fine gain [11:8]
Fine gain [11:0]: This register provides fine gain value sync channel. FGAIN [11:0] fine gain Pb_B register subaddress 4Ah-4Bh (see Section 2.11.53). 1111 1111 1111 1.9995 1000 0000 0000 0010 0000 0000 Coarse gain [3:0]: This register provides coarse gain value sync channel. CGAIN [3:0] coarse gain register subaddress (see Section 2.11.49). 1111 0101 0000 These gain status registers updated automatically TVP5146 decoder with manual gain control mode these register values updated TVP5146 decoder.
2-46
2.11.45 Video Standard Status Register
Subaddress
Read only
Autoswitch Reserved Video standard [2:0]
Autoswitch mode: Stand-alone (forced video standard) mode Autoswitch mode Video standard [2:0]: CVBS S-video Reserved NTSC (Combination-N) NTSC 4.43 SECAM Component video Reserved Component Component Reserved Reserved Reserved Reserved Reserved
This register contains information about detected video standard that decoder currently operating. When autoswitch code running, this register must tested determine which video standard been detected.
2.11.46 GPIO Input Register
Subaddress
Read only
input status: Input low. Input high. These status bits only valid when terminals used inputs their states updated every line.
2-47
2.11.47 GPIO Input Register
Subaddress
Read only
AVID GLCO
input terminal status: Input low. Input high. AVID input terminal status: Input low. Input high. GLCO input terminal status: Input Input high. input terminal status: Input low. Input high. input status: Input low. Input high. input status: Input low. Input high. input status: Input low. Input high. These status bits only valid when terminals used inputs their states updated every line.
2.11.48 Vertical Line Count Register
Subaddress 42h-43h
Read only
Subaddress Reserved V_CNT[7:0] V_CNT[9:8]
V_CNT[9:0] represents detected total number lines from previous frame.
2-48
2.11.49 Coarse Gain Register
Subaddress Default CGAIN [3:0] Reserved
CGAIN [3:0]: Coarse_Gain (CGAIN 1)/10, where CGAIN This register works only manual gain control mode. When active, writing value ignored. 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 (default) 0001 0000
2.11.50 Coarse Gain Register
Subaddress Default CGAIN [3:0] Reserved
CGAIN [3:0]: Coarse_Gain (CGAIN 2)/10, where CGAIN This register works only manual gain control mode. When active, writing value ignored. 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 (default) 0001 0000
2-49
2.11.51 Coarse Gain Register
Subaddress Default CGAIN [3:0] Reserved
CGAIN [3:0]: Coarse_Gain (CGAIN 3)/10, where CGAIN This register works only manual gain control mode. When active, writing value ignored. 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 (default) 0001 0000
2.11.52 Coarse Gain Register
Subaddress Default CGAIN [3:0] Reserved
CGAIN [3:0]: Coarse_Gain (CGAIN 4)/10, where CGAIN This register works only manual gain control mode. When active, writing value ignored. 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 (default) 0001 0000
2-50
2.11.53 Fine Gain Pb_B Register
Subaddress Default Subaddress Reserved 4Ah-4Bh 900h FGAIN [7:0] FGAIN [11:8]
FGAIN [11:0]: This fine gain applies component Pb/B. Fine_Gain (1/2048) FGAIN where FGAIN 4095 This register works only manual gain control mode. When active, writing value ignored. 1111 1111 1111 1.9995 1100 0000 0000 1001 0000 0000 1.125 (default) 1000 0000 0000 0100 0000 0000 0011 1111 1111 0000 0000 0000 Reserved
2.11.54 Fine Gain Y_G_Chroma Register
Subaddress Default Subaddress Reserved 4Ch-4Dh 900h FGAIN [7:0] FGAIN [11:8]
FGAIN [11:0]: This gain applies component channel S-video chroma. Fine_Gain (1/2048) FGAIN where FGAIN 4095 This register works only manual gain control mode. When active, writing value ignored. 1111 1111 1111 1.9995 1100 0000 0000 1001 0000 0000 1.125 (default) 1000 0000 0000 0100 0000 0000 0011 1111 1111 0000 0000 0000 Reserved
2-51
2.11.55 Fine Gain R_Pr Register
Subaddress Default Subaddress Reserved 4Eh-4Fh 900h FGAIN [7:0] FGAIN [11:8]
FGAIN [11:0]: This fine gain applies component Pb/B. Fine_Gain (1/2048) FGAIN where FGAIN 4095 This register works only manual gain control mode. When active, writing value ignored. 1111 1111 1111 1.9995 1100 0000 0000 1001 0000 0000 1.125 (default) 1000 0000 0000 0100 0000 0000 0011 1111 1111 0000 0000 0000 Reserved
2.11.56 Fine Gain CVBS_Luma Register
Subaddress Default Subaddress Reserved 50h-51h 900h FGAIN [7:0] FGAIN [11:8]
FGAIN [11:0]: This fine gain applies CVBS S-video luma. Fine_Gain (1/2048) FGAIN where FGAIN 4095 This register works only manual gain control mode. When active, writing value ignored. 1111 1111 1111 1.9995 1100 0000 0000 1001 0000 0000 1.125 (default) 1000 0000 0000 0100 0000 0000 0011 1111 1111 0000 0000 0000 Reserved
2.11.57 Version Register
Subaddress
Read only
version [7:0]
Version [7:0]: revision number
2-52
2.11.58 White Peak Processing Register
Subaddress Default Luma peak Reserved Color burst Sync height Luma peak Composite peak Color burst Sync height
Luma peak luma peak video amplitude reference back-end feed-forward type algorithm. Enabled (default) Disabled Color burst color burst amplitude video amplitude reference back-end. NOTE: available SECAM, component, video sources. Enabled (default) Disabled Sync height sync height video amplitude reference back-end feed-forward type algorithm. Enabled (default) Disabled Luma peak luma peak video amplitude reference front-end feedback type algorithm. Enabled (default) Disabled Composite peak: composite peak video amplitude reference front-end feedback type algorithm. NOTE: Required CVBS SCART (with color burst) video sources. Enabled (default) Disabled Color burst color burst amplitude video amplitude reference front-end feedback type algorithm. NOTE: available SECAM, component, video sources. Enabled (default) Disabled Sync height sync height video amplitude reference front-end feedback type algorithm. Enabled (default) Disabled NOTE: bits lower nibble logic (that amplitude reference selected), then front-end analog digital gains automatically nominal values 2304, respectively. bits upper nibble logic (that amplitude reference selected), then back-end gain automatically unity. input sync height greater than 100% AGC-adjusted output video amplitude becomes less than 100%, then back-end scale factor attempts increase contrast back restore video amplitude 100%.
2-53
2.11.59 Increment Speed Register
Subaddress Default Reserved increment speed [3:0]
increment speed: Adjusts gain increment speed. (slowest) (default) (fastest)
2.11.60 Increment Delay Register
Subaddress Default
increment delay [7:0]
increment delay: Number frames delay gain increments 1111 1111 0001 1110 (default) 0000 0000
2.11.61 Chip Register
Subaddress
Read only
Chip [7:0]
Chip [7:0]: This register identifies device Value
2.11.62 Chip Register
Subaddress
Read only
Chip [7:0]
Chip [7:0]: This register identifies device Value
2-54
2.11.63 Filter Mask Registers
Subaddress Default Subaddress
Filter mask Filter mask Filter mask Filter mask Filter mask Filter mask Filter mask Filter mask Filter mask Filter mask
Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern Filter pattern
NABTS system, packet prefix consists five bytes. Each byte contains data bits (D[3:0]) interlaced with Hamming protection bits (H[3:0]):
Only data portion D[3:0] from each byte applied teletext filter function with corresponding pattern bits P[3:0] mask bits M[3:0] (see Figure 2-27). filter ignores Hamming protection bits. system (PAL NTSC), packet prefix consists bytes. bytes contain three bits magazine number (M[2:0]) five bits address (R[4:0]), interlaced with eight Hamming protection bits H[7:0]:
mask bits enable filtering using corresponding pattern register. example, mask means that filter module must compare nibble pattern register first data transaction. these match, then true result returned. mask means that filter module must ignore that data transaction. programmed mask bits, then filter matches patterns returning true result (default 00h).
2-55
2.11.64 Filter Control Register
Subaddress Default Reserved Filter logic [1:0] Mode filter enable filter enable
Filter logic [1:0]: Allows different logic applied when combining decision filter filter follows: (default) NAND Mode: Indicates which teletext mode use. Teletext filter applies header bytes (default) Teletext filter applies header bytes filter enable: Provides enabling teletext filter function within VDP. Disabled (default) Enabled filter enable: Provides enabling teletext filter function within VDP. Disabled (default) Enabled filter matches filter mask then true result returned.
2-56
1P1[3] D1[3] 1P1[2] D1[2] 1P1[1] D1[1] 1P1[0] D1[0] 1M1[0] NIBBLE D2[3:0] 1P2[3:0] 1M2[3:0] PASS D3[3:0] 1P3[3:0] 1M3[3:0] D4[3:0] 1P4[3:0] 1M4[3:0] D5[3:0] 1P5[3:0] 1M5[3:0] FILTER Filter Logic NIBBLE NIBBLE NIBBLE Filter Enable NIBBLE 1M1[1] 1M1[2] 1M1[3]
PASS
D1.D5 2P1.2P5 2M1.2M5 FILTER
PASS Filter Enable
Figure 2-27. Teletext Filter Function
2.11.65 FIFO Word Count Register
Subaddress
Read only
FIFO word count [7:0]
FIFO word count [7:0]: This register provides number words FIFO. NOTE: word equals bytes.
2-57
2.11.66 FIFO Interrupt Threshold Register
Subaddress Default Threshold [7:0]
Threshold [7:0]: This register programmed trigger interrupt when number words FIFO exceeds this value. NOTE: word equals bytes.
2.11.67 FIFO Reset Register
Subaddress Default Reserved FIFO reset
FIFO reset: Writing data this register clears FIFO data registers (CC, WSS, VITC VPS). After clearing them, this register automatically cleared.
2.11.68 FIFO Output Control Register
Subaddress Default Reserved Host access enable
Host access enable: This register programmed allow host port access FIFO allow data video output. Output FIFO data video output Y[9:2] (default) Allow host port access FIFO data
2.11.69 Line Number Interrupt Register
Subaddress Default Field enable Field enable
Line number [5:0]
Field enable: Interrupt disabled (default) Interrupt enabled Field enable: Interrupt disabled (default) Interrupt enabled Line number [5:0]: Interrupt line number (default 00h) This register programmed trigger interrupt when video line number exceeds this value bits [5:0]. This interrupt must enabled address F4h. NOTE: line number value invalid does generate interrupt.
2-58
2.11.70 Pixel Alignment Register
Subaddress Default Subaddress Reserved C2h-C3h 01Eh
Pixel alignment [7:0] Pixel alignment [9:8]
Pixel alignment [9:0]: These registers form 10-bit horizontal pixel position from falling edge horizontal sync, where controller initiates program from line standard next line standard. example, previous line teletext next line closed caption. This value must that switch occurs after previous transaction cleared delay VDP, early enough allow values programmed before current settings required. default value 0x1E been tested with every standard supported here. value needed only custom standard use.
2.11.71 Line Start Register
Subaddress Default
line start [7:0]
line start [7:0]: Sets line starting address This register must properly before enabling line mode registers. processor works only region this register line stop register subaddress (see Section 2.11.72).
2.11.72 Line Stop Register
Subaddress Default
line stop [7:0]
line stop [7:0]: Sets stop line address
2.11.73 Global Line Mode Register
Subaddress Default
Global line mode [7:0]
Global line mode [7:0]: processing multiple lines start line register subaddress stop line register subaddress D7h. Global line mode register same definition general line mode registers. General line mode priority over global line mode.
2-59
2.11.74 Full Field Enable Register
Subaddress Default Reserved Full field enable
Full field enable: Disabled full field mode (default) Enabled full field mode This register enables full field mode. this mode, lines outside vertical blank area lines line mode register programmed with sliced with definition full field mode register subaddress DAh. Values other than line mode registers allow different slice mode that particular line.
2.11.75 Full Field Mode Register
Subaddress Default
Full field mode [7:0]
Full field mode [7:0]: This register programs specific standard full field mode. standard. Individual line settings take priority over full field register. This allows each line programmed independently have remaining lines full field mode. full field mode register same definition line mode registers (default FFh). Global line mode priority over full field mode.
2.11.76 VBUS Data Access With VBUS Address Increment Register
Subaddress Default VBUS data [7:0]
VBUS data [7:0]: VBUS data register VBUS single byte read/write transaction.
2.11.77 VBUS Data Access With VBUS Address Increment Register
Subaddress Default VBUS data [7:0]
VBUS data [7:0]: VBUS data register VBUS multibyte read/write transaction. VBUS address autoincremented after each data byte read/write.
2-60
2.11.78 FIFO Read Data Register
Subaddress
Read only
FIFO read data [7:0]
FIFO read data [7:0]: This register provided access FIFO data through host port. forms teletext data come directly from FIFO, while other forms data programmed come from registers from FIFO. host port used read data from FIFO, then (host access enable) FIFO output control register subaddress must (see Section 2.11.68).
2.11.79 VBUS Address Access Register
Subaddress Default Subaddress
VBUS address [7:0] VBUS address [15:8] VBUS address [23:16]
VBUS address [23:0]: VBUS 24-bit wide internal bus. user must program these registers 24-bit address internal register accessed host port indirect access mode.
2-61
2.11.80 Interrupt Status Register
Subaddress
Read only
FIFO THRS VITC Line
FIFO THRS: FIFO threshold passed, unmasked passed Passed TTX: Teletext data available unmasked available Available WSS: data available unmasked available Available VPS: data available unmasked available Available VITC: VITC data available unmasked available Available field data available unmasked available Available field data available unmasked available Available Line: Line number interrupt unmasked available Available also interrupt status register subaddress (see Section 2.11.81). host interrupt status registers represent interrupt status without applying mask bits.
2-62
2.11.81 Interrupt Status Register
Subaddress
Read only
Reserved Macrovision status changed Standard changed FIFO full
Macrovision status changed: unmasked Macrovision status unchanged Macrovision status changed Standard changed: unmasked Video standard unchanged Video standard changed FIFO full: unmasked FIFO full FIFO full during write FIFO FIFO full error flag when current line data cannot enter FIFO. example, FIFO only bytes left teletext current line, then FIFO full error flag set, data written because entire teletext line does fit. However, next line closed caption requiring only bytes data plus header, then this goes into FIFO even full error flag set.
2-63
2.11.82 Interrupt Status Register
Subaddress
Read only
FIFO THRS VITC Line
FIFO THRS: FIFO threshold passed, masked passed Passed TTX: Teletext data available masked available Available WSS: data available masked available Available VPS: data available masked available Available VITC: VITC data available masked available Available field data available masked available Available field data available masked available Available Line: Line number interrupt masked available Available also interrupt status register subaddress (see Section 2.11.83). interrupt status registers represent interrupt status after applying mask bits. Therefore, status bits result logical between status mask bits. external interrupt terminal derived from this register function nonmasked interrupts this register. Reading data from corresponding register does clear status flags automatically. These flags reset using corresponding bits interrupt clear registers.
2-64
2.11.83 Interrupt Status Register
Subaddress
Read only
Reserved Macrovsion status changed Standard changed FIFO full
Macrovision status changed: Macrovision status changed masked Macrovision status changed Macrovision status changed Standard changed: Standard changed masked Video standard changed Video standard changed FIFO full: Full status FIFO masked FIFO full FIFO full during write FIFO, interrupt mask register subaddress details (see Section 2.11.85)
2-65
2.11.84 Interrupt Mask Register
Subaddress Default FIFO THRS VITC Line
FIFO THRS: FIFO threshold passed mask Disabled (default) Enabled FIFO_THRES interrupt TTX: Teletext data available mask Disabled (default) Enabled available interrupt WSS: data available mask Disabled (default) Enabled available interrupt VPS: data available mask Disabled (default) Enabled available interrupt VITC: VITC data available mask Disabled (default) Enabled VITC available interrupt field data available mask Disabled (default) Enabled CC_field available interrupt field data available mask Disabled (default) Enabled CC_field available interrupt Line: Line number interrupt mask Disabled (default) Enabled Line_INT interrupt also interrupt mask register subaddress (see Section 2.11.85). host interrupt mask registers used external processor mask unnecessary interrupt sources interrupt status register bits, external interrupt terminal. external interrupt generated from nonmasked interrupt flags.
2-66
2.11.85 Interrupt Mask Register
Subaddress Default Reserved Macrovision status changed Standard changed FIFO full
Macrovision status changed: Macrovision status changed mask Macrovision status unchanged Macrovision status changed Standard changed: Standard changed mask Disabled (default) Enabled video standard changed FIFO full: FIFO full mask Disabled (default) Enabled FIFO full interrupt
2-67
2.11.86 Interrupt Clear Register
Subaddress Default FIFO THRS VITC Line
FIFO THRS: FIFO threshold passed clear effect (default) Clear (FIFO_THRS) interrupt status register subaddress TTX: Teletext data available clear effect (default) Clear (TTX available) interrupt status register subaddress WSS: data available clear effect (default) Clear (WSS available) interrupt status register subaddress VPS: data available clear effect (default) Clear (VPS available) interrupt status register subaddress VITC: VITC data available clear Disabled (default) Clear (VITC available) interrupt status register subaddress field data available clear Disabled (default) Clear field available) interrupt status register subaddress field data available clear Disabled (default) Clear field available) interrupt status register subaddress Line: Line number interrupt clear Disabled (default) Clear (line interrupt available) interrupt status register subaddress also interrupt clear register subaddress (see Section 2.11.87). host interrupt clear registers used external processor clear interrupt status bits host interrupt status registers. When nonmasked interrupts remain registers, external interrupt terminal also becomes inactive.
2-68
2.11.87 Interrupt Clear Register
Subaddress Default Reserved Macrovision status changed Standard changed FIFO full
Macrovision status changed: Clear Macrovision status changed flag effect (default) Clear (Macrovision status changed) interrupt status register subaddress interrupt status register subaddress Standard changed: Clear standard changed flag effect (default) Clear (video standard changed) interrupt status register subaddress interrupt status register subaddress FIFO full: Clear FIFO full flag effect (default) Clear (FIFO full flag) interrupt status register subaddress interrupt status register subaddress
2-69
2.12 VBUS Register Definitions
2.12.1 Closed Caption Data Register
Subaddress 051Ch-80 051Fh
Read only
Subaddress 051Ch 051Dh 051Eh 051Fh Closed caption field byte Closed caption field byte Closed caption field byte Closed caption field byte
These registers contain closed caption data arranged bytes field.
2.12.2 Data Register
Subaddress 0520h-80 0526h
NTSC (CGMS): Read only
Subaddress 0520h 0521h 0522h 0523h 0524h 0525h 0526h Reserved field byte field byte field byte Byte field byte field byte field byte
These registers contain wide screen signaling data NTSC. Bits represent word aspect ratio. Bits represent word header code word Bits 6-13 represent word copy control. Bits 14-19 represent word CRC. PAL/SECAM: Read only
Subaddress 0520h 0521h 0522h 0523h 0524h 0525h 0526h Reserved Reserved Reserved field byte field byte Byte field byte field byte
PAL/SECAM: Bits represent group aspect ratio. Bits represent group enhanced services. Bits 8-10 represent group subtitles. Bits 11-13 represent group others.
2-70
2.12.3 VITC Data Register
Subaddress 052Ch-80 0534h
Read only
Subaddress 052Ch 052Dh 052Eh 052Fh 0530h 0531h 0532h 0533h 0534h
VITC frame byte VITC frame byte VITC seconds byte VITC seconds byte VITC minutes byte VITC minutes byte VITC hours byte VITC hours byte VITC byte
These registers contain VITC data.
2.12.4 V-Chip Rating Block Register
Subaddress 0540h
Read only
Reserved 14-D PG-D Reserved MA-L 14-L PG-L Reserved
parental guidelines rating block 14-D: When incoming video program TV-14-D rated, then this high PG-D: When incoming video program TV-PG-D rated, then this high MA-L: When incoming video program TV-MA-L rated, then this high 14-L: When incoming video program TV-14-L rated, then this high PG-L: When incoming video program TV-PG-L rated, then this high
2.12.5 V-Chip Rating Block Register
Subaddress 0541h
Read only
MA-S 14-S PG-S Reserved MA-V 14-V PG-V Y7-FV
parental guidelines rating block MA-S: When incoming video program TV-MA-S rated, then this high 14-S: When incoming video program TV-14-S rated, then this high PG-S: When incoming video program TV-PG-S rated, then this high MA-V: When incoming video program TV-MA-V rated, then this high 14-V: When incoming video program TV-14-V rated, then this high PG-V: When incoming video program TV-PG-S rated, then this high Y7-FV: When incoming video program TV-Y7-FV rated, then this high
2-71
2.12.6 V-Chip Rating Block Register
Subaddress 0542h
Read only
None TV-MA TV-14 TV-PG TV-G TV-Y7 TV-Y None
parental guidelines rating block None: block intended TV-MA: When incoming video program TV-MA rated Parental Guidelines Rating, then this high TV-14: When incoming video program TV-14 rated Parental Guidelines Rating, then this high TV-PG: When incoming video program TV-PG rated Parental Guidelines Rating, then this high TV-G: When incoming video program TV-G rated Parental Guidelines Rating, then this high TV-Y7: When incoming video program TV-Y7 rated Parental Guidelines Rating, then this high TV-Y: When incoming video program TV-G rated Parental Guidelines Rating, then this high None: block intended
2.12.7 V-Chip MPAA Rating Data Register
Subaddress 0543h
Read only
Rated NC-17 PG-13
MPAA rating block (E5h): Rated: When incoming video program Rated rated MPAA Rating, then this high When incoming video program rated MPAA Rating, then this high NC-17: When incoming video program NC-17 rated MPAA Rating, then this high When incoming video program rated MPAA Rating, then this high PG-13: When incoming video program PG-13 rated MPAA Rating, then this high When incoming video program rated MPAA Rating, then this high When incoming video program rated MPAA Rating, then this high N/A: When incoming video program rated MPAA Rating, then this high
2-72
2.12.8 General Line Mode Line Address Register
Subaddress 0600h-80 0611h
(default line mode FFh, address 00h)
Subaddress 0600h 0601h 0602h 0603h 0604h 0605h 0606h 0607h 0608h 0609h 060Ah 060Bh 060Ch 060Dh 060Eh 060Fh 0610h 0611h Line mode Line address Line mode Line address Line mode Line address Line mode Line address Line mode Line address Line mode Line address Line mode Line address Line mode Line address Line mode
Line address
Line address [7:0]: Line number processed line mode register (default 00h) Line mode [7:0]: Bits [2:0]: Disabled filters Enabled filters teletext (Null byte filter) (default) Send sliced data registers only (default) Send sliced data FIFO registers, teletext data only goes FIFO (default) Allow data with errors FIFO allow data with errors FIFO (default) Disabled error detection correction Enabled error detection correction (teletext only) (default) Field Field (default) Teletext (WST625, Chinese teletext, NABTS 525) (US, Europe, Japan, China) (525, 625) VITC (PAL only), (NTSC only) USER USER Reserved (active video) (default)
2-73
2.12.9 VPS/Gemstar Data Register
Subaddress 0700h-80 070Ch
VPS: Read only
Subaddress 0700h 0701h 0702h 0703h 0704h 0705h 0706h 0707h 0708h 0709h 070Ah 070Bh 070Ch byte byte byte byte byte byte byte byte byte byte byte byte byte
These registers contain entire data line except clock run-in code start code. Gemstar: Read only
Subaddress 0700h 0701h 0702h 0703h 0704h 0705h 0706h 0707h 0708h 0709h 070Ah 070Bh 070Ch
Gemstar frame code Gemstar byte Gemstar byte Gemstar byte Gemstar byte Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
2.12.10 FIFO Read Register
Subaddress 1904h
Read only
FIFO data [7:0]
FIFO data [7:0]: This register provided access FIFO data through host port. forms teletext data come directly from FIFO, while other forms data programmed come from registers from FIFO. host port used read data from FIFO, then (host access enable) FIFO output control register subaddress must
2-74
2.12.11 Interrupt Configuration Register
Subaddress Default 0060h Reserved Polarity Reserved
Polarity: Interrupt terminal polarity Active high (default) Active
2-75
2-76
Electrical Specifications
Absolute Maximum Ratings
IOVDD DVDD DGND -0.2 A33VDD (see Note A18GND (see Note -0.3 A18VDD (see Note A33GND (see Note -0.2 Digital input voltage, DGND -0.5 Digital output voltage, DGND -0.5 Analog input voltage range AGND -0.2 Operating free-air temperature, 70°C Storage temperature, Tstg -65°C 150°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: CH1_A33VDD, CH2_A33VDD, CH3_A33VDD, CH4_A33VDD CH1_A33GND, CH2_A33GND, CH3_A33GND, CH4_A33GND CH1_A18VDD, CH2_A18VDD, CH3_A18VDD, CH4_A18VDD, A18VDD_REF, PLL_A18VDD CH1_A18GND, CH2_A18GND, CH3_A18GND, CH4_A18GND
Supply voltage range:
Recommended Operating Conditions
IOVDD DVDD AVDD33 AVDD18 VI(P-P) Digital supply voltage Digital supply voltage Analog supply voltage Analog supply voltage Analog input voltage (ac-coupling necessary) Digital input voltage high (Note Digital input voltage (Note Output current, Vout Output current, Vout Operating free-air temperature 1.65 1.65 IOVDD IOVDD 1.95 1.95 UNIT
NOTES: Exception: AVDD18 XTAL1 terminal Exception: AVDD18 XTAL1 terminal
3.2.1
Crystal Specifications
CRYSTAL SPECIFICATIONS 14.31818 UNIT
Frequency Frequency tolerance
Electrical Characteristics
minimum/maximum values: IOVDD DVDD 1.65 1.95 AVDD33 AVDD18 1.65 1.95 70°C typical values: IOVDD DVDD AVDD33 AVDD18 25°C
3.3.1
Electrical Characteristics
PARAMETER TEST CONDITIONS CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS 66.2 47.8 79.3 334.5 design IOVDD IOVDD UNIT
IDDIO(D) IDD(D) IDD33(A) IDD18(A) PTOT PSAVE PDOWN Ilkg
3.3-V digital supply current 1.8-V digital supply current 3.3-V analog supply current 1.8-V analog supply current Total power dissipation (normal operation) Total power dissipation (power save) Total power dissipation (power down) Input leakage current Input capacitance Output voltage high Output voltage
NOTE Measured with load parallel
3.3.2
Vi(pp) XTALK
Analog Processing Converters
PARAMETER Input impedance, analog video inputs Input capacitance, analog video inputs Input voltage range Gain control range Differential nonlinearity Integral nonlinearity Frequency response Crosstalk Signal-to-noise ratio, channels Gain match (Note Noise spectrum Differential phase Differential gain only only Multiburst IRE) MHz, VP-P Full scale, Luma ramp (100 full, tilt-null) Modulated ramp Modulated ramp 1.1% ±1.5% 1.5% design design Ccoupling 0.50 0.75 -0.9 TEST CONDITIONS UNIT
NOTE Component inputs only
3.3.3
Timing
3.3.3.1 Clocks, Video Data, Sync Timing
PARAMETER Duty cycle DATACLK High time, DATACLK time, DATACLK Fall time, DATACLK Rise time, DATACLK TEST CONDITIONS (see Note 18.5 18.5 UNIT
Output delay time NOTE
DATACLK
AVID, Valid Data Valid Data
Figure 3-1. Clocks, Video Data, Sync Timing
3.3.3.2 Host Port Timing
PARAMETER fI2C free time between STOP START Data hold time Data setup time Setup time (repeated) START condition Setup time STOP condition Hold time (repeated) START condition Rise time VC1(SDA) VC0(SCL) signal Fall time VC1(SDA) VC0(SCL) signal Capacitive load each line clock frequency Stop Start TEST CONDITIONS Stop UNIT
(SDA)
Data
(SCL)
Change Data
Figure 3-2. Host Port Timing
Example Register Settings
following example register settings provided only reference. These settings, given assumed input connector, video format, output format, TVP5146 decoder provide video output. Example register settings other features data processor provided here.
Example
4.1.1 Assumptions
Composite (VI_1_A) (default) NTSC SECAM (default)
Input connector: Video format:
NOTE: NTSC-443, PAL-Nc, PAL-M masked from autoswitch process default. autoswitch mask register address 04h. Output format: 10-bit ITU-R BT.656 with embedded syncs (default)
4.1.2
Recommended Settings
Recommended writes: given assumptions, only write required. other registers default. register address Luminance processing control register data Optimizes trap filter selection NTSC register address Chrominance processing control register data Optimizes chrominance filter selection NTSC register address Output formatter register data Enables YCbCr output clock output NOTE: HS/CS, VS/VBLK, AVID, FID, GLCO logic inputs default. output formatter registers addresses 36h, respectively.
Example
4.2.1 Assumptions
S-video [VI_2_C (luma), VI_1_C (chroma)] NTSC 443), SECAM 10-bit 4:2:2 YCbCr with discrete sync outputs
Input connector: Video format: Output format:
4.2.2
Recommended Settings
Recommended writes: This setup requires additional writes output discrete sync 10-bit 4:2:2 data, autoswitch between video formats mentioned above. register address Input select register data Sets luma VI_2_C chroma VI_1_C register address Autoswitch mask register data Includes NTSC autoswitch register address Luminance processing control register data Optimizes trap filter selection NTSC register address Chrominance processing control register data Optimizes chrominance filter selection NTSC register address Output formatter register data Selects 10-bit 4:2:2 output format register address Output formatter register data Enables YCbCr output clock output register address Output formatter register data Enables sync outputs
Example
4.3.1 Assumptions
Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)] NTSC 443), SECAM 20-bit 4:2:2 YCbCr with discrete sync outputs
Input connector: Video format: Output format:
4.3.2
Recommended Settings
Recommended writes: This setup requires additional writes output discrete sync 20-bit 4:2:2 data, autoswitch between video formats mentioned above. register address Input select register data Sets VI_1_B, VI_2_B, VI_3_B register address Autoswitch mask register data Includes NTSC autoswitch register address Luminance processing control register data Optimizes trap filter selection NTSC register address Chrominance processing control register data Optimizes chrominance filter selection NTSC register address Output formatter register data Selects 20-bit 4:2:2 output format register address Output formatter register data Enables YCbCr output clock output register address Output formatter register data Enables sync outputs
Application Information
Application Example
XTAL1 XTAL2 14.31818 A3.3VDD A1.8VDD VS/VBLK HS/CS XTAL1 XTAL2
IOVDD3.3V DVDD1.8V
VI_1A VI_1B VI_1C VI_2A VI_2B VI_2C VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD CH4_A33VDD
CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK HS/CS DGND DVDD IOGND IOVDD
VI_1_A
TVP5146PFP
C_6/RED C_7/GREEN C_8/BLUE C_9/FSO DGND DVDD IOGND IOVDD DGND DVDD
VI_3A VI_3B VI_3C
VI_4A IOVDD GLCO/I2CA
CH4_A33GND VI_4A CH4_A18GND CH4_A18VDD AGND DGND INTREQ DVDD DGND PWDN RESETB AVID GLCO/I2CA IOVDD IOGND DATACLK
DATACLK GLCO/I2CA AVID RESETB PWDN INTREQ
Address selection Base Addr. 0xBA Base Addr. 0xB8
NOTE: XTAL1 connected clock source, input voltage high must Terminals must connected ground through pulldown resistors.
Figure 5-1. Application Example
Designing With PowerPADt Devices
TVP5146 device housed high-performance, thermally enhanced, 80-terminal PowerPAD package package designator: 80PFP). PowerPAD package does require special considerations except note that thermal pad, which exposed bottom device, metallic thermal electrical conductor. Therefore, implementing PowerPAD features, solder masks other assembly techniques) required prevent inadvertent shorting exposed thermal connection etches vias under package. recommended option, however, etches signal vias under device, have only grounded thermal land explained following paragraphs. Although actual size exposed vary, minimum size required keep-out area 80-terminal PowerPAD package recommended that there thermal land, which area solder-tinned copper, underneath PowerPAD package. thermal land varies size, depending PowerPAD package being used, construction, amount heat that needs removed. addition, thermal land contain numerous thermal vias depending construction. Other requirements using thermal lands thermal vias detailed PowerPADt Thermally Enhanced Package technical brief, literature number SLMA002, available pages http://www.ti.com. TVP5146 device, this thermal land must grounded low-impedance ground plane device. This improves only thermal performance also electrical grounding device. also recommended that device ground terminal landing pads connected directly grounded thermal land. land size must large possible without shorting device signal terminals. thermal land soldered exposed thermal using standard reflow soldering techniques. While thermal land electrically floated configured remove heat external heat sink, recommended that thermal land connected impedance ground plane device. More information obtained from Recommendations Layout applicaton report, literature number SLLA020.
PowerPAD trademark Texas Instruments.
Mechanical Data
(S-PQFP-G80)
0,27 0,17
PowerPAD PLASTIC QUAD FLATPACK
0,50
0,08
Thermal (see Note
0,13
9,50 12,20 11,80 14,20 13,80 1,05 0,95
Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane 0°-7°
1,20
0,08 4146925/B 08/03
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion. This package designed soldered thermal board. Refer Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature SLMA002 information regarding recommended board layout. This document available www.ti.com <http://www.ti.com>. Falls within JEDEC MS-026
PowerPAD trademark Texas Instruments.
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