Wide Operating Voltage Range Operation From Very Slow Input Trans

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Wide Operating Voltage Range Operation From Very Slow Input Trans

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SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE GATES WITH SCHMITT TRIGGER INPUTS
Wide Operating Voltage Range Operation From Very Slow Input
Transitions Same Pinouts 'HC32 Outputs Drive LSTTL Loads Power Consumption, 20-µA Typical ±4-mA Output Drive Input Current Temperature-Compensated Threshold Levels High Noise Immunity
SN54HC7032 PACKAGE SN74HC7032 PACKAGE (TOP VIEW)
SN54HC7032 PACKAGE (TOP VIEW)
description/ordering information
these devices, each circuit functions quadruple gate. They perform Boolean function positive logic. However, because Schmitt action, inputs have different input threshold levels positive- negative-going signals. These circuits temperature compensated triggered from slowest input ramps still give clean jitter-free output signals. ORDERING INFORMATION
PDIP PACKAGE Tube Tube 85°C -40°C SOIC CDIP 125°C -55°C Reel 2500 Reel Reel 2000 Tube Tube ORDERABLE PART NUMBER SN74HC7032N SN74HC7032D SN74HC7032DR SN74HC7032DT SN74HC7032NSR SNJ54HC7032J SNJ54HC7032W
internal connection
LCCC Tube SNJ54HC7032FK SNJ54HC7032FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 2003, Texas Instruments Incorporated
DALLAS, TEXAS 75265
TOP-SIDE MARKING SN74HC7032N HC7032 HC7032 SNJ54HC7032J SNJ54HC7032W
SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE GATES WITH SCHMITT TRIGGER INPUTS
logic diagram, each gate (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 86°C/W package 80°C/W package 76°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
recommended operating conditions (see Note
SN54HC7032 Supply voltage Low-level input voltage Input voltage Output voltage 3.15 1.35 SN74HC7032 3.15 1.35 UNIT
High-level input voltage
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE GATES WITH SCHMITT TRIGGER INPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -5.2 1.55 3.98 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.15 ±0.1 0.26 0.26 ±100 3.15 2.45 SN54HC7032 1.55 ±1000 3.15 2.45 SN74HC7032 1.55 3.84 5.34 0.33 0.33 ±1000 3.15 2.45 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 25°C SN54HC7032 SN74HC7032 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance gate TEST CONDITIONS load UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE GATES WITH SCHMITT TRIGGER INPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point (see Note In-Phase Output Input tPLH tPHL Out-of-Phase Output Input tPLH tPHL
LOAD CIRCUIT
VOLTAGE WAVEFORM INPUT RISE FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
NOTES: includes probe test-fixture capacitance. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
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MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
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Wide Operating Voltage Range Operation From Very Slow Input Trans

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