State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs, Ceramic Flat Package
SN54ABT533 PACKAGE SN74ABT533A PACKAGE (TOP VIEW)
SN54ABT533 PACKAGE (TOP VIEW)
description
These octal transparent D-type latches with 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. When latch-enable (LE) input high, outputs follow complements data inputs. When taken low, outputs latched inverse levels inputs.
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. Previously stored data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN54ABT533 characterized operation over full military temperature range -55°C 125°C. SN74ABT533A characterized operation from -40°C 85°C.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic symbol
logic diagram (positive logic)
Seven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT533 SN74ABT533A Input clamp current, Output clamp current, Package thermal impedance, (see Note package 115°C/W package 97°C/W package 67°C/W package 128°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51, except through-hole packages, which trace length zero.
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54ABT533 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate SN74ABT533A UNIT ns/V
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high Outputs high input Other inputs Outputs Outputs disabled Outputs high Outputs Outputs disabled -140 ±150 -180 -180 ±150 -180 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT533 -1.2 SN74ABT533A -1.2 UNIT
products compliant MIL-PRF-38535, this parameter does apply. typical values more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN54ABT533 25°C Pulse duration, high Setup time, data before Hold time, data after High High UNIT
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN74ABT533A 25°C Pulse duration, high Setup time, data before Hold time, data after High High UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN54ABT533 PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN74ABT533A PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
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MECHANICAL DATA
MCFP006B JANUARY 1995 REVISED JULY 2003
(R-GDFP-F20)
0.300 (7,62) 0.245 (6,22)
CERAMIC DUAL FLATPACK
Base Seating Plane
0.045 (1,14) 0.026 (0,66)
0.100 (2,54) 0.045 (1,14) 0.320 (8,13)
0.009 (0,23) 0.004 (0,10)
0.022 (0,56) 0.015 (0,38)
0.050 (1,27) 0.540 (13,72)
0.005 (0,13) Places
0.370 (9,40) 0.250 (6,35)
0.370 (9,40) 0.250 (6,35) 4040180-4 07/03
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with ceramic using glass frit. Index point provided terminal identification only. Falls within Mil-Std 1835 GDFP2-F20
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MECHANICAL DATA
MLCC006B OCTOBER 1996
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
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MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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