SLES092A OCTOBER 2003 REVISED AUGUST 2004 24-BIT, SAMPLING ENHANC

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SLES092A OCTOBER 2003 REVISED AUGUST 2004 24-BIT, SAMPLING ENHANC

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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
24-BIT, SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
FEATURES 24-Bit Resolution Analog Performance (VCC
Power Supply: Single Supply Small 16-Lead SSOP Package, Lead-Free APPLICATIONS Receivers Movie Players Add-On Cards High-End Audio Players HDTV Receivers Audio Systems Other Applications Requiring 24-Bit Audio DESCRIPTION
PCM1753/54/55 CMOS, monolithic, integrated circuit, which includes stereo digital-to-analog converters support circuitry small 16-lead SSOP package. data converters TI's enhanced multilevel delta-sigma architecture, which employs 4th-order noise shaping 8-level amplitude quantization achieve excellent dynamic performance improved tolerance clock jitter. PCM1753/54/55 accepts industrystandard audio data formats with 24-bit data, providing easy interfacing audio decoder chips. Sampling rates supported. full user-programmable functions accessible through three-wire serial control port, which supports register write functions. PCM1753/55 compatible with PCM1748, PCM1742, PCM1741, except
Dynamic Range: SNR: Typical THD+N: 0.002%, Typical Full-Scale Output: p-p, Typical
Oversampling Digital Filter:
Stop-Band Attenuation: Pass-Band Ripple: ±0.04
Sampling Frequency: System Clock:
1152 With Auto Detect
Software Control (PCM1753, PCM1755):
Accepts 16-, 18-, 20-, 24-Bit Audio Formats: Standard, I2S, Left-Justified Digital Attenuation: dB/Step Digital De-Emphasis Digital Filter Rolloff: Sharp Slow Soft Mute Zero Flags Each Output Open-Drain Output Zero Flag (PCM1755) 16-Bit Word, Right-Justified 44.1 Digital De-Emphasis Soft Mute Zero Flag R-Channel Common Output
Hardware Control (PCM1754):
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Audio Precision System trademarks Audio Precision, Inc. Other trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2004, Texas Instruments Incorporated
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE CODE 16DBQ 16DBQ 16DBQ OPERATION TEMPERATURE RANGE -25°C 85°C 25°C -40°C 85°C 40°C -25°C 85°C 25°C PACKAGE MARKING PCM1753 PCM1754 PCM1755 ORDERING NUMBER(1) PCM1753DBQ PCM1753DBQ PCM1754DBQ PCM1755DBQ
TRANSPORT MEDIA Tube Tape reel Tube Tape reel Tube Tape reel
16-pin SSOP 16-pin SSOP 16-pin SSOP
PCM1753DBQR PCM1754DBQ PCM1754DBQR PCM1755DBQ PCM1755DBQR
most current specification package information, site www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage: Ground voltage differences: AGND, DGND Input voltage Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature reflow, peak)
-0.3 ±0.1 -0.3 -40°C 125°C -55°C 150°C 150°C 260°C, 260°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
specifications 25°C, 44.1 kHz, system clock 24-bit data, unless otherwise noted PARAMETER Resolution DATA FORMAT Audio data Audio-data interface format PCM1753 PCM1755 PCM1754 Audio data Audio-data length Audio data format Sampling frequency System clock frequency PCM1753 PCM1755 PCM1754 Standard, I2S, left-justified I2S, standard 16-, 18-, 20-, 24-bit, selectable 16-24-bit (I2S), 16-bit (standard) first, complement 1152 TEST CONDITIONS PCM1753DBQ, PCM1754DBQ, PCM1755DBQ Bits UNIT
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
specifications 25°C, 44.1 kHz, system clock 24-bit data, unless otherwise noted PARAMETER DIGITAL INPUT/OUTPUT Logic family
TEST CONDITIONS
PCM1753DBQ, PCM1754DBQ, PCM1755DBQ compatible
UNIT
Input logic level Input logic current Output logic level 44.1 THD+N VOUT 44.1 THD+N VOUT fS=192 EIAJ, A-weighted, 44.1 Dynamic range A-weighted, A-weighted, EIAJ, A-weighted, 44.1 Signal noise Signal-to-noise ratio A-weighted, A-weighted, 44.1 Channel separation Level linearity error =192 VOUT
0.002% 0.003% 0.004% 0.65% 0.8% 0.95% ±0.5 Vp-p 0.006%
DYNAMIC PERFORMANCE
ACCURACY Gain error Gain mismatch, channel-to-channel Bipolar zero error ANALOG OUTPUT Output voltage Center voltage Load impedance DIGITAL FILTER PERFORMANCE FILTER CHARACTERISTICS (SHARP ROLLOFF) Pass band Stop band Pass-band ripple Stop-band attenuation Stop band 0.546 ±0.04 0.546 ±0.04 0.454 AC-coupled load Full scale VOUT
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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ELECTRICAL CHARACTERISTICS (CONTINUED)
specifications 25°C, 44.1 kHz, system clock 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS PCM1753DBQ, PCM1754DBQ, PCM1755DBQ FILTER CHARACTERISTICS (SLOW ROLLOFF, PCM1753/PCM1755) Pass band Stop band Pass-band ripple Stop-band attenuation Delay time De-emphasis error ANALOG FILTER PERFORMANCE Frequency response POWER SUPPLY REQUIREMENTS
UNIT
0.198
±0.5 0.884
±0.5 Stop band 0.884 18/fs ±0.1 44.1 44.1 -0.03 -0.20
Voltage range Supply current
Power dissipation TEMPERATURE RANGE Operation temperature
PCM1753 PCM1755 PCM1754 16-pin SSOP
°C/W
Thermal resistance
Pins SCK, BCK, DATA, LRCK. Pins 13-15: (PCM1753/PCM1755). Pins 12-15: TEST, DEMP, MUTE, (PCM1754). Pins ZEROR, ZEROL (PCM1753). ZEROA (PCM1754). Pins ZEROR, ZEROL (PCM1753/PCM1755). ZEROA (PCM1754). Analog performance specifications measured using System Twot Cascade audio measurement system Audio Precisiont averaging mode. Conditions 192-kHz operation system clock oversampling rate register
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
ASSIGNMENTS
PCM1753/PCM1755 (TOP VIEW) PCM1754 (TOP VIEW)
DATA LRCK DGND VOUTL VOUTR
ZEROL/NA ZEROR/ZEROA VCOM AGND
DATA LRCK DGND VOUTL VOUTR
MUTE DEMP TEST ZEROA VCOM AGND
FUNCTIONAL BLOCK DIAGRAM
LRCK DATA Audio Serial Port 4y/8y Oversampling Digital Filter Function Control Output Low-Pass Filter VOUTL
(FMT) Serial Control Port
Enhanced Multilevel Delta-Sigma Modulator
VCOM
(MUTE)
(DEMP)
Output Low-Pass Filter
VOUTR
(TEST) System Clock Manager
System Clock
Zero Detect
Power Supply
DGND
Open-Drain Output PCM1755
PCM1754
ZEROR/ZEROA (ZEROA)
ZEROL/NA
AGND
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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Terminal Functions
TERMINAL NAME PCM1753/PCM1755 AGND DATA DGND LRCK VCOM VOUTL VOUTR ZEROR/ZEROA ZEROL/NA PCM1754 AGND DATA DEMP DGND LRCK MUTE TEST VCOM VOUTL VOUTR ZEROA
DESCRIPTION
Analog ground Audio data clock input Audio data digital input Digital ground L-channel R-channel audio data latch enable input Mode control clock input(1) Mode control data input Mode control latch input System clock input Analog power supply, Common voltage decoupling Analog output L-channel Analog output R-channel Zero flag output R-channel/Zero flag output L-/R-channels Zero flag output L-channel/Not assigned Analog ground Audio-data bit-clock input Audio-data digital input De-emphasis control Digital ground Data format select L-channel R-channel audio data latch enable input Analog mixing control System clock input Test pin. Ground open Analog power supply, Common voltage decoupling Analog output L-channel Analog output R-channel Zero flag output channels
Schmitt-trigger input with internal pulldown. Open-drain output (PCM1755).
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
TYPICAL PERFORMANCE CURVES DIGITAL FILTER (DE-EMPHASIS OFF)
AMPLITUDE FREQUENCY
Amplitude Amplitude -100 -120 -140 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 Frequency -0.05
AMPLITUDE FREQUENCY
Frequency
Figure Frequency Response, Sharp Rolloff
AMPLITUDE FREQUENCY
Amplitude Amplitude -100 -120 -140
Figure Pass-Band Ripple, Sharp Rolloff
AMPLITUDE FREQUENCY
Frequency
Frequency
Figure Frequency Response, Slow Rolloff
Figure Transition Characteristics, Slow Rolloff
specifications 25_C, 44.1 kHz, system clock 24-bit data, unless otherwise noted
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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DE-EMPHASIS CURVES
DE-EMPHASIS LEVEL FREQUENCY
De-emphasis Level De-emphasis Error -0.1 -0.2 -0.3 -0.4 -0.5
DE-EMPHASIS ERROR FREQUENCY
Frequency
Frequency
Figure
Figure
DE-EMPHASIS LEVEL FREQUENCY
De-emphasis Level De-emphasis Error 44.1 -0.1 -0.2 -0.3 -0.4 -0.5
DE-EMPHASIS ERROR FREQUENCY
44.1
Frequency
Frequency
Figure
Figure
specifications 25_C, 44.1 kHz, system clock 24-bit data, unless otherwise noted
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
DE-EMPHASIS CURVES (CONTINUED)
DE-EMPHASIS LEVEL FREQUENCY
De-emphasis Level De-emphasis Error -0.1 -0.2 -0.3 -0.4 -0.5
DE-EMPHASIS ERROR FREQUENCY
Frequency
Frequency
Figure
Figure
specifications 25_C, 44.1 kHz, system clock 24-bit data, unless otherwise noted
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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ANALOG DYNAMIC PERFORMANCE (SUPPLY VOLTAGE CHARACTERISTICS)
TOTAL HARMONIC DISTORTION NOISE SUPPLY VOLTAGE
THD+N Total Harmonic Distortion Noise kHz, 44.1 kHz, kHz, kHz, Dynamic Range
DYNAMIC RANGE SUPPLY VOLTAGE
44.1 kHz,
kHz,
kHz, 0.01
kHz,
0.001 44.1 kHz,
0.0001
Supply Voltage
Supply Voltage
Figure
Figure
SIGNAL-to-NOISE RATIO SUPPLY VOLTAGE
Signal-to-Noise Ratio 44.1 kHz, Channel Separation kHz, kHz,
CHANNEL SEPARATION SUPPLY VOLTAGE
44.1 kHz,
kHz, kHz,
Supply Voltage
Supply Voltage
Figure
Figure
specifications 25_C, 44.1 kHz, system clock 24-bit data, unless otherwise noted
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
ANALOG DYNAMIC PERFORMANCE (TEMPERATURE CHARACTERISTICS)
TOTAL HARMONIC DISTORTION NOISE FREE-AIR TEMPERATURE
THD+N Total Harmonic Distortion Noise kHz, kHz, 44.1 kHz, kHz, 0.01 kHz, 44.1 kHz, Dynamic Range kHz,
DYNAMIC RANGE FREE-AIR TEMPERATURE
kHz,
0.001
44.1 kHz,
0.0001
Free-Air Temperature
Free-Air Temperature
Figure
Figure
SIGNAL-to-NOISE RATIO FREE-AIR TEMPERATURE
Signal-to-Noise Ratio 44.1 kHz, Channel Separation kHz,
CHANNEL SEPARATION FREE-AIR TEMPERATURE
kHz,
44.1 kHz,
kHz,
kHz,
Free-Air Temperature
Free-Air Temperature
Figure
Figure
specifications 25_C, 44.1 kHz, system clock 24-bit data, unless otherwise noted -25°C 85°C PCM1753/55, -40°C 85°C PCM1754
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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SYSTEM CLOCK RESET FUNCTIONS
System Clock Input PCM1753/54/55 requires system clock operating digital interpolation filters multilevel delta-sigma modulators. system clock applied input (pin 16). Table shows examples system clock frequencies common audio sampling rates. Figure shows timing requirements system clock input. optimal performance, important clock source with phase-jitter noise. TI's PLL170x family multiclock generators excellent choice providing PCM1753/54/55 system clock. Table System Clock Rates Common Audio Sampling Frequencies
SAMPLING FREQUENCY 44.1 88.2
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) 1.5360 3.0720 6.1440 8.4672 9.2160 16.9344 18.4320 36.8640 2.0480 4.0960 8.1920 11.2896 12.2880 22.5792 24.5760 49.1520 3.0720 6.1440 12.2880 16.9344 18.4320 33.8688 36.8640 4.0960 8.1920 16.3840 22.5792 24.5760 45.1584 49.1520 6.1440 12.2880 24.5760 33.8688 36.8640 1152 9.2160 18.4320 36.8640 1.0240 2.0480 4.0960 5.6448 6.1440 11.2896 12.2880 24.5760
This system clock rate supported given sampling frequency. t(SCKH) System Clock (SCK) t(SCKL) PARAMETERS t(SCY) SYMBOL t(SCKH) t(SCKL) t(SCY)
UNITS
System clock pulse duration, high System clock pulse duration, System clock pulse cycle time
1/128 1/256 1/384 1/512 1/768 1/1152
Figure System Clock Input Timing
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
Power-On Reset Functions PCM1753/54/55 includes power-on reset function. Figure shows operation this function. With system clock active (typical, power-on reset function enabled. initialization sequence requires 1024 system clocks from time (typical, After initialization period, PCM1753/55 reset default state, described Mode Control Registers section this data sheet. During reset period (1024 system clocks), analog output forced bipolar zero level, VCC/2. After reset period, internal register initialized next 1/fS period SCK, BCK, LRCK provided continuously, PCM1753/54/55 provides proper analog output with unit group delay against input data.
(Max) (Typ) (Min)
Reset Internal Reset
Reset Removal
Don't Care System Clock
1024 System Clocks
Figure Power-On Reset Timing
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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AUDIO SERIAL INTERFACE
audio serial interface PCM1753/54/55 consists 3-wire synchronous serial port. includes LRCK (pin (pin DATA (pin serial audio clock, used clock serial data present DATA into serial shift register audio interface. Serial data clocked into PCM1753/54/55 rising edge BCK. LRCK serial audio left/right word clock. used latch serial data into internal registers serial audio interface. Both LRCK should synchronous system clock. Ideally, recommended that LRCK derived from system clock input, SCK. LRCK operated sampling frequency, operated times sampling frequency standard left-justified formats. operated times sampling frequency format. Internal operation PCM1753/54/55 synchronized with LRCK. Accordingly, internal operation held when sampling rate clock LRCK changed when and/or interrupted 3-bit clock cycle longer. SCK, BCK, LRCK provided continuously after this held condition, internal operation re-synchronized automatically period less than 3/fS. External resetting required. Audio Data Formats Timing PCM1753/55 supports industry-standard audio data formats, including standard, I2S, left-justified. PCM1754 supports 16-bit-word right-justified. data formats shown Figure Data formats selected using format bits, FMT[2:0], located control register PCM1753/55, selected using PCM1754. default data format 24-bit left-justified. formats require binary 2s-complement, MSB-first audio data. Figure shows detailed timing diagram serial audio interface.
LRCK t(BCH) t(BCY) DATA t(DS) PARAMETERS pulse cycle time high-level time low-level time rising edge LRCK edge LRCK falling edge rising edge DATA setup time DATA hold time
t(BCL) t(LB) t(BL) t(DH) SYMBOL t(BCY) t(BCH) t(BCL) t(BL) t(LB) t(DS) t(DH) 1/(32 fS), 1/(48 fS), 1/(64 UNITS
sampling frequency (e.g., 44.1 kHZ, kHz, kHz, etc.).
Figure Audio Interface Timing
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
Standard Data Format; L-Channel HIGH, R-Channel
1/fS LRCK L-Channel R-Channel
16-Bit Right-Justified, DATA
16-Bit Right-Justified, DATA
18-Bit Right-Justified, DATA
20-Bit Right-Justified, DATA
24-Bit Right-Justified, DATA
Data Format; L-Channel LOW, R-Channel HIGH
1/fS LRCK L-Channel R-Channel
DATA
Left-Justified Data Format; L-Channel HIGH, R-Channel
1/fS LRCK L-Channel R-Channel
DATA
Figure Audio Data Input Formats
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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ZERO FLAGS (PCM1753/55)
Zero-Detect Condition Zero detection either output channel independent from other channel. data given channel remains level 1024 sample periods LRCK clock periods), zero-detect condition exists that channel. Zero Flag Outputs zero-detect condition exists more channels, zero flag pins those channels logic state. There zero flag pins each channel, ZEROL (pin ZEROR (pin 11). These pins used operate external mute circuits, used status indicators microcontroller, audio signal processor, other digitally controlled function. active polarity zero flag outputs inverted setting ZREV control register reset default active-high output, ZREV L-channel R-channel common zero flag selected setting AZRO control register reset default independent zero flags L-channel R-channel, AZRO case PCM1755, ZEROL ZEROR open-drain outputs.
ZERO FLAG (PCM1754)
PCM1754 ZERO flag pin, ZEROA (pin 11). ZEROA L-channel R-channel common zero flag pin. data L-channel R-channel remains level 1024 sampling periods LRCK clock periods), ZEROA logic state.
HARDWARE CONTROL (PCM1754)
digital functions PCM1754 capable hardware control. Table shows selectable formats, Table shows de-emphasis control, Table shows mute control. Table Data Format Select
(PIN HIGH 24-bit, format 16-bit right-justified DATA FORMAT
Table De-Emphasis Control
DEMP (PIN HIGH DE-EMPHASIS FUNCTION 44.1 de-emphasis 44.1 de-emphasis
Table Mute Control
MUTE (PIN HIGH Mute Mute MUTE
OVERSAMPLING RATE CONTROL (PCM1754)
PCM1754 automatically controls oversampling rate delta-sigma converters with system clock rate. oversampling rate oversampling with every system clock sampling frequency.
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SOFTWARE CONTROL (PCM1753/55)
PCM1753/55 many programmable functions which controlled software control mode. functions controlled programming internal registers using serial control interface 3-wire serial port, which operates asynchronously audio serial interface. serial control interface used program on-chip mode registers. control interface includes (pin 13), (pin 14), (pin 15). serial data input, used program mode registers. serial clock, used shift data into control port. control port latch clock. Register Write Operation write operations serial control port 16-bit data words. Figure shows control data word format. most significant must There seven bits, labeled IDX[6:0], that register index address) write operation. least significant eight bits, D[7:0], contain data written register specified IDX[6:0]. Figure shows functional timing diagram writing serial control port. held logic state until register needs written. start register write cycle, logic Sixteen clocks then provided corresponding bits control data word After sixteenth clock cycle completed, logic latch data into indexed mode control register.
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index Address)
Register Data
Figure Control Data Word Format
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6
Figure Register Write Operation
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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Control Interface Timing Requirements Figure shows detailed timing diagram serial control interface. These timing parameters critical proper control port operation.
t(MHH) t(MLS) t(MCH) t(MCY) t(MDS) PARAMETERS pulse cycle time low-level time high-level time high-level time falling edge rising edge hold time hold time setup time
t(MCL) t(MLH)
t(MDH) SYMBOL t(MCY) t(MCL) t(MCH) t(MHH) t(MLS) t(MLH) t(MDH) t(MDS)
UNITS
rising edge rising edge. (min); sampling rate
Figure Control Interface Timing
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
MODE CONTROL REGISTERS (PCM1753/55)
User-Programmable Mode Controls PCM1753/55 includes number user programmable functions, which accessed control registers. registers programmed using serial control interface, which previously discussed this data sheet. Table lists available mode control functions, along with their reset default conditions associated register index. Register mode control register shown Table Each register includes index address) indicated IDX[6:0] bits. Table User-Programmable Mode Controls
FUNCTION Digital attenuation control, 0.5-dB steps Soft mute control Oversampling rate control Soft reset control operation control De-emphasis function control De-emphasis sample rate selection Audio data format control Digital filter rolloff control Zero flag function select Output phase select Zero flag polarity select RESET DEFAULT attenuation Mute disabled oversampling Reset disabled DAC1 DAC2 enabled De-emphasis disabled 44.1 24-bit left-justified Sharp rolloff R-channel independent Normal phase High REGISTER BIT(s) AT1[7:0], AT2[7:0] MUT[2:0] OVER SRST DAC[2:1] DM12 DMF[1:0] FMT[2:0] AZRO DREV ZREV
Table Mode Control Register
(B8-B14) REGISTER Register Register Register Register Register Register IDX6 IDX6 IDX6 IDX6 IDX6 IDX6 IDX5 IDX5 IDX5 IDX5 IDX5 IDX5 IDX4 IDX4 IDX4 IDX4 IDX4 IDX4 IDX3 IDX3 IDX3 IDX3 IDX3 IDX3 IDX2 IDX2 IDX2 IDX2 IDX2 IDX2 IDX1 IDX1 IDX1 IDX1 IDX1 IDX1 IDX0 IDX0 IDX0 IDX0 IDX0 IDX0 AT17 AT27 SRST AT16 AT26 OVER DMF1 AT15 AT25 DMF0 AT14 AT24 DM12 AT13 AT23 AT12 AT22 FMT2 AZRO AT11 AT21 MUT2 DAC2 FMT1 ZREV AT10 AT20 MUT1 DAC1 FMT0 DREV
NOTE: RSV: Reserved test operation. should regular operation.
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Register Definitions
Register Register IDX6 IDX6 IDX5 IDX5 IDX4 IDX4 IDX3 IDX3 IDX2 IDX2 IDX1 IDX1 IDX0 IDX0 AT17 AT27 AT16 AT26 AT15 AT25 AT14 AT24 AT13 AT23 AT12 AT22 AT11 AT21 AT10 AT20
ATx[7:0]: Digital Attenuation Level Setting Where corresponding output VOUTL VOUTR Default value: 1111 1111b Each channel (VOUTL VOUTR) includes digital attenuation function. attenuation level from 0.5-dB steps. Changes attenuator levels made incrementing decrementing step (0.5 every 8/fS time internal until programmed attenuator setting reached. Alternatively, attenuation level infinite attenuation mute). attenuation data each channel individually. attenuation level using following formula: Attenuation level (dB) (ATx[7:0] 255) where ATx[7:0] through 255. ATx[7:0] through 128, attenuation infinite attenuation. following table shows attenuation levels various settings:
ATx[7:0] 1111 1111b 1111 1110b 1111 1101b 1000 0011b 1000 0010b 1000 0001b 1000 0000b 0000 0000B
Register
DECIMAL VALUE
IDX5
ATTENUATION LEVEL SETTING Attenuation. (default) -0.5 -1.0 -62.0 -62.5 -63.0 Mute Mute
IDX6
IDX4
IDX3
IDX2
IDX1
IDX0
SRST
OVER
MUT2
MUT1
MUTx: Soft Mute Control where corresponding outputs VOUT VOUTR Default value: MUTx MUTx Mute disabled (default) Mute enabled
mute bits, MUT1 MUT2, used enable disable soft mute function corresponding outputs, VOUTL VOUTR. soft mute function incorporated into digital attenuators. When mute disabled (MUTx attenuator operate normally. When mute enabled setting MUTx digital attenuator corresponding output decreased from current setting infinite attenuation, attenuator step (0.5 every 8/fS seconds. This provides pop-free muting output.
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PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
setting MUTx attenuator increased step every 8/fS seconds previously programmed attenuation level. OVER: Oversampling Rate Control Default value: System clock rate 1152 OVER OVER oversampling (default) oversampling
System clock rate OVER OVER oversampling (default) oversampling
OVER used control oversampling rate delta-sigma converters. OVER setting recommended when sampling rate (system clock rate fS). SRST: Reset Default value: SRST SRST Reset disabled (default) Reset enabled
SRST used enable disable soft reset function. operation same power-on reset. registers initialized.
Register
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
DMF1
DMF0
DM12
DAC2
DAC1
DACx: Operation Control Where corresponding output VOUTL VOUTR Default value: DACx DACx operation enabled (default) operation disabled
operation controls used enable disable outputs, VOUTL VOUTR. When DACx corresponding output generates audio waveform dictated data present DATA pin. When DACx corresponding output bipolar zero level, VCC. DM12: Digital De-Emphasis Function Control Default value: DM12 DM12 De-emphasis disabled (default) De-emphasis enabled
DM12 used enable disable digital de-emphasis function. plots shown Typical Performance Curves section this data sheet.
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DMF[1:0]: Sampling Frequency Selection De-Emphasis Function Default value: DMF[1:0] bits used select sampling frequency used digital de-emphasis function when enabled. DMF[1:0]
Register IDX6
De-Emphasis Sample Rate Selection 44.1 (default) Reserved
IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 FMT2 FMT1 FMT0
FMT[2:0]: Audio Interface Data Format Default value: FMT[2:0] bits used select data format serial audio interface. following table shows available format options. FMT[2:0] Audio Data Format Selection 24-bit standard format, right-justified data 20-bit standard format, right-justified data 18-bit standard format, right-justified data 16-bit standard format, right-justified data 24-bit format 24-bit left-justified format (default) Reserved Reserved
FLT: Digital Filter Rolloff Control Default value: Sharp rolloff (default) Slow rolloff
allows user select digital filter rolloff that best suited application. filter rolloff selections available, sharp slow. filter responses these selections shown Typical Performance Curves section this data sheet.
Register IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AZRO ZREV DREV
DREV: Output Phase Select Default value: DREV DREV Normal output (default) Inverted output
DREV output analog signal phase control.
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SLES092A OCTOBER 2003 REVISED AUGUST 2004
ZREV: Zero Flag Polarity Select Default value: ZREV ZREV High zero flag pins indicates zero detect (default) zero flag pins indicates zero detect
ZREV allows user select polarity zero flag pins. AZRO: Zero Flag Function Select Default value: AZRO AZRO AZRO AZRO L-/R-channel independent zero flags (default) L-/R-channel common zero flag
AZRO allows user select function zero flag pins. ZEROR, zero flag output R-channel ZEROL, zero flag output L-channel ZEROA, zero flag output L-/R-channels assigned
ANALOG OUTPUTS
PCM1753/54/55 includes independent output channels, VOUTL VOUTR. These unbalanced outputs, each capable driving typical into ac-coupled load. internal output amplifiers VOUTL VOUTR biased common-mode bipolar zero) voltage, equal VCC. output amplifiers include continuous-time filter, which helps reduce out-of-band noise energy present outputs noise shaping characteristics PCM1753/54/55 delta-sigma converters. frequency response this filter shown Figure itself, this filter enough attenuate out-of-band noise acceptable level many applications. external low-pass filter required provide sufficient out-of-band noise rejection. Further discussion post-filter circuits provided Applications Information section this data sheet.
LEVEL FREQUENCY
Level
Frequency
Figure Output Filter Frequency Response
PCM1753 PCM1754 PCM1755
SLES092A OCTOBER 2003 REVISED AUGUST 2004
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VCOM Output unbuffered common-mode voltage output pin, VCOM (pin brought decoupling purposes. This nominally biased voltage level equal VCC. This used bias external circuits. Figure shows example using VCOM external biasing applications.
where PCM1753/54/55 Filtered Output
VOUTX
OPA2353
VCOM
Using VCOM Bias Single-Supply Filter Stage
PCM1753/54/55
OPA337
Buffered VCOM
VCOM
Using Voltage Follower Buffer VCOM When Biasing Multiple Nodes
Figure Biasing External Circuits Using VCOM
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APPLICATION INFORMATION CONNECTION DIAGRAMS
basic connection diagram shown Figure with necessary power supply bypassing decoupling components. recommends using component values shown Figure designs. series resistors recommended SCK, LRCK, BCK, DATA inputs. series resistor combines with stray device input capacitance form low-pass filter, which reduces high-frequency noise emissions helps dampen glitches ringing present clock data lines.
Audio Data DATA LRCK DGND VOUTL VOUTR PCM1753 PCM1755 ZEROL/NA ZEROR/ZEROA VCOM AGND Post R-Ch System Clock Format MUTE On/Off DEMP On/Off Zero Mute Control Post R-Ch Zero Mute Control Register Control System Clock
Post
L-Ch
Audio Data
DATA LRCK DGND VOUTL VOUTR
PCM1754
MUTE DEMP TEST ZEROA VCOM AGND
Post
L-Ch
Figure Basic Connection Diagram
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POWER SUPPLIES GROUNDING
PCM1753/54/55 requires VCC. Proper power supply bypassing shown Figure 10-µF capacitors should tantalum aluminum electrolytic.
OUTPUT FILTER CIRCUITS
Delta-sigma converters noise-shaping techniques improve in-band signal-to-noise ratio (SNR) performance expense generating increased out-of-band noise above Nyquist frequency, fS/2. out-of-band noise must low-pass filtered order provide optimal converter performance. This accomplished combination on-chip external low-pass filtering. Figure 27(a) Figure show recommended external low-pass active filter circuits single- dual-supply applications. These circuits 2nd-order Butterworth filters using multiple feedback (MFB) circuit arrangement, which reduces sensitivity passive component variations over frequency temperature. more information regarding active filter design, Burr-Brown applications bulletin (SBAA055), available from site http://www.ti.com. Because overall system performance defined quality converters their associated analog output circuitry, high-quality audio operational amplifiers recommended active filters. TI's OPA2353 OPA2134 dual operational amplifiers shown Figure 27(a) Figure recommended with PCM1753/54/55.
OPA2134
VOUT
Figure Dual-Supply Filter Circuit
LAYOUT GUIDELINES
typical floor plan PCM1753/54/55 shown Figure ground plane recommended, with analog digital sections being isolated from another using split circuit board. PCM1753/54/55 should oriented with digital pins facing ground plane split/cut allow short, direct connections digital audio interface control signals originating from digital section board.
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Digital Power DGND
Analog Power AGND +5VA
Digital Logic Audio Processor
DGND PCM1753/54/55 AGND
Output Circuits Digital Ground
Digital Section
Analog Section
Analog Ground
Return Path Digital Signals
Figure Recommended Layout Separate power supplies recommended digital analog sections board. This prevents switching noise present digital supply from contaminating analog power supply degrading dynamic performance PCM1753/54/55. cases where common supply must used analog digital sections, inductance choke, ferrite bead) should placed between analog digital supply connections avoid coupling digital switching noise into analog circuitry. Figure shows recommended approach single-supply applications.
Choke Ferrite Bead Power Supplies AGND
DGND PCM1753/54/55 AGND
Output Circuits
Digital Section
Analog Section
Common Ground
Figure Single-Supply Layout
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THEORY OPERATION
delta-sigma section PCM1753/54/55 based 8-level amplitude quantizer 4th-order noise shaper. This section converts oversampled input data 8-level delta-sigma format. block diagram 8-level delta-sigma modulator shown Figure This 8-level delta-sigma modulator advantage stability clock jitter sensitivity over typical one-bit (2-level) delta-sigma modulator. combined oversampling rate delta-sigma modulator interpolation filter theoretical quantization noise performance 8-level delta-sigma modulator shown Figure Figure enhanced multilevel delta-sigma architecture also advantages input clock jitter sensitivity multilevel quantizer, with simulated jitter sensitivity shown Figure
PERFORMANCE PARAMETERS MEASUREMENT
This section provides information measure dynamic performance parameters PCM1753/54/55. cases, Audio Precision System Cascade audio measurement system equivalent used perform testing. Total Harmonic Distortion Noise Total harmonic distortion noise (THD+N) significant figure merit audio converters because takes into account both harmonic distortion noise sources within specified measurement bandwidth. average value distortion noise referred THD+N. PCM1753/54/55, THD+N measured with full-scale, 1-kHz digital sine wave test stimulus input DAC. digital generator 24-bit audio word length sampling frequency 44.1 kHz. digital generator output taken from unbalanced S/PDIF connector measurement system. S/PDIF data transmitted coaxial cable digital audio receiver DEM-DAI1753 demonstration board. receiver then configured output 24-bit data either left-justified data format. audio interface format programmed match receiver output format. analog output then taken from post filter connected analog analyzer input measurement system. analog input band limited using filters resident analyzer. resulting THD+N measured analyzer displayed measurement system.
8-Level Quantizer
Figure Eight-Level Delta-Sigma Modulator
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AMPLITUDE FREQUENCY
-100 -120 -140 -160 -180 -100 -120 -140 -160 -180
AMPLITUDE FREQUENCY
Amplitude
Amplitude
Frequency
Frequency
Figure Quantization Noise Spectrum Oversampling)
Figure Quantization Noise Spectrum Oversampling)
DYNAMIC RANGE JITTER
Dynamic Range
Jitter
Figure Jitter Dependence Oversampling)
PCM1753 PCM1754 PCM1755
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Dynamic Range Dynamic range specified A-weighted THD+N measured with -60-dB full-scale, 1-kHz digital sine wave stimulus input converter. This measurement designed give good indicator performs given low-level input signal. measurement setup dynamic range measurement shown Figure similar THD+N test setup discussed previously. differences include band limit filter selection, additional A-weighting filter, -60-dB full-scale input level.
Evaluation Board DEM-DAI1753 S/PDIF Receiver 2nd-Order Low-Pass Filter
PCM1753/54/55
Audio Precision System Digital Generator (100% Full-Scale), 24-Bit, 1-kHz Sine Wave Analyzer Display Averaging Mode
AES17 Filter Band Limit 20.9
S/PDIF Output
Figure Test Setup THD+N Measurement Idle Channel Signal-to-Noise Ratio test provides measure noise floor converter. input all-0s data, dither function digital generator must disabled ensure all-0s data stream input converter. measurement setup identical that used dynamic range, with exception input signal level. (See note provided Figure 37).
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Evaluation Board DEM-DAI1753 S/PDIF Receiver 2nd-Order Low-Pass Filter
PCM1753/54/55
Audio Precision System Digital Generator Full-Scale, Dither (SNR) Sine Wave (Dynamic Range)
S/PDIF Output
Analyzer Display Averaging Mode
A-Weighting Filter
Band Limit
AES17 Filter 20.9
Results without A-Weighting approximately worse.
Figure Test Setup Dynamic Range Measurement
MECHANICAL DATA
MSOI004E JANUARY 1995 REVISED 2002
(R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64)
0.012 (0,30) 0.008 (0,20)
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20)
Gauge Plane 0°-8° 0.069 (1,75) 0.035 (0,89) 0.016 (0,40) 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,74) 0.337 (8,56)
0.344 (8,74) 0.337 (8,56)
0.394 (10,01) 0.386 (9,80)
M0-137 VARIATION
4073301/F 02/2002 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Falls within JEDEC MO-137.
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