SBAZ003 SEPTEMBER 2003 Errata MSC1210, Datasheet Literature Numbe

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SBAZ003 SEPTEMBER 2003 Errata MSC1210, Datasheet Literature Numbe

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MSC1210 Errata
SBAZ003 SEPTEMBER 2003
Errata MSC1210, Datasheet Literature Number SBAS203A
MSC1210 device conforms functionally product data sheet (SBAS203A), except anomalies described below.
Errata Index
Internal SRAM corruption occur SPIFIFO mode. Flash memory write operation fails when additional MOVX command issued before operation complete (only when system executing from external program memory).
Erratum Brief Description Issue
FIFO mode improper operation internal SRAM corruption.
Detailed Description Issue
data transfers occur circular fashion (that byte residing master buffer transfers slave buffer, vice versa). Therefore, data write read both occurring each device during transfer. When using FIFO mode, address and/or data during data transfer corrupted controller. data corrupted during transfer, then incorrect data written into internal SRAM. address corrupted during transfer, then data will written incorrect address SRAM (the internal SRAM address range 00h-FFh). either case, data internal SRAM will corrupted.
Impact Customer
FIFO mode recommended; instead, should only used double-buffer mode.
Workaround
None.
Affected Devices
MSC1210Y2, MSC1210Y3, MSC1210Y4, MSC1210Y5.
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MSC1210 Errata
SBAZ003 SEPTEMBER 2003
Erratum Brief Description Issue
Using MOVX command (from non-boot program memory) after MSC1210 initiated internal flash write cause flash memory become corrupted.
Detailed Description Issue
When flash write initiated MOVX @DPTR, command, value accumulator placed onto data input lines flash memory. another MOVX @DPTR, command issued while write operation still progress, data input lines updated with accumulator value. Thus, area flash memory that being written corrupted second memory write. Note: address second MOVX effect flash write destination.
Impact Customer
behavior only observed when MSC1210 executing code from non-boot program memory. effect customer system executing from flash memory boot memory. user ensure flash write completed before executing next write command polling FLSBSY register FMCON. Since length flash write operation 60µs, this latency must accounted user application.
Workaround
While flash memory being written, ensure that FLSBSY register FMCON before initiating next MOVX @DPTR, command.
Affected Devices
MSC1210Y2, MSC1210Y3, MSC1210Y4, MSC1210Y5.
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SBAZ003 SEPTEMBER 2003 Errata MSC1210, Datasheet Literature Numbe

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