Precision, Analog-to-Digital Converter (ADC) Digital-to-Analog Convert

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Precision, Analog-to-Digital Converter (ADC) Digital-to-Analog Convert

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MSC1201 MSC1202
Precision, Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) with 8051 Microcontroller Flash Memory
ANALOG Peripheral Features Digital Pins Additional 32-Bit Accumulator 16-Bit Timer/Counters System Timers Programmable Watchdog Timer Full-Duplex USART Basic Basic Power Management Control Internal Clock Divider Idle Mode Current 200mA Stop Mode Current 100nA Digital Brownout Reset Analog Low-Voltage Detect Interrupt Sources
MSC1201:
Bits Missing Codes Bits Effective Resolution 10Hz Noise: 75nV MSC1202: Bits Missing Codes Bits Effective Resolution 200Hz Noise: 600nV From Precision On-Chip Voltage Reference Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.02ppm/°C Gain Drift: 0.5ppm/°C On-Chip Temperature Sensor Selectable Buffer Input Burnout Detect 8-Bit Current
GENERAL
DIGITAL Microcontroller Core 8051-Compatible High-Speed Core: Clocks Instruction Cycle 33MHz On-Chip Oscillator with 32kHz Capability Single Instruction 121ns Dual Data Pointer Memory Flash Memory Flash Memory Partitioning Endurance Erase/Write Cycles, 100-Year Data Retention Bytes Data SRAM In-System Serially Programmable Flash Memory Security Boot
Each Device Unique Serial Number Package: QFN-36 Power: 3.0V, 1MHz Industrial Temperature Range: -40°C +125°C Power Supply: 2.7V 5.25V
APPLICATIONS
Industrial Process Control Instrumentation Liquid/Gas Chromatography Blood Analysis Smart Transmitters Portable Instruments Weigh Scales Pressure Transducers Intelligent Sensors Portable Applications Systems
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademark Motorola. trademark Philips Corporation. other trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2004-2005, Texas Instruments Incorporated
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MSC1201 MSC1202
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PACKAGE/ORDERING INFORMATION(1)
PRODUCT MSC1201Y2 MSC1201Y3 MSC1202Y2 MSC1202Y3 FLASH MEMORY (BYTES) RESOUTION (BITS) PACKAGE-LEAD QFN-36 QFN-36 QFN-36 QFN-36 PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE -40°C +125°C -40°C +125°C -40°C +125°C -40°C +125°C PACKAGE MARKING MSC1201Y2 MSC1201Y3 MSC1202Y2 MSC1202Y3
most current package ordering information, Package Option Addendum located this datasheet, refer site www.ti.com.
MSC1201Yx/MSC1202Yx FAMILY FEATURES(1) Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad (Bytes) MSC120xY2(2) MSC120xY3(2)
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
peripheral features same devices; flash memory size only difference. last digit part number represents onboard flash size N)kBytes.
ABSOLUTE MAXIMUM RATINGS(1)
MSC1201Yx, MSC1202Yx Analog Inputs Momentary Input current Input voltage Power Supply DVDD DGND AVDD AGND AGND DGND VREF AGND Digital input voltage DGND Digital output voltage DGND Maximum junction temperature Operating temperature range Storage temperature range Lead temperature (soldering, 10s) Package power dissipation Output current, pins Output short-circuit High Thermal Resistance Digital Outputs Output current source/sink current Power maximum Continuous Junction ambient (qJA) Junction case (qJC) (1s) -0.3 -0.3 -0.3 +0.3 -0.3 AVDD -0.3 DVDD -0.3 DVDD +150 +125 +150 +235 TAMBIENT)/qJA 21.9 103.7 21.9 °C/W °C/W °C/W Continuous AGND AVDD UNITS
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. Exposure absolute maximum conditions extended periods affect device reliability.
MSC1201 MSC1202
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, DVDD +2.7V +5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER Analog Input (AIN0-AIN5, AINCOM) Buffer Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Fast Settling Filter Bandwidth Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Offset Offset Range Offset Resolution Offset Full-Scale Gain Error Offset Full-Scale Gain Error Drift System Performance MSC1201 Resolution MSC1202 MSC1201 ENOB Output Noise MSC1201, Sinc3 Filter, Decimation Missing Codes Integral Nonlinearity Offset Error Offset Drift(2) Gain Error(3) Gain Error Drift(2) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection 60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz Normal-Mode Rejection Power-Supply Rejection 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz -20log(VOUT/VDD)(4) MSC1202, Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration ±0.0004 0.02 0.005 ±0.0015 MSC1202 Typical Characteristics Bits Bits FS/°C ppm/°C Bits Bits Bits Bits ±1.0
±VREF/(2 PGA)
CONDITION
UNITS
AGND AGND 50mV
AVDD AVDD ±VREF/PGA 7/PGA(1) 0.469 fDATA 0.318 fDATA 0.262 fDATA
Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Range Buffer Multiplexer Channel OFF, +25°C Buffer
Bits Range ppm/°C
input impedance same that (that 7M/64). Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result.
MSC1201 MSC1202
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ELECTRICAL CHARACTERISTICS: AVDD (continued)
specifications from TMIN TMAX, DVDD +2.7V +5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER Voltage Reference Input Reference Input Range VREF VREF Common-Mode Rejection Input Current On-Chip Voltage Reference VREFH +25°C Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient IDAC Output Characteristics IDAC Resolution Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Current AVDD OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC PDIDAC Buffer Analog Power-Supply Current Current (IADC) 128, Buffer Buffer 128, Buffer VREF Supply Current (IVREF) IDAC Supply Current (IIDAC) IDAC 4.75 5.25 Indefinite AVDD Bits +25°C µV/°C Sink Source CREFOUT 0.1µF VREFH 1.25 Indefinite IN+, VREF (REFIN+) (REFIN-) VREF 2.5V, AGND AVDD(3) AVDD CONDITION UNITS
input impedance same that (that 7M/64). Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result.
MSC1201 MSC1202
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, DVDD +2.7V +5.25V, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise noted. fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, MSC1201Yx, MSC1202Yx PARAMETER Analog Input (AIN0-AIN5, AINCOM) Buffer Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Fast Settling Filter Bandwidth Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Offset Offset Range Offset Resolution Offset Full-Scale Gain Error Offset Full-Scale Gain Error Drift System Performance MSC1201 Resolution MSC1202 MSC1201 ENOB Output Noise MSC1201, Sinc3 Filter, Decimation Missing Codes Integral Nonlinearity Offset Error Offset Drift(2) Gain Error(3) Gain Error Drift(2) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection 60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz Normal-Mode Rejection Power-Supply Rejection fSIG 50Hz, fDATA 50Hz fSIG 60Hz, fDATA 60Hz -20log(VOUT/VDD)(4) MSC1202, Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration ±0.0004 0.02 0.005 ±0.0015 MSC1202 Typical Characteristics Bits Bits FS/°C ppm/°C Bits Bits Bits Bits ±1.5
±VREF/(2 PGA)
CONDITIONS
UNITS
AGND AGND 50mV
AVDD AVDD ±VREF/PGA 7/PGA(1) 0.469 fDATA 0.318 fDATA 0.262 fDATA
Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Range Buffer Multiplexer Channel Off, +25°C Buffer
Bits Range ppm/°C
input impedance same that (that 7M/64). Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result.
MSC1201 MSC1202
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ELECTRICAL CHARACTERISTICS: AVDD (continued)
specifications from TMIN TMAX, DVDD +2.7V +5.25V, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise noted. fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, MSC1201Yx, MSC1202Yx PARAMETER Voltage Reference Input Reference Input Range VREF VREF Common-Mode Rejection Input Current On-Chip Voltage Reference Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient IDAC Output Characteristics IDAC Resolution Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Current AVDD OFF, External Clock Mode, Analog OFF, ALVD OFF, PDADC PDIDAC Buffer Analog Power-Supply Current Current (IADC) 128, Buffer Buffer 128, Buffer VREF Supply Current (IVREF) IDAC Supply Current (IIDAC) IDAC Indefinite AVDD Bits +25°C µV/°C Sink Source CREFOUT VREFH +25°C 1.25 Indefinite IN+, VREF (REFIN+) (REFIN-) VREF 1.25V, AGND 1.25 AVDD(3) AVDD CONDITIONS UNITS
input impedance same that (that 7M/64). Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result.
MSC1201 MSC1202
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DIGITAL CHARACTERISTICS: DVDD 2.7V 5.25V
specifications from TMIN TMAX, unless otherwise specified. MSC1201Yx, MSC1202Yx PARAMETER Digital Power-Supply Requirements DVDD Normal Mode, fOSC 1MHz Digital Power-Supply Current Normal Mode, fOSC 8MHz, Peripherals Internal Oscillator Mode (12.8MHz nominal) Stop Mode, External Clock DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz, Peripherals Digital Power-Supply Current Internal Oscillator Mode (12.8MHz nominal) Internal Oscillator Mode (25.6MHz nominal) Stop Mode, External Clock Digital Input/Output (CMOS) Logic Level (except pin) (except pin) DVDD DVDD DGND 30mA, (20mA) 30mA, (20mA) DVDD DGND DVDD DVDD DVDD DVDD DVDD 4.75 5.25 CONDITIONS UNITS
Ports Input Leakage Current, Input Mode Hysteresis VOL, Ports Output Modes
VOH, Ports Strong Drive Output Ports Pull-Up Resistors
FLASH MEMORY CHARACTERISTICS: DVDD 2.7V 5.25V
tUSEC tMSEC MSC1201Yx, MSC1202Yx PARAMETER Flash Memory Endurance Flash Memory Data Retention Mass Page Erase Time Flash Memory Write Time with Value FTCON, from TMIN TMAX with Value FTCON CONDITIONS 100,000 1,000,000 UNITS cycles Years
MSC1201 MSC1202
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ELECTRICAL CHARACTERISTICS(1): DVDD 2.7V 5.25V
MSC1201Yx, MSC1202Yx PARAMETER PHASE LOCK LOOP (PLL) Input Frequency Range Mode Mode Lock Time INTERNAL OSCILLATOR (IO) Mode Mode Settling Time CONDITION External Crystal/Clock Frequency (fOSC) PLLDIV (default) PLLDIV (must user), DVDD Within Typical Characteristics DVDD Within 14.7 29.5 32.768 14.8 29.5 UNITS
Parameters valid over operating temperature range, unless otherwise specified.
EXTERNAL CLOCK DRIVE TIMING: FIGURE
SYMBOL External Clock Mode fOSC(1) 1/tOSC(1) fOSC(1) tHIGH tLOW PARAMETER External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) HIGH Time(2) Time(2) Rise Time(2) Fall Time(2) 2.7V 3.6V 4.75V 5.25V UNITS
1/fOSC oscillator clock period clock divider These values characterized 100% production tested.
tHIGH 0.8V 0.8V tLOW 0.8V tOSC
0.8V
Figure External Clock Drive SERIAL FLASH PROGRAMMING TIMING: FIGURE
SYMBOL tRRD tRFD PARAMETER width rise P1.0 internal pull high falling start Input signal falling setup time falling P1.0 hold time tOSC tOSC UNITS
P1.0/PROG NOTE: P1.0 internally pulled- with ~11k during high. tRFD,
Figure External Clock Drive
MSC1201 MSC1202
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CONFIGURATION
P3.6/SCK/SCL/CLKS
P3.0/RxD0
P3.1/TxD0
P3.3/INT1
P3.2/INT0
XOUT DGND AVDD AGND AGND AINCOM IDAC
DVDD DGND P1.6/INT4 P1.5/INT3 P1.4/INT2/SS P1.3/DIN P1.2/DOUT P1.1 P1.0/PROG
MSC1201 MSC1202
P1.7/INT5 AIN0
P3.5/T1 REFIN-
REFOUT/REFIN+
AIN5
P3.4/T0
P3.7
AIN4
AIN3
AIN2
AIN1
MSC1201 MSC1202
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ASSIGNMENTS
19-25, NAME XOUT DGND AVDD AGND AINCOM IDAC REFOUT/REF AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 P1.0-P1.7 DESCRIPTION crystal oscillator supports parallel resonant fundamental frequency crystals ceramic resonators. also input there external clock source instead crystal. must left floating. crystal oscillator XOUT supports parallel resonant fundamental frequency crystals ceramic resonators. XOUT serves output crystal amplifier. Digital Ground HIGH reset input tOSC periods will reset device. connection Analog Power Supply Analog Ground Analog Input (can analog common single-ended inputs analog input differential inputs) IDAC Output Internal Voltage Reference Output/Voltage Reference Positive Input Voltage Reference Negative Input (tie AGND internal voltage reference) Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Port bidirectional port (refer P1DDRL, AEh, P1DDRH, AFh, port configuration control). alternate functions Port listed below. Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 29-36 DVDD P3.0-P3.7 Digital Power Supply Port bidirectional port (refer P3DDRL, B3h, P3DDRH, B4h, port configuration control). alternate functions Port listed below. Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P1.7 Alternate Name(s) RxD0 TxD0 INT0 INT1 SCK/SCL/CLKS Alternate Serial port input Serial port output External interrupt External interrupt Timer external input Timer external input various clocks (refer PASEL, F2h) Alternate Name(s) PROG DOUT INT2/SS INT3 INT4 INT5 Serial data Serial data External interrupt Slave Select External interrupt External interrupt External interrupt Alternate Serial programming mode
MSC1201 MSC1202
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TYPICAL CHARACTERISTICS: MSC1201 ONLY
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA1 PGA8 PGA32 PGA64 PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DATA RATE ENOB (rms) Sinc3 Filter, Buffer Data Rate (SPS) 1000
ENOB (rms)
PGA128
PGA16
PGA32
PGA64
PGA128
Sinc3 Filter, Buffer
1000 Decimation Ratio fMOD
1500 fDATA
2000
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA2 PGA4 PGA8
ENOB (rms)
PGA1
ENOB (rms)
PGA16 PGA32 PGA64 PGA128
1000 Decimation Ratio fDATA 1500 2000 Sinc3 Filter, Buffer
PGA32 PGA16 PGA64 PGA128
1000 Decimation Ratio fDATA 1500 2000 AVDD Sinc3 Filter, VREF 1.25V, Buffer
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
ENOB (rms)
PGA1
ENOB (rms)
PGA1
1000 Decimation Ratio fMOD fDATA 1500 2000 AVDD Sinc3 Filter, VREF 1.25V, Buffer
PGA16 PGA32 PGA64 PGA128
PGA32
PGA16
PGA64
1000 Decimation Ratio 1500 fMOD fDATA
PGA128
Sinc2 Filter
2000
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TYPICAL CHARACTERISTICS: MSC1201 ONLY (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER BITS DECIMATION RATIO ENOB (Bits) 1000 Decimation Ratio 1500 fMOD fDATA 2000 Fast Settling Filter Data Rate (SPS) 100k fMOD 62.5kHz Gain ENOB (rms) fMOD 31.25kHz Gain fMOD 15.6kHz fMOD 203kHz fMOD 110kHz EFFECTIVE NUMBER BITS fMOD (set with ACLK)
EFFECTIVE NUMBER BITS fMOD (set with ACLK) WITH FIXED DECIMATION 2020 Noise (rms, Data Rate (SPS) 100k
NOISE INPUT SIGNAL
ENOB (rms)
HISTOGRAM OUTPUT DATA 4500 4000 Number Occurrences 3500 3000 2500 2000 1500 1000
MSC1201 MSC1202
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TYPICAL CHARACTERISTICS: MSC1202 ONLY
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. EFFECTIVE NUMBER BITS DATA RATE ENOB (rms) ENOB (rms) Data Rate (SPS) 1000 PGA128 Sinc3 Filter, Buffer PGA1 1000 Decimation Ratio fMOD fDATA 1500 2000 Sinc3 Filter, Buffer PGA128 PGA1 EFFECTIVE NUMBER BITS DECIMATION RATIO
EFFECTIVE NUMBER BITS DECIMATION RATIO ENOB (rms) 1000 Decimation Ratio fDATA 1500 2000 PGA128 Sinc3 Filter, Buffer ENOB (rms) PGA1 PGA1
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA128
AVDD Sinc3 Filter, VREF 1.25V, Buffer 1000 Decimation Ratio fMOD fDATA 1500 2000
EFFECTIVE NUMBER BITS DECIMATION RATIO ENOB (rms) 1000 Decimation Ratio fMOD fDATA 1500 2000 AVDD Sinc3 Filter, VREF 1.25V, Buffer PGA128 ENOB (rms) PGA1 PGA1
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA128
Sinc2 Filter
1000 Decimation Ratio
1500 fMOD fDATA
2000
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TYPICAL CHARACTERISTICS: MSC1202 ONLY (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER BITS DECIMATION RATIO ENOB (rms) 1000 Decimation Ratio 1500 fMOD fDATA 2000 Data Rate (SPS) 100k Fast Settling Filter fMOD 62.5kHz ENOB (rms) fMOD 15.6kHz fMOD 31.25kHz fMOD 110kHz fMOD 203kHz EFFECTIVE NUMBER BITS fMOD (set with ACLK)
EFFECTIVE NUMBER BITS fMOD (set with ACLK) WITH FIXED DECIMATION
ENOB (rms)
Data Rate (SPS) 100k
MSC1201 MSC1202
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TYPICAL CHARACTERISTICS: MSC1201 MSC1202
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
INTEGRAL NONLINEARITY INPUT VOLTAGE (ppm) AVDD VREF 2.5V -55_ +25_ (ppm +85_C -2.5 -2.0 -1.5 -1.0 -0.5 +125_C -VREF -40_C
INTEGRAL NONLINEARITY INPUT SIGNAL VREF AVDD Buffer
+VREF
Input Voltage
INTEGRAL NONLINEARITY VREF (ppm AVDD VREF (ppm VREF Buffer
INTEGRAL NONLINEARITY ERROR AVDD VREF 2.5V
AVDD
Setting
ANALOG SUPPLY CURRENT ANALOG SUPPLY VOLTAGE Analog Supply Current (mA) (µA) +25_ Analog Supply Voltage -40_C -55_C DVDD AVDD VREF 1.25V +125_ +85_
POWER-SUPPLY CURRENT
AVDD Buffer AVDD Buffer AVDD Buffer AVDD Buffer
Setting
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TYPICAL CHARACTERISTICS: MSC1201 MSC1202 (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
OFFSET DAC: OFFSET TEMPERATURE 1.00008 1.00006 1.00004 Normalized Gain 1.00002 0.99998 0.99996 0.99994
OFFSET DAC: GAIN TEMPERATURE
Offset (ppm FSR)
0.99992 +100 +120 +140
+100 +120 +140 Temperature (_C)
Temperature (_C)
DIGITAL SUPPLY CURRENT EXTERNAL CLOCK FREQUENCY Digital Supply Current (mA) DVDD Normal Mode DVDD Normal Mode
DIGITAL SUPPLY CURRENT CLOCK DIVIDER Divider Values Digital Supply Current (mA)
DVDD Idle Mode
1024
DVDD Idle Mode Clock Frequency (MHz)
Clock Frequency (MHz)
DIGITAL SUPPLY CURRENT DIGITAL SUPPLY VOLTAGE Digital Supply Current (mA) +85_C Digital Supply Voltage -40_C +25_C -55_C DVDD AVDD VREF 1.25V
NORMALIZED GAIN Buffer Normalized Gain
+125_
Setting
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TYPICAL CHARACTERISTICS: MSC1201 MSC1202 (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. VOLTAGE REFERENCE CURRENT SETTING Output Input Current (µA) Output Current (mA) Gain VREF 2.5V fMOD 62.5kHz VREF 1.25V 62.5kHz VREF 2.5V fMOD 15.6kHz VREF 1.25V 15.6kHz
DIGITAL OUTPUT VOLTAGE Output Voltage Output
INTERNAL OSCILLATOR LOW-FREQUENCY MODE TEMPERATURE 16.0 15.5 Frequency (MHz) 15.0 14.5 14.0 13.5 3.3V 13.0 2.7V 12.5 12.0 Temperature 5.25V 4.75V Frequency (MHz)
INTERNAL OSCILLATOR HIGH-FREQUENCY MODE TEMPERATURE
5.25V 4.75V Temperature (_C)
IDAC OUTPUT CURRENT IDAC OUTPUT VOLTAGE IDAC Output Current (mA) IDAC Output Votage IDAC AVDD AVDD IDAC Output Current (µA)
IDAC OUTPUT CURRENT TEMPERATURE
Temperature (_C)
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DESCRIPTION
MSC1201Yx/MSC1202Yx completely integrated families mixed-signal devices incorporating high-resolution, delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, programmable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, Data SRAM, shown Figure On-chip peripherals include additional 32-bit accumulator, basic SPI, basic I2C, USART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, external interrupts. devices accept low-level differential single-ended signals directly from transducer. provides bits (MSC1201) bits (MSC1202) resolution bits (MSC1201) bits (MSC1202) no-missing-code performance using Sinc3 filter with programmable sample rate. also selectable filter that allows high-resolution single-cycle conversion. microcontroller core 8051 instruction compatible. microcontroller core optimized 8051 core that executes three times faster than standard 8051 core, given same clock source. This makes possible device lower external clock frequency achieve same performance lower power than standard 8051 core. MSC1201Yx/MSC1202Yx allow user uniquely configure Flash Memory meet needs their application. Flash programmable down +2.7V using serial programming. Flash endurance typically Erase/Write cycles. parts have separate analog digital supplies, which independently powered from +2.7V +5.25V. operation, power dissipation part typically less than 3mW. MSC1201Yx/MSC1202Yx both packaged QFN-36 package. MSC1201Yx/MSC1202Yx designed high-resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation.
AVDD AVDD
AGND
REFOUT/REFIN+
DVDD
DGND
Burnout Detect
Temperature Sensor
VREF
ALVD DBOR
Timers/ Counters
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AINCOM
8-Bit Offset
Alternate Functions
Modulator FLASH Bytes SRAM
Digital Filter PORT1
DOUT PROG USART SCK/SCL/CLKS
8051 PORT3 On-Chip Oscillator
Burnout Detect
AGND IDAC 8-Bit IDAC
System Clock Divider
XOUT NOTE: must tied AGND when using internal VREF.
Figure Block Diagram
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ENHANCED 8051 CORE
instructions MSC1201/02 families perform exactly same functions they would standard 8051. effects bits, flags, registers same; however, timing different. MSC1201/02 families efficient 8051 core that results improved instruction execution speed between times faster than original core same external clock speed clock cycles instruction versus clock cycles instruction, shown Figure This translates into effective throughput improvement more than times, using same code same external clock speed. Therefore, device frequency 33MHz MSC1201Yx/MSC1202Yx actually performs equivalent execution speed 82.5MHz compared standard 8051 core. This allows user device slower clock speeds, which reduces system noise power consumption, provides greater throughput. This performance difference seen Figure timing software loops will faster with MSC1201/02. However, timer/counter operation MSC1201/02 maintained clocks increment optionally clocks increment. MSC1201Yx/MSC1202Yx also provide dual data pointers (DPTRs).
MSC1201/02 Timing
Single-Byte, Single-Cycle Instruction PSEN Internal AD0-AD7 Internal A8-A15 Cycles Cycles
Standard 8051 Timing
PSEN AD0-AD7 PORT Single-Byte, Single-Cycle Instruction
Figure Comparison MSC1201/02 Timing Standard 8051 Timing
instr_cycle
cpu_cycle
Figure Instruction Timing Cycle
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Furthermore, improvements were made peripheral features that off-load processing from core, user, further improve efficiency. instance, 32-bit accumulation done through summation register significantly reduce processing overhead multiple byte data from other sources. This allows 32-bit addition, subtraction shifting accomplished instruction cycles, compared hundreds instruction cycles through software implementation.
subtract software functions freely migrate between family members. Thus, MSC1201/02 become standard device used across several application platforms.
Family Development Tools
MSC1201Yx/MSC1202Yx fully compatible with standard 8051 instruction set. This means that user develop software MSC1201/02 with their existing 8051 development tools. Additionally, complete, integrated development environment provided with each demo board, third-party developers also provide support.
Family Device Compatibility
hardware functionality configuration across MSC1201/02 families fully compatible. user, only differences between family members memory configuration. This makes migration between family members simple. Code written MSC1201Y2 MSC1202Y2 executed directly MSC1201Y3 MSC1202Y3, respectively. This gives user ability
Power-Down Modes
MSC1201Yx/MSC1202Yx each power several peripherals into IDLE. This accomplished shutting clocks those sections, shown Figure
tSYS tCLK SPICON/ I2CCON PDCON.0 USEC FTCON Flash Write (30µs 40µs) [3:0] Timing Flash Erase (5ms 11ms) FTCON [7:4] Timing milliseconds interrupt PDCON.1 SECINT HMSEC PDCON.2 ACLK divide ADCON3 ADCON2 Decimation Ratio Output Rate 100ms WDTCON watchdog seconds interrupt SCL/SCK
MSECL MSECH
MSINT
Power Down PDCON.3
Modulator Clock Timers USART
IDLE
Clock
Figure MSC1201/02 Timing Chain Clock Control
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OVERVIEW
MSC1201/02 structure shown Figure figure lists components that make ADC, along with corresponding special function register (SFR) associated with each component.
AVDD
Burnout Detect
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AINCOM Temperature Sensor
REFIN+ SAMP
Input Multiplexer Buffer Sample Hold
Burnout Detect
REFIN- AGND ADCON0 ACLK
Offset ODAC
ADMUX
REFIN+
fMOD
DATA
FAST Modulator SINC2 SINC3 AUTO
Offset Calibration Register
Gain Calibration Register
Result Register
Summation Block
REFIN- ADCON1 ADCON2 ADCON3
ADRES DBh(1) SUMR
NOTE: MSC1202, this register sign-extended (Bipolar mode) zero-padded (Unipolar mode) 16-bit result registers D9h.
SSCON
Figure MSC1201/02 Structure
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INPUT MULTIPLEXER
input multiplexer provides combination differential inputs selected input channel, shown Figure AIN0 selected positive differential input channel, other channel selected negative differential input channel. With this method, possible have fully differential input channels. also possible switch polarity differential input pair negate offset voltages. addition, current sources supplied that will source sink current detect open short circuits pins.
BURNOUT DETECT
When Burnout Detect (BOD) control configuration register (ADCON0, DCh), current sources enabled. current source positive input channel sources approximately current. current source negative input channel sinks approximately 2µA. This allows detection open circuit (full-scale reading) short circuit (small differential reading) selected input differential pair. buffer should sensor burnout detection.
INPUT BUFFER
analog input impedance always high, regardless setting (when buffer enabled). With buffer enabled, input voltage range reduced analog power-supply current higher. limitation input voltage range acceptable, then buffer always preferred. input impedance MSC1201/02 without buffer 7M/PGA. buffer controlled state control register (ADCON0, DCh).
AIN0
AIN1 AVDD
AIN2
Burnout Detect (2µA)
ANALOG INPUT
AIN3 AIN4 Buffer
When buffer selected, input impedance analog input changes with ACLK clock frequency (ACLK, F6h) gain (PGA). relationship
Impedance
1MHz ACLK Frequency ACLK
AIN5 Burnout Detect (2µA) Temperature Sensor AVDD AVDD
where ACLK frequency ACLK) ACLK
AGND
NOTE: input impedance same that (that 7M/64). Figure shows basic input structure MSC1201/02.
RSWITCH typical)
AINCOM
Figure Input Multiplexer Configuration
Sampling Frequency fSAMP SAMP fMOD fMOD fMOD fMOD AGND
High Impedance 18pF 36pF
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When configuration register input diodes connected inputs ADC. other channels open. internal device power dissipation affects temperature sensor reading.
Figure Analog Input Structure (without Buffer)
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gains 128. Using actually improve effective resolution ADC. instance, with ±2.5V full-scale range (FSR), resolve 1.5µV. With ±19mV FSR, resolve 75nV. With ±2.5V FSR, would require 26-bit resolve 75nV, shown Table
system calibration, appropriate signal must applied inputs. then computes offset that will nullify offset system. system gain calibration requires positive full-scale differential input signal. then computes gain value nullify gain errors system. Each these calibrations will take seven tDATA periods complete. Calibration should performed after power change temperature, power supply, voltage reference, decimation ratio, buffer, change PGA. completion calibration, Interrupt goes high, which indicates calibration finished valid data available.
Table ENOB versus (Bipolar Mode)
MSC1201 ENOB 10HZ (BITS) 21.7 21.5 21.4 21.2 20.8 20.4 MSC1202 ENOB 200HZ (BITS) 15.6 15.5 15.4 15.4 15.3 15.2 14.2 MEASUREMENT RESOLUTION MSC1201 (nV) 1468 74.5 74.5 MSC1202 (mV) 76.3 38.1 19.1
SETTING
FULL-SCALE RANGE ±2.5 ±1.25 ±0.625 ±0.313 ±0.156 ±0.078 ±0.039 ±0.019
DIGITAL FILTER
Digital Filter either Fast Settling, Sinc2, Sinc3 filter, shown Figure addition, Auto mode changes Sinc filter after input channel changed. When switching channel, will Fast Settling filter next conversions, first which should discarded. will then Sinc2 followed Sinc3 filter improve noise performance. This combines low-noise advantage Sinc3 filter with quick response Fast Settling Time filter. frequency response each filter shown Figure
OFFSET
analog output from offset half full-scale input range using ODAC register (SFR E6h). ODAC (Offset DAC) register 8-bit value; sign seven LSBs provide magnitude offset. Since ODAC introduces analog (instead digital) offset PGA, using ODAC does reduce range ADC.
Adjustable Digital Filter Sinc3
Modulator
Sinc2
Data
MODULATOR
modulator single-loop 2nd-order system. modulator runs clock speed (fMOD) that derived from using value Analog Clock register (ACLK, F6h). data output rate
Fast Settling
FILTER SETTLING TIME FILTER Sinc3 Sinc2 Fast SETTLING TIME (Conversion Cycles)(1)
Data Rate DATA where
Decimation Ratio
ACLK (ACLK
With synchronized channel changes.
AUTO MODE FILTER SELECTION
CALIBRATION
offset gain errors MSC1201/02, complete system, reduced with calibration. Calibration controlled through ADCON1 register (SFR DDh), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) complete. Therefore, takes tDATA periods complete both offset gain calibration.
CONVERSION CYCLE Discard Fast Sinc2 Sinc3
Figure Filter Step Responses
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SINC3 FILTER RESPONSE (-3dB 0.262 fDATA) Gain (dB) -100 -120 fDATA SINC2 FILTER RESPONSE (-3dB 0.318 fDATA) Gain (dB) -100 -120 fDATA FAST SETTLING FILTER RESPONSE (-3dB 0.469 fDATA) Gain (dB) -100 -120 fDATA NOTE: fDATA Data Output Rate 1/tDATA
internal voltage reference selected either 1.25V 2.5V. analog power supply (AVDD) must within specified range selected internal voltage reference. valid ranges are: VREF internal (AVDD 3.3V 5.25V) VREF 1.25 internal (AVDD 2.7V 5.25V). internal VREF selected, then AGND must connected REFIN-. REFOUT/REFIN+ should also have 0.1µF capacitor connected AGND close possible pin. internal VREF used, then VREF should disabled ADCON0. external voltage reference selected, used either single-ended input differential input, ratiometric measures. When using external reference, important note that input current will increase VREF with higher settings with higher modulator frequency. external voltage reference used over input range specified electrical characteristics section.
IDAC
8-bit IDAC MSC1201/02 used provide current source that used ratiometric measurements. IDAC operates from voltage reference dependent voltage reference. full-scale output current IDAC approximately 1mA. equation IDAC output current
IDAC IDAC 3.6mA
RESET
Taking high stops operation device, taking initiates reset. device also reset Power Reset circuitry, Digital Brownout Reset, Software Reset. timing reset operation shown Electrical Characteristic section. P1.0/PROG unconnected tied high, device will enter User Application mode (UAM) reset. P1.0/PROG tied during reset, device will enter Serial Programming mode.
Figure Filter Frequency Responses
POWER RESET
on-chip Power Reset (POR) circuitry releases device from reset approximately DVDD 2.0V. accommodates power-supply ramp rates slow 1V/10ms. ensure proper operation, power supply should ramp monotonically. Note that, device released from reset program execution begins,
VOLTAGE REFERENCE
MSC1201/02 either internal external voltage reference. voltage reference selection controlled Control Register (ADCON0, DCh). default power-up configuration voltage reference 2.5V internal.
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device current consumption increase, which result power-supply voltage drop. power supply ramps slower rate, monotonic, brownout condition occurs (where supply does drop below 2.0V threshold), then improper device operation occur. on-chip Brownout Reset provide benefit these conditions. circuit shown Figure
DBOR level should chosen match closely with application. That with high external clock frequency, DBOR level should match minimum operating voltage range device improper operation still occur.
ANALOG LOW-VOLTAGE DETECT
MSC1201/02 contain analog low-voltage detect. When analog supply drops below value programmed LVDCON (SFR E7h), interrupt generated.
DVDD 0.1µF
MSC1201/02
CLOCKS
MSC1201/02 operate three separate clock modes: Internal Oscillator mode (IOM), External Clock mode (ECM), Phase Lock Loop (PLL) mode. block diagram shown Figure clock mode MSC1201/02 selected CLKSEL bits HCR2. default mode device. Serial Flash Programming mode (SFPM) uses low-frequency (LF) mode (the HCR2 CLKSEL bits have effect). Table shows active clock mode various startup conditions during UAM.
Figure Typical Reset Circuit
DIGITAL BROWNOUT RESET
Digital Brownout Reset (DBOR) enabled through Hardware Configuration Register (HCR1). conditions proper device encounters brownout condition that does generate POR, DBOR used ensure proper device operation. DBOR will hold state device when power supply drops below threshold level programmed HCR1, then generate reset when supply rises above threshold level. Note that, device released from reset program execution begins, device current consumption increase, which result power supply voltage drop, which initiate another brownout condition. Also, DBOR comparison done against analog reference; therefore, AVDD must within valid operating range DBOR function.
Internal Oscillator
IOM, executes either mode HCR2, CLKSEL 111) high-frequency (HF) mode HCR2, CLKSEL 110). this mode, must grounded tied supply.
External Clock
(HCR2, CLKSEL 011), execute from external crystal, external ceramic resonator, external clock, external oscillator. external clock detected startup, then will begin execution after startup. external clock detected startup, then device will revert mode shown Table
STOP Phase Detector Charge Pump 100k
tOSC tPLL/tIOM tSYS SYSCLK tCLK
XOUT
LF/HF Internal Mode Oscillator PLLDIV
NOTE: Disabled mode; therefore, external resistor between XOUT required.
Figure Clock Block Diagram
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Table Active Clock Modes
SELECTED CLOCK MODE (HCR2, CLKCON2:0) External Clock Mode (ECM) Mode Mode Mode PLL(3) Mode STARTUP CONDITION(1) Active clock present clock present Active 32.768kHz clock clock present Active 32.768kHz clock clock present ACTIVE CLOCK MODE (fSYS) External Clock Mode Mode Mode Mode Mode Nominal Mode Mode Nominal Mode
Internal Oscillator Mode (IOM)(2)
Clock detection only done startup; refer Electrical Characteristics parameter tRFD Figure must left floating; must tied high low. operation requires that both AVDD DVDD within their specified ranges.
mode (HCR2, CLKSEL HCR2, CLKSEL 100), execute from external 32.768kHz crystal. This mode enables circuit that synthesizes selected clock frequencies (PLL mode mode). external clock detected startup, then will begin execution mode after startup. external clock detected startup, then device will revert mode shown Table status determined first writing PLLLOCK (enable) then reading PLLLOCK status PLLH SFR. frequency preloaded with default trimmed values. However, frequency fine-tuned writing PLLDIV1 PLLDIV0 SFRs. equation frequency Frequency ((PLLDIV9:PLLDIV0) fOSC where fOSC 32.768kHz. default value mode automatically loaded into PLLDIV SFR. mode, PLLDIV must loaded with appropriate value. different connections external clocks, Figure Figure Figure
XOUT
NOTE: Refer crystal manufacturer's specification values.
Figure External Crystal Connection
External Clock
Figure External Clock Connection
32pF 32.768kHz XOUT 32pF NOTE: Typical configuration shown.
Figure Connection
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MSC1201/02 implement basic interface that includes hardware simple serial data transfers. Figure shows block diagram SPI. peripheral supports master slave modes, full duplex data transfers, both clock polarities, both clock phases, order, slave select. timing diagram supported data transfers shown Figure pins needed data transfer Data (DIN), Data (DOUT) serial clock (SCK). slave select (SS) also used control output data DOUT. used shifting data both master slave modes. DOUT used shifting data both master slave modes. used synchronize transfer data both master slave modes. always generated master. generation master mode done either software simply toggling port pin, configuring output PASEL (SFR F2h). list most common methods generating follows, complete list clock sources found referring PASEL SFR.
Toggle setting clearing port pin. Memory Write Pulse (WR) that idle high.
Whenever external memory write command (MOVX) executed, pulse seen P3.6. This method used only CPOL `1'.
Memory Write Pulse toggle version. this mode,
toggles whenever external write command (MOVX) executed.
T0_Out signal used clock. pulse
generated whenever Timer expires. idle state signal low, this used only CPOL cleared `0'.
T0_Out toggle. toggles whenever Timer
expires.
T1_Out signal used clock. pulse
generated whenever Timer expires. idle state signal low, this used only CPOL cleared `0'.
T1_Out toggle. toggles whenever Timer
expires.
DOUT Data Write TX_CLK SPICON I2CCON CNT_CLK Counter Start/Stop Detect Logic SCK/SCL Control P3.6 Stretch Control RX_CLK /I2C Data Read P1.4 P1.2 DOUT
P1.3
CLKS (refer PASEL, F2h)
Figure SPI/I2C Block Diagram
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Cycle (CPOL
(CPOL
Sample Input (CPHA Data Sample Input (CPHA Data Slave Slave CPHA Transfer Progress Asserted First Edge CNTIF (dependent CPHA bit) Negated Slave CPHA Transfer Progress
Figure Timing Diagram
used control output data DOUT when MSC1201/02 slave mode. function enabled disabled SPICON SFR. When enabled, input slave device must externally asserted before master device exchange data with slave device. must before data transactions must stay duration transaction. When high, data will shifted into shift register will counter increment. When enabled, also controls drive line DOUT (P1.2). When slave mode, DOUT will driven when high, DOUT will high impedance. generates interrupt ECNT (AIE.2) indicate that transfer/reception byte complete. interrupt goes high whenever counter value equal (indicating that eight SCKs have occurred). interrupt cleared reading writing SPIDATA register. During data transfer, actual counter value read from SPICON SFR.
Application Flow
This section explains typical application usage flow master slave modes.
Master Mode Application Flow Configure port pins. Configure SPI. Assert enable slave communication applicable). Write data SPIDATA. Generate eight SCKs. Read received data from SPIDATA. Slave Mode Application Flow Configure ports pins. Enable applicable). Configure SPI. Write data SPIDATA. Wait Count Interrupt (eight SCKs). Read data from SPIDATA.
CAUTION: SPIDATA read before next transaction, ECNT interrupt will removed previous data will lost.
Power Down
powered down PDSPI power control register (PDCON). This needs cleared enable function. When powered down, pins P1.2, P1.3, P1.4, P3.6 revert general-purpose pins.
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pins needed transfer serial clock (SCL) serial data (SDA-implemented connecting DOUT externally). transfer timing shown Figure MSC1201/02 supports:
Master slave operation (control software) Standard fast modes transfer Clock stretching General call
When used mode, pins (P1.3) DOUT (P1.2) should tied together externally. should configured input DOUT should configured open drain standard 8051 setting P1DDR (DOUT should high that pulled low). MSC1201/02 generate interrupts:
interrupt generation data transfer (I2CCON.CNTSEL). This used ACK/NACK interrupt generation. instance, interrupt configured 8-bit interrupt detection; eighth bit, interrupt generated. Following this interrupt, clock stretched (SCL held low). interrupt then configured 1-bit detection, which will terminate clock stretching. ACK/NACK written software, which will terminate clock stretching. next interrupt will generated after ACK/NACK been latched receiving device. interrupt cleared reading writing I2CDATA register. I2CDATA read before next data transfer, interrupt will removed previous data will lost.
Master Operation
source controlled PASEL register generated software.
Transmit
serial data must stable while high. Therefore, writing serial data I2CDATA must coordinated with generation SCL, since transitions interpreted START STOP while high. START STOP conditions must generated software. After serial data been transmitted, generation ACK/NACK clock must enabled writing 0xFFh I2CDATA. This allows master read state ACK/NACK.
interrupt START/STOP interrupt (AIE.3) interrupt counter interrupt (AIE.2)
START/STOP interrupt generated when START condition STOP condition detected bus. counter generates interrupt complete (8-bit) data transfer also after transfer ACK/NACK. counter serial transfer always incremented falling edge reset reading writing I2CDATA (SFR 9Bh) when START/STOP condition detected. counter polled used interrupt. counter interrupt occurs when counter value equal indicating that eight bits data have been transferred. mode also allows
Receive
serial data latched into receive buffer rising edge SCL. After serial data been received, ACK/NACK generated writing 0x7Fh (for ACK) 0xFFh (for NACK) I2CDATA.
START ADDRESS(2) Condition(1)
R/W(2)
ACK(3)
DATA(2)
ACK(3)
DATA(2)
ACK(3)
STOP Condition(4)
NOTES: Generate software; write 0x7F I2CDATA. I2CDATA register. Generate software. enable count interrupt prior ACK/NACK interrupt use. Generate writing 0x7F I2CDATA; generate NACK writing 0xFF I2CDATA. Generate software; write 0xFF I2CDATA.
Figure Timing Diagram Transmission Reception
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Slave Operation
Slave operation supported, address recognition, determination, ACK/NACK must done under software control. Disable Clock Stretch (DCS) disable clock stretching. When set, device will longer stretch clock will generate interrupts. This used disable clock stretch interrupts when there address match. This automatically cleared when start repeated start condition occurs.
activated through hardware configuration bits, which disables erase/write operation Program Flash Memory entire Program Flash Memory User Application mode.
FLASH MEMORY
MSC1201/02 memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). program data segments overlap since they accessed different instructions. Program Memory fetched microcontroller automatically. MOVC instruction that used explicitly read program area, commonly used read lookup tables. MSC1201/02 have three Hardware (HW) Configuration registers (HCR0, HCR1, HCR2) that programmable only during Flash Memory Programming mode. MSC1201/02 allow user partition Flash Memory between Program Memory Data Memory. instance, MSC1201Y3/MSC1202Y3 contain Flash Memory on-chip. Through configuration registers, user define partition between Program Memory (PM) Data Memory (DM), shown Table Table Figure MSC1201/02 families offer memory configurations.
Transmit
Once address recognition, determination, ACK/NACK complete, serial data transferred written I2CDATA. data automatically shifted based master SCL. After data transmission, CNTIF generated stretched MSC1201/02 until I2CDATA register written with 0xFFh. ACK/NACK from master then read.
Receive
Once address recognition, determination, ACK/NACK complete, I2CDATA must written with 0xFFh enable data reception. Upon completion data shift, MSC1201/02 generates interrupt stretches SCL. Received data then read from I2CDATA. After serial data been received, ACK/NACK generated writing 0x7Fh (for ACK) 0xFFh (for NACK) I2CDATA. write I2CDATA clears interrupt clock stretch.
Table Flash Memory Partitioning
HCR0 DFSEL (default) MSC1201/02Y2 MSC1201/02Y3
MEMORY
MSC1201/02 contain on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM. registers primarily used control status. standard 8051 features additional peripheral features MSC1201/02 controlled through SFR. Reading from undefined will return zero. Writing undefined registers recommended will have indeterminate effects. Flash Memory used both Program Memory Data Memory. Program/Data Memory partition size selectable. partition size through hardware configuration bits, which programmed serially. Both Program Data Flash Memories erasable writable (programmable) User Application mode. However, program execution only occur from Program Memory. added precaution, lock feature
Table Flash Memory Partitioning Addresses
HCR0 DFSEL (default) MSC1201/02Y2 0000-07FF 0000-07FF 0000-0BFF 0000-0FFF 0400-0BFF 0400-0BFF 0400-07FF 0000 MSC1201/02Y3 0000-0FFF 0000-17FF 0000-1BFF 0000-1FFF 0400-13FF 0400-0BFF 0400-07FF 0000
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Program Memory
FFFFh Unused Select HCR0 FC00h Internal Boot F800h
Data Memory
FFFFh
System Memory
Unused UAM: Read Only SFPM: Read Only
Unused
2000h, (Y3) On-Chip Flash 1400h, (Y3) 1000h, (Y2) 0000h, On-Chip Flash 0C00h, (Y2) 0400h, UAM: Read Only SFPM: ReadWrite
Figure Memory
important note that Flash Memory readable writable (depending MXWS SFR) user through MOVX instruction when configured either Program Data Memory. This means that user partition device maximum Flash Program Memory size Flash Data Memory) Flash Program Memory Flash Data Memory. This lead undesirable behavior points area Flash Program Memory that being used data storage. Therefore, recommended Flash partitioning when Flash Memory used data storage. Flash partitioning prohibits execution code from Data Flash Memory. Additionally, Program Memory erase/write disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) Data Flash Memory. effect memory mapping Program Data Memory straightforward. Program Memory decreased size from Flash Memory. maintain compatibility with MSC121x, Flash Data Memory maps addresses 0400h. Therefore, access Data Memory (through MOVX) will access Flash Memory addresses shown Table
Data Memory
MSC1201/02 on-chip Flash Data Memory, which readable writable (depending Memory Write Select register) during normal operation (full range). This memory mapped into external Data Memory space, which requires MOVX instruction program. Note that page size bytes both Program Data Memory page must erased before written.
System Memory
System Memory nonvolatile memory that read User Application mode through faddr_data_read Boot routine. Serial Flash Programming mode, lower bytes written. lower bytes include Hardware Configuration registers.
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REGISTER
Register illustrated Figure entirely separate from Program Data Memory areas mentioned before. separate class instructions used access registers. There potential register locations. practice, MSC1201/02 have bytes Scratchpad SFRs. This possible, since upper Scratchpad locations only accessed indirectly. Thus, direct reference upper locations must access. Direct reached locations 127).
Word register (PSW; 0D0h) area described below. bytes immediately above R0-R7 registers bit-addressable, bits this area directly accessed using bit-addressable instructions.
Direct Addressable
Indirect Direct Scratchpad
Direct Special Function Registers
Registers
Figure Register
SFRs accessed directly between (128 255). locations between reached through indirect reference those locations. Scratchpad available general-purpose data storage. Within bytes RAM, there several special-purpose areas.
Addressable Locations
addition direct register access, some individual bits also accessible. These individually addressable bits both area. Scratchpad area, registers bit-addressable. This provides individual bits available software. access distinguished from full-register access type instruction. area, register location ending bit-addressable. Figure shows details on-chip addressing including locations individual bits.
Bank Bank Bank Bank
Working Registers
part lower bytes RAM, there four banks Working Registers, shown Figure Working Registers general-purpose locations that addressed special way. They designated through Since there four banks, currently selected bank will used instruction using R0-R7. This allows software change context simply switching banks. This controlled Program Status
Figure Scratchpad Register Addressing
Thus, instruction designate value stored (for example) address upper RAM. bytes immediately above these registers bit-addressable, bits this area directly accessed using bit-addressable instructions.
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Stack
Another Scratchpad area programmer's stack. This area selected using Stack Pointer (SP, 81h). Whenever call interrupt invoked, return address placed Stack. also available programmer variables, etc., since Stack moved there fixed location within designated Stack. Stack Pointer defaults reset user then move needed. will point last used value. Therefore, next value placed Stack Each PUSH CALL increments appropriate value each decrements
Table MSC1201/02 Maximum Internal Program Memory Sizes
MODEL NUMBER MSC1201Y2/MSC1202Y2 MSC1201Y3/MSC1202Y3 STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES)
Boot
There Boot that controls operation during serial programming. Additionally, Boot routines shown Table accessed during user mode, enabled. When enabled, Boot routines will located memory addresses F800h-FBFFh during user mode.
Program Memory
After reset, begins execution from Program Memory location 0000h. standard internal Program Memory size MSC1201/02 family members shown Table enabled, Boot will appear from address F800h FFFFh.
Table MSC1201/02 Boot Routines
ADDRESS F802 F805 FBD8 FBDA FBDC FBDE FBE0 FBE2 FBE4 FBE6 FBE8 FBEA FBEC FBEE FBF0 FBF2 FBF4 FBF6 FBF8 FBFA FBFC FBFE ROUTINE sfr_rd sfr_wr monitor_isr cmd_parser put_string page_erase write_flash write_flash_chk write_flash_byte faddr_data_read data_x_c_read tx_byte tx_hex putx rx_byte rx_byte_echo rx_hex_echo rx_hex_dbl_echo rx_hex_word_echo autobaud putspace1 putcr DECLARATIONS char sfr_rd(void); void sfr_wr(char void monitor_isr() interrupt void cmd_parser(void); void put_string(char code *string); char page_erase(int faddr, char fdata, char fdm); Assembly only; DPTR address, data char write_flash_chk(int faddr, char fdata, char fdm); void write_flash_byte(int faddr, char fdata); char faddr_data_read(char faddr); char data_x_c_read(int faddr, char fdm); void tx_byte(char); void tx_hex(char); void putx(void); char rx_byte(void); char rx_byte_echo(void); char rx_hex_echo(void); int_rx_hex_dbl_echo(void); int_rx_hex_word_echo(void); void autobaud(void); void putspace1(void); void putcr(void); DESCRIPTION Return value pointed CADDR(1) Write pointed CADDR(1) Push registers call cmd_parser application note SBAA076, Programming MSC1210, available www.ti.com. Output string Erase flash page Flash write(2) Write flash byte, verify Write flash byte(2) Read System Memory byte from faddr Read xdata code byte Send byte USART0 send value USART0 send USART0 Read byte from USART0 Read echo byte USART0 Read echo USART0 Read echo: USART0 Read reversed echo: USART0 baud with received CR(3) Output space USART0 Output USART0
CADDR must using faddr_data_read routine. register (SFR 8Fh) defines Data Memory Program Memory write. registers CKCON TCON must initialized: CKCON 0x10 TCON 0x00.
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Serial Flash Programming Mode
Serial Flash Programming mode initiated holding P1.0/PROG during reset, shown Figure User Application mode also allows Flash programming. Code execution from Flash Memory cannot occur this mode while programming, code execution occur from Boot while programming.
INTERRUPTS
MSC1201/02 three-priority interrupt system. shown Table each interrupt source independent priority bit, flag, interrupt vector, enable (except that nine interrupts share Auxiliary Interrupt, highest priority). addition, interrupts globally enabled disabled. interrupt structure compatible with original 8051 family. standard interrupts available.
MSC1201/02 P3.0/RxD0 P3.1/TxD0 P1.0/PROG Programmer
HARDWARE CONFIGURATION MEMORY
configuration bytes only written during program mode. bytes accessed through registers CADDR (SFR 93h) CDATA (SFR 94h) using faddr_data_read Boot-ROM routine. Three configuration bytes control Flash partitioning system control. security set, these bits cannot changed except with Mass Erase command that erases Flash Memory, including configuration bytes.
NOTE: User Application mode, avoid heavy loading P1.0/PROG, which result erroneously entering Serial Flash Programming mode power-
Figure Serial Flash Programming Mode Table Interrupt Summary
INTERRUPT INTERRUPT/EVENT AVDD Voltage Detect Count (SPI/I2C) Start/Stop Milliseconds Timer Summation Register Seconds Timer External Interrupt Timer Overflow External Interrupt Timer Overflow Serial Port External Interrupt External Interrupt External Interrupt External Interrupt Watchdog ADDR PRIORITY HIGH FLAG ALVDIP (AIPOL.1)(1) CNTIP (AIPOL.2)(1) I2CIP (AIPOL.3)(1) ENABLE EALV (AIE.1)(1) ECNT (AIE.2)(1) EI2C (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE.5)(1) PRIORITY CONTROL (IP.0) (IP.1) (IP.2) (IP.3) (IP.4) (EIP.0) (EIP.1) (EIP.2) (EIP.3) PWDI (EIP.4)
MSECIP (AIPOL.4)(1) ADCIP (AIPOL.5)(1)
SUMIP (AIPOL.6)(1) SECIP (AIPOL.7)(1) (TCON.1)(2)
ESUM (AIE.6)(1) ESEC (AIE.7)(1) (IE.0)(4)
(TCON.5)(3) (TCON.3)(2)
(IE.1)(4) (IE.2)(4)
(TCON.7)(3) RI_0 (SCON0.0) TI_0 (SCON0.1) (EXIF.4) (EXIF.5) (EXIF.6) (EXIF.7) WDTI (EICON.3)
(IE.3)(4) (IE.4)(4) (EIE.0)(4) (EIE.1)(4)
(EIE.2)(4) (EIE.3)(4) EWDI (EIE.4)(4)
These interrupts flag (EICON.4) enabled (EICON.5). edge-triggered, cleared automatically hardware when service routine vectored level-triggered, flag follows state pin. Cleared automatically hardware when interrupt vector occurs. Globally enabled (IE.7).
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Hardware Configuration Register (HCR0)-Accessed Using Registers CADDR CDATA.
CADDR EPMA EWDR DFSEL1 DFSEL0
EPMA
Enable Programming Memory Access (Security Bit). After reset programming modes, Flash Memory only accessed until mass erase done. Fully Accessible (default) Program Memory Lock (PML Priority Over RSL). Enable read write Program Memory UAM. Enable Read-Only mode Program Memory (default). Reset Sector Lock. reset sector used provide another method Flash Memory programming. This will allow Program Memory updates without changing jumpers in-circuit code updates program development. code this boot sector would then provide monitor programming routines with ability jump into main Flash code when programming finished. Enable Reset Sector Writing Enable Read-Only mode reset sector (4kB) (default). Same effect MSC1201Y2/MSC1202Y2. Enable Boot ROM. Boot code located ROM, confused with Boot Sector located Flash Memory. Disable Internal Boot Enable Internal Boot (default) Enable Watchdog Reset. Disable Watchdog Reset Enable Watchdog Reset (default)
EWDR
DFSEL1-0 Data Flash Memory Size (See Table bits Data Flash Memory (MSC1201Y3/MSC1202Y3 Only) Data Flash Memory Data Flash Memory Data Flash Memory (default)
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Hardware Configuration Register (HCR1)
CADDR
Disable Digital Brownout Detection. Enable Digital Brownout Detection (2.7V) Disable Digital Brownout Detection (default)
Hardware Configuration Register (HCR2)
CADDR CLKSEL2 CLKSEL1 CLKSEL0
CLKSEL2-1 Clock Select. bits 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: High-Frequency (HF) Mode 101: Low-Frequency (LF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode
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DEFINITIONS
ADDRESS AIPOL AISTAT SECIP ESEC SUMIP ESUM ADCIP EADC MSECIP EMSEC MSEC I2CIP PAI3 EI2C CNTIP PAI2 ECNT ALVDIP PAI1 EALV ALVD PAI0 SCON0 SBUF0 SPICON I2CCON SPIDATA I2CDATA SBIT3 SBIT3 SBIT2 SBIT2 SBIT1 SBIT1 SBIT0 SBIT0 ORDER STOP CPHA START CPOL CNTSEL SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 CKCON EXIF MPAGE CADDR CDATA P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 P1.2 DOUT P1.1 MXWS P1.0 PROG DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD SMOD STOP IDLE REGISTER RESET VALUE
Timer GATE
Timer GATE
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DEFINITIONS (continued)
ADDRESS SYSCLK DIVMOD1 DIVMOD0 EWUWDT DIV2 EWUEX1 DIV1 EWUEX0 DIV0 P3DDRL P3DDRH IDAC P33H P37H P33L P37L P32H P36H P32L P36L P31H P35H P31L P35L P30H P34H P30L P34L P1DDRL P1DDRH P13H P17H P3.7 P13L P17L P3.6
SCK/SCL/CLKS
REGISTER
RESET VALUE
P12H P16H P3.5
P12L P16L P3.4
P11H P15H P3.3 INT1
P11L P15L P3.2 INT0
P10H P14H P3.1 TXD0
P10L P14L P3.0 RXD0
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DEFINITIONS (continued)
ADDRESS REGISTER ADMUX EICON ADRESL(1) ADRESM(1) ADRESH(1) ADCON0 ADCON1 ADCON2 ADCON3 SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON HWPC0 HWPC1 HWVER Reserved Reserved FMCON FTCON PDCON PASEL Reserved PLLL PLLH ACLK SRST SECINT MSINT USEC MSECL MSECH HMSEC WDTCON PLL7 CKSTAT2 MSECL7 MSECH7 HMSEC7 EWDT PLL6 CKSTAT1 FREQ6 SECINT6 MSINT6 MSECL6 MSECH6 HMSEC6 DWDT PLL5 CKSTAT0 FREQ5 SECINT5 MSINT5 FREQ5 MSECL5 MSECH5 HMSEC5 RWDT PLL4 PLLLOCK FREQ4 PWDI SECINT4 MSINT4 FREQ4 MSECL4 MSECH4 HMSEC4 WDCNT4 PLL3 FREQ3 SECINT3 MSINT3 FREQ3 MSECL3 MSECH3 HMSEC3 WDCNT3 PLL2 FREQ2 SECINT2 MSINT2 FREQ2 MSECL2 MSECH2 HMSEC2 WDCNT2 PLL1 PLL9 FREQ1 SECINT1 MSINT1 FREQ1 MSECL1 MSECH1 HMSEC1 WDCNT1 PLL0 PLL8 FREQ0 RSTREQ SECINT0 MSINT0 FREQ0 MSECL0 MSECH0 HMSEC0 WDCNT0 xxh(2) xxh(2) PDICLK PSEN4 PDIDAC PSEN3 PDI2C PSEN2 PSEN1 PDADC PSEN0 PDWDT PDST PDSPI FER3 PGERA FER2 FER1 FRCM FER0 FWR3 BUSY FWR2 FWR1 FWR0 ALVDIS EWDI DEVICE MEMORY OF_UF ACC.7 SSCON1 MSB(1) MSB(1) ACC.6 SSCON0 EVREF ACC.5 SCNT2 VREFH ACC.4 SCNT1 EBUF ACC.3 SCNT0 PGA2 CAL2 DR10 ACC.2 SHF2 PGA1 CAL1 ACC.1 SHF1 PGA0 CAL0 ACC.0 SHF0 INP3 INP2 INP1 INP0 INN3 WDTI INN2 INN1 INN0 LSB(1) RESET VALUE 0000_00xxb
MSC1201, result contained ADRESH, ADRESM, ADRESL. MSC1202, result contained ADRESM ADRESL (that shifted right byte) sign-extended (Bipolar mode) zero-padded (Unipolar mode) ADRESH. Therefore, when migrating between MSC1201 MSC1202, result calculation must adjusted accordingly. both MSC1201 MSC1202, interrupt cleared reading ADRESL. Dependent HCR2 value.
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Stack Pointer (SP)
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Reset Value
SP.7-0 bits
Stack Pointer. stack pointer identifies location where stack will begin. stack pointer incremented before every PUSH CALL operation decremented after each RET/RETI. This register defaults after reset.
Data Pointer (DPL0)
DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 Reset Value
DPL0.7-0 bits
Data Pointer This register byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86h).
Data Pointer High (DPH0)
DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 Reset Value
DPH0.7-0 bits
Data Pointer High This register high byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86h).
Data Pointer (DPL1)
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Reset Value
DPL1.7-0 bits
Data Pointer This register byte auxiliary 16-bit data pointer. When (DPS.0) (SFR 86h) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer High (DPH1)
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Reset Value
DPH1.7-0 bits
Data Pointer High. This register high byte auxiliary 16-bit data pointer. When (DPS.0) (SFR 86h) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer Select (DPS)
Reset Value
Data Pointer Select. This selects active data pointer. Instructions that DPTR will DPL0 DPH0. Instructions that DPTR will DPL1 DPH1.
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Power Control (PCON)
SMOD STOP IDLE Reset Value
SMOD STOP IDLE
Serial Port Baud Rate Doubler Enable. serial baud rate doubling function Serial Port Serial Port baud rate will standard baud rate. Serial Port baud rate will double that defined baud rate generation equation. General-Purpose User Flag This general-purpose flag software control. General-Purpose User Flag This general-purpose flag software control. Stop Mode Select. Setting this will halt internal oscillator block external clocks. This will always read Exit with RESET. this mode, internal peripherals frozen pins held their current state. frozen, IDAC VREF remain active. Idle Mode Select. Setting this will freeze CPU, Timer USART; other peripherals remain active. This will always read Exit with (A6h) (C6h) interrupts (refer Figure clocks affected during IDLE).
Timer/Counter Control (TCON)
Reset Value
Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH1, TL1. Timer halted. Timer enabled. Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH0, TL0. Timer halted. Timer enabled. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT1 pin. Interrupt Type Select. This selects whether INT1 will detect edge- level-triggered interrupts. INT1 level triggered. INT1 edge triggered. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT0 pin. Interrupt Type Select. This selects whether INT0 will detect edge- level-triggered interrupts. INT0 level triggered. INT0 edge triggered.
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Timer Mode Control (TMOD)
GATE TIMER GATE TIMER Reset Value
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT1. Timer will clock only when INT1 Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.6, 88h) Timer Mode Select. These bits select operating mode Timer
MODE Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto reload. Mode Timer halted, holds count.
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT0 (software control). Timer will clock only when INT0 (hardware control). Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.4, 88h) Timer Mode Select. These bits select operating mode Timer
MODE Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto reload. Mode 8-bit counters.
Timer (TL0)
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Reset Value
TL0.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TL1)
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 Reset Value
TL1.7-0 bits
Timer LSB. This register contains least significant byte Timer
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Timer (TH0)
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Reset Value
TH0.7-0 bits
Timer MSB. This register contains most significant byte Timer
Timer (TH1)
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 Reset Value
TH1.7-0 bits
Timer MSB. This register contains most significant byte Timer
Clock Control (CKCON)
Reset Value
Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide-by-12 crystal frequency. Timer uses divide-by-4 crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide-by-12 crystal frequency. Timer uses divide-by-4 crystal frequency. Stretch MOVX Select. These bits select time which external MOVX cycles stretched. Since MSC1201/02 does allow external memory access, these bits should 000B allow fastest Flash Data Memory access.
MD2, MD1, bits
Memory Write Select (MWS)
MXWS Reset Value
MXWS
MOVX Write Select. This allows writing internal Flash Program Memory. writes allowed internal Flash Program Memory. Writing allowed internal Flash Program Memory, unless (HCR0, CADDR 3Fh)
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Port (P1)
P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 P1.2 DOUT P1.1 P1.0 PROG Reset Value
P1.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. alternate function, appropriate mode P1DDRL (SFR AEh), P1DDRH (SFR AFh). External Interrupt falling edge this will cause external interrupt enabled.
INT5 INT4 INT3 INT2/SS DOUT PROG
External Interrupt rising edge this will cause external interrupt enabled.
External Interrupt falling edge this will cause external interrupt enabled.
External Interrupt rising edge this will cause external interrupt enabled. This used slave select (SS) slave mode. Serial Data This receives serial data modes mode, this should configured input) standard 8051. Serial Data Out. This transmits serial data modes mode, this should configured open drain) standard 8051. Program Mode. When this pulled power-up, device enters Serial Programming mode (refer Figure
External Interrupt Flag (EXIF)
Reset Value
External Interrupt Flag. This will when falling edge detected INT5. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT4. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when falling edge detected INT3. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT2. This must cleared manually software. Setting this software will cause interrupt enabled.
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Configuration Address Register (CADDR) (write-only)
Reset Value
CADDR bits
Configuration Address Register. This register supplies address reading bytes bytes Flash Configuration Memory. Always Boot CADDR access routine (faddr_data_read). This register also used read write routines.
CAUTION: this register written while executing from Flash Memory, CDATA register will incorrect.
Configuration Data Register (CDATA) (read-only)
Reset Value
CDATA bits
Configuration Data Register. This register will contain data bytes Flash Configuration Memory that located last written address CADDR register. This read-only register.
Serial Port Control (SCON0)
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE FUNCTION Synchronous Synchronous Asynchronous Asynchronous-Valid Stop Required(2) Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication(3) LENGTH bits bits bits bits bits bits bits bits PERIOD pCLK(1) pCLK(1) Timer Baud Rate Equation Timer Baud Rate Equation pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD Timer Baud Rate Equation Timer Baud Rate Equation
pCLK will equal tCLK, except that pCLK will stop IDLE. RI_0 will only activated when valid STOP received. RI_0 will activated
REN_0
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes
TB8_0 RB8_0 TI_0
Received State. This identifies state reception received data serial Port modes serial port mode when SM2_0 RB8_0 state stop bit. RB8_0 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_0 data bit. other modes, this last data bit. This must manually cleared software. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_0 bit. serial port mode RI_0 after last sample incoming stop subject state SM2_0. modes RI_0 after last sample RB8_0. This must manually cleared software.
RI_0
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Serial Data Buffer (SBUF0)
Reset Value
SBUF0 bits
Serial Data Buffer Data Serial Port read from written this location. serial transmit receive buffers separate registers, both addressed this location.
Control (SPICON)
SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA CPOL Reset Value
SBIT3-0 bits
Serial Count. Number bits transferred (read-only).
SBIT3:0 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C COUNT
ORDER
Order Transmit Receive. Most Significant Bits First Least Significant Bits First Serial Clock Phase Control. Valid data starting from half period before first edge Valid data starting from first edge Enable Slave Select. (P1.4) configured general-purpose (default). (P1.4) configured mode. DOUT (P1.2) drives when low, DOUT (P1.2) high-impedance when high. Serial Clock Polarity. idle logic idle logic HIGH
CPHA
CPOL
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Control (I2CCON)
SBIT3 SBIT2 SBIT1 SBIT0 STOP START CNTSEL Reset Value
SBIT3-0 bits
Serial Count. Number bits transferred (read-only).
SBIT3:0 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C COUNT
STOP
Stop-Bit Status. Stop Stop Condition Received I2CCNT (cleared write I2CDATA) Start-Bit Status. Stop Start Repeated Start Condition Received I2CCNT (cleared write I2CDATA) Disable Serial Clock Stretch. Enable Stretch (cleared firmware START condition) Disable Stretch Counter Select. Counter Counter (default) Counter Counter (default)
START
CNTSEL
Data Register (SPIDATA) Data Register (I2CDATA)
Reset Value
SPIDATA bits
Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location. Read clear receive interrupt write clear transmit interrupt. Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location.
I2CDATA bits
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Auxiliary Interrupt Poll (AIPOL)
SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP Reset Value
Interrupts enabled EICON.4 (SFR D8h). other interrupts controlled registers.
SECIP Second System Timer Interrupt Poll (before masking). Second System Timer Interrupt Poll Inactive Second System Timer Interrupt Poll Active Accumulator Interrupt Poll (before masking). Accumulator Interrupt Poll Inactive Accumulator Interrupt Poll Active Interrupt Poll (before masking). Interrupt Poll Inactive Interrupt Poll Active Millisecond System Timer Interrupt Poll (before masking). Millisecond System Timer Interrupt Poll Inactive Millisecond System Timer Interrupt Poll Active Interrupt Poll (before masking). Interrupt Poll Inactive Interrupt Poll Active Serial Count Interrupt Poll (before masking). Serial Count Interrupt Poll Inactive Serial Count Interrupt Poll Active Analog Voltage Detect Interrupt Poll (before masking). Analog Voltage Detect Interrupt Poll Inactive Analog Voltage Detect Interrupt Poll Active
SUMIP
ADCIP
MSECIP
I2CIP
CNTIP
ALVDIP
Pending Auxiliary Interrupt (PAI)
PAI3 PAI2 PAI1 PAI0 Reset Value
bits
Pending Auxiliary Interrupt Register. results this register used index vector appropriate interrupt routine. these interrupts vector through address 0033h.
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS Pending Auxiliary IRQ. Reserved. Analog Voltage Detect Possible Lower Priority Pending. Possible Lower Priority Pending. Serial Count Interrupt Possible Lower Priority Pending. Millisecond System Timer Possible Lower Priority Pending. Possible Lower Priority Pending. Accumulator Possible Lower Priority Pending. Second System Timer Possible Lower Priority Pending.
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Auxiliary Interrupt Enable (AIE)
ESEC ESUM EADC EMSEC EI2C ECNT EALV Reset Value
Interrupts enabled EICON.4 (SFR D8h). other interrupts controlled registers.
ESEC Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). Write: mask this interrupt; masked, enabled. Read: Second Timer Interrupt mask. Enable Summation Interrupt. Write: mask this interrupt; masked, enabled. Read: Summation Interrupt mask. Enable Interrupt. Write: mask this interrupt; masked, enabled. Read: Interrupt mask. Enable Millisecond System Timer Interrupt. Write: mask this interrupt; masked, enabled. Read: Millisecond System Timer Interrupt mask. Enable Start/Stop Bit. Write: mask this interrupt; masked, enabled. Read: Start/Stop mask. Enable Serial Count Interrupt. Write: mask this interrupt; masked, enabled. Read: Serial Count Interrupt mask. Enable Analog Voltage Interrupt. Write: mask this interrupt; masked, enabled. Read: Analog Voltage Detect Interrupt mask.
ESUM
EADC
EMSEC
ESPIT
ECNT
EALV
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Auxiliary Interrupt Status Register (AISTAT)
MSEC ALVD Reset Value
Second System Timer Interrupt Status Flag (lowest priority AI). interrupt cleared masked. Interrupt active cleared reading SECINT, F9h). Summation Register Interrupt Status Flag. interrupt cleared masked. interrupt active cleared reading lowest byte SUMR0, E2h). Interrupt Status Flag. interrupt cleared masked. interrupt active cleared reading lowest byte ADRESL, D9h; active, data will written Results registers). Millisecond System Timer Interrupt Status Flag. MSEC interrupt cleared masked. MSEC interrupt active cleared reading MSINT, FAh). Start/Stop Interrupt Status Flag. Start/stop interrupt cleared masked. Start/stop interrupt active cleared writing I2CDATA, 9Bh). Interrupt Status Flag. Interrupt cleared masked. Interrupt active cleared reading from writing SPIDATA/I2CDATA, 9Bh). Analog Voltage Detect Interrupt Status Flag. ALVD Interrupt cleared masked. ALVD Interrupt active (cleared AVDD exceeds ALVD threshold).
MSEC
ALVD
NOTE: interrupt masked, status read AIPOL (SFR A4h).
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Interrupt Enable (IE)
Reset Value
Global Interrupt Enable. This controls global masking interrupts except those (SFR A6h). Disable interrupt sources. This overrides individual interrupt mask settings this register. Enable individual interrupt masks. Individual interrupts this register will occur enabled. Enable Serial port Interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_0 (SCON0.0, 98h) TI_0 (SCON0.1, 98h) flags. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupt. Enable interrupt requests generated flag (TCON.7, 88h). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT1 pin. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (TCON.5, 88h). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT0 pin.
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Port Data Direction Register (P1DDRL)
P13H P13L P12H P12L P11H P11L P10H P10L Reset Value
P1.3 bits
Port control.
P13H P13L Standard 8051 CMOS Output Open Drain Output Input
P1.2 bits
Port control.
P12H P12L Standard 8051 CMOS Output Open Drain Output Input
P1.1 bits
Port control.
P11H P11L Standard 8051 CMOS Output Open Drain Output Input
P1.0 bits
Port control.
P10H P10L Standard 8051 CMOS Output Open Drain Output Input
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Port Data Direction High Register (P1DDRH)
P17H P17L P16H P16L P15H P15L P14H P14L Reset Value
P1.7 bits
Port control.
P17H P17L Standard 8051 CMOS Output Open Drain Output Input
P1.6 bits
Port control.
P16H P16L Standard 8051 CMOS Output Open Drain Output Input
P1.5 bits
Port control.
P15H P15L Standard 8051 CMOS Output Open Drain Output Input
P1.4 bits
Port control.
P14H P14L Standard 8051 CMOS Output Open Drain Output Input
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Port (P3)
P3.7 P3.6 SCK/SCL/CLKS P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 Reset Value
P3.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity.
SCK/SCL/CLKS Clock Source Select. Refer PASEL (SFR F2h). INT1 INT0 TXD0 RXD0 Timer/Counter External Input. transition this will increment Timer
Timer/Counter External Input. transition this will increment Timer
External Interrupt falling edge/low level this will cause external interrupt enabled.
External Interrupt falling edge/low level this will cause external interrupt enabled.
Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode
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Port Data Direction Register (P3DDRL)
P33H P33L P32H P32L P31H P31L P30H P30L Reset Value
P3.3 bits
Port control.
P33H P33L Standard 8051 CMOS Output Open Drain Output Input
P3.2 bits
Port control.
P32H P32L Standard 8051 CMOS Output Open Drain Output Input
P3.1 bits
Port control.
P31H P31L Standard 8051 CMOS Output Open Drain Output Input
P3.0 bits
Port control.
P30H P30L Standard 8051 CMOS Output Open Drain Output Input
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Port Data Direction High Register (P3DDRH)
P37H P37L P36H P36L P35H P35L P34H P34L Reset Value
P3.7 bits
Port control.
P37H P37L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.6 bits
Port control.
P36H P36L Standard 8051 CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.5 bits
Port control.
P35H P35L Standard 8051 CMOS Output Open Drain Output Input
P3.4 bits
Port control.
P34H P34L Standard 8051 CMOS Output Open Drain Output Input
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IDAC Register
Reset Value
IDAC bits
IDAC Register. IDACOUT IDAC 3.8µA (1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC float IDAC pin.
Interrupt Priority (IP)
Reset Value
Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt.
Enable Wake (EWU) Waking from IDLE Mode
EWUWDT EWUEX1 EWUEX0 Reset Value
Auxiliary interrupts will wake from IDLE. They enabled with (EICON.5).
EWUWDT Enable Wake Watchdog Timer. Wake using watchdog timer interrupt. wake watchdog timer interrupt. Wake watchdog timer interrupt. Enable Wake External Wake using external interrupt source wake external interrupt source Wake external interrupt source Enable Wake External Wake using external interrupt source wake external interrupt source Wake external interrupt source
EWUEX1
EWUEX0
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System Clock Divider Register (SYSCLK)
DIVMOD1 DIVMOD0 DIV2 DIV1 DIV0 Reset Value
DIVMOD1-0 Clock Divide Mode bits Write:
DIVMOD DIVIDE MODE Normal mode (default, divide). Immediate mode: start divide immediately; return Normal mode IDLE wakeup condition Normal mode write. Delay mode: same Immediate mode, except that mode changes with millisecond interrupt (MSINT). MSINT enabled, divide will start next MSINT return normal mode following MSINT. MSINT enabled, divide will start next MSINT condition (even masked) will leave divide mode until MSINT counter overflows, which follows wakeup condition. exit Normal mode write. Manual mode: start divide immediately; exit mode only write DIVMOD.
Read:
DIVMOD DIVISION MODE STATUS divide Divider Immediate mode Divider Delay mode Medium mode
DIV2-0
Divide Mode
DIVISOR Divide (default) Divide Divide Divide Divide Divide 1024 Divide 2048 Divide 4096 fCLK fSYS/2 fCLK fSYS/4 fCLK fSYS/8 fCLK fSYS/16 fCLK fSYS/32 fCLK fSYS/1024 fCLK fSYS/2048 fCLK fSYS/4096
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Program Status Word (PSW)
Reset Value
RS1, bits
Carry Flag. This when last arithmetic operation resulted carry (during addition) borrow (during subtraction). Otherwise cleared arithmetic operations. Auxiliary Carry Flag. This last arithmetic operation resulted carry into (during addition), borrow (during subtraction) from high order nibble. Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control.
Register Bank Select 1-0. These bits select which register bank addressed during register accesses.
REGISTER BANK ADDRESS
Overflow Flag. This last arithmetic operation resulted carry (addition), borrow (subtraction), overflow (multiply divide). Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control.
Parity Flag. This modulo-2 bits accumulator (odd parity); cleared even parity.
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Offset Calibration Register Byte (OCL)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Offset Calibration Register Byte. This byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Offset Calibration Register Middle Byte (OCM)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Offset Calibration Register Middle Byte. This middle byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Offset Calibration Register High Byte (OCH)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Offset Calibration Register High Byte. This high byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Gain Calibration Register Byte (GCL)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Gain Calibration Register Byte. This byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
Gain Calibration Register Middle Byte (GCM)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Gain Calibration Register Middle Byte. This middle byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
Gain Calibration Register High Byte (GCH)
Reset Value
Both MSC1201 MSC1202 support 24-bit calibration values.
bits Gain Calibration Register High Byte. This high byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
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Input Multiplexer Register (ADMUX)
INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 Reset Value
INP3-0 bits
Input Multiplexer Positive Input. This selects positive signal input.
INP3 INP2 INP1 INP0 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 REFIN- REFIN- AINCOM Temperature Sensor (requires ADMUX FFh)
INN3-0 bits
Input Multiplexer Negative Input. This selects negative signal input.
INN3 INN2 INN1 INN0 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 REFIN- REFIN- AINCOM Temperature Sensor (requires ADMUX FFh)
MSC1201 MSC1202
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Enable Interrupt Control (EICON)
WDTI Reset Value
Enable Auxiliary Interrupt. Auxiliary Interrupt accesses nine different interrupts which masked identified registers (SFR A5h), (SFR A6h), AISTAT (SFR A7h). Auxiliary Interrupt disabled (default). Auxiliary Interrupt enabled. Auxiliary Interrupt Flag. must cleared software before exiting interrupt service routine, after source interrupt cleared. Otherwise, interrupt occurs again. Setting software generates Auxiliary Interrupt, enabled. Auxiliary Interrupt detected (default). Auxiliary Interrupt detected. Watchdog Timer Interrupt Flag. WDTI must cleared software before exiting interrupt service routine. Otherwise, interrupt occurs again. Setting WDTI software generates watchdog time interrupt, enabled. Watchdog timer generate interrupt reset. interrupt available only reset action disabled HCR0. Watchdog Timer Interrupt Detected (default). Watchdog Timer Interrupt Detected.
WDTI
Results Register Byte (ADRESL)
Reset Value
ADRESL bits
Results Byte. This byte results. Reading from this register clears interrupt; however, EICON (SFR must also cleared.
Results Register Middle Byte (ADRESM)
Reset Value
ADRESM bits
Results Middle Byte. This middle byte results MSC1201 most significant byte MSC1202.
Results Register High Byte (ADRESH)
Reset Value
ADRESH bits
Results High Byte. This high byte most significant byte results MSC1201. This sign-extended (Bipolar mode) zero-padded (Unipolar mode) byte MSC1202 (that positive unipolar results negative results).
MSC1201 MSC1202
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Control Register (ADCON0)
EVREF VREFH EBUF PGA2 PGA1 PGA0 Reset Value
Burnout Detect. When enabled, this connects positive current source positive channel negative current source negative channel. channel open circuit, then results will full-scale (buffer must enabled). Burnout Current Sources (default). Burnout Current Sources Enable Internal Voltage Reference. external voltage used, internal voltage reference should disabled. Internal Voltage Reference external reference. Internal Voltage Reference (default). Note that REFIN- must connected AGND. Voltage Reference High Select. internal voltage reference selected 2.5V 1.25V. REFOUT/REF 1.25V. REFOUT/REF 2.5V (default). Enable Buffer. Enables input buffer provide higher input impedance limits input voltage range dissipates more power. Buffer disabled (default). Buffer enabled. Input signal limited AVDD 1.5V. Programmable Gain Amplifier. Sets gain from 128.
PGA2 PGA1 PGA0 GAIN (default)
EVREF
VREFH
EBUF
PGA2-0 bits
MSC1201 MSC1202
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Control Register (ADCON1)
OF_UF CAL2 CAL1 CAL0 Reset Value
OF_UF
Overflow/Underflow. this set, data Summation register invalid; either overflow underflow occurred. This cleared writing Polarity. Polarity result Summation register. Bipolar. Unipolar.
DIGITAL OUTPUT ANALOG INPUT +FSR ZERO -FSR +FSR ZERO -FSR MSC1201 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000 MSC1202(1) 0x7FFF 0x0000 0x8000 0xFFFF 0x0000 0x0000
MSC1202 result sign-extended into ADRESH.
SM1-0 bits
Settling Mode. Selects type filter auto select which defines digital filter settling characteristics.
SETTLING MODE Auto Fast Settling Filter Sinc2 Filter Sinc3 Filter
CAL2-0 bits
Calibration Mode Control Bits. Writing this register initiates calibration.
CAL2 CAL1 CAL0 CALIBRATION MODE Calibration (default) Self-Calibration, Offset Gain Self-Calibration, Offset only Self-Calibration, Gain only System Calibration, Offset only (requires external connection) System Calibration, Gain only (requires external connection) Reserved Reserved
NOTE: Read value-000B.
MSC1201 MSC1202
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Control Register (ADCON2)
Reset Value
DR7-0 bits
Decimation Ratio (refer ADCON3, DFh).
Control Register (ADCON3)
DR10 Reset Value
DR10-8 bits
Decimation Ratio Most Significant Bits. output data rate
fMOD Decimation Ratio where fMOD fCLK
(ACLK)1)
Accumulator ACC)
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Reset Value
ACC.7-0 bits
Accumulator. This register serves accumulator arithmetic logic operations.
MSC1201 MSC1202
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Summation/Shifter Control (SSCON)
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 Reset Value
Summation register powered down when powered down. zeroes written this register 32-bit SUMR3-0 registers will cleared. Summation registers will sign extend Bipolar Mode selected ADCON1.
SSCON1-0 Summation/Shift Count. bits
SSCON1 SSCON0 SCNT2 Note Note SCNT1 Note Note SCNT0 Note Note SHF2 Note Note SHF1 Note Note SHF0 Note Note DESCRIPTION Clear Summation Register Summation Write SUMR0 (sum count/shift ignored) Subtraction Write SUMR0 (sum count/shift ignored) Shift only Summation only Summation completes then shift completes
Refer register definition.
SCNT2-0 bits
Summation Count. When summation complete interrupt will generated unless masked. Reading SUMR0 register clears interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
SHF2-0 bits
Shift Count.
SHF2 SHF1 SHF0 SHIFT DIVIDE
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Summation Register (SUMR0)
Reset Value
SUMR0 bits
Summation Register This least significant byte 32-bit summation register bits Write: Will cause values SUMR3-0 added summation register. Read: Will clear Summation Interrupt.
Summation Register (SUMR1)
Reset Value
SUMR1 bits
Summation Register This most significant byte lowest bits summation register bits 8-15.
Summation Register (SUMR2)
Reset Value
SUMR2 bits
Summation Register This most significant byte lowest bits summation register bits 16-23.
Summation Register (SUMR3)
Reset Value
SUMR3 bits
Summation Register This most significant byte 32-bit summation register bits 24-31.
Offset Register (ODAC)
Reset Value
ODAC bits
Offset Register. This register will shift input half full-scale input range. Offset value summed into prior conversion. Writing ODAC turns Offset DAC. Offset Sign Bit. Positive Negative Offset *VREF ODAC bit7 (*1)
MSC1201 MSC1202
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Voltage Detect Control (LVDCON)
ALVDIS Reset Value
ALVDIS
Analog Voltage Detect Disable. Enable Detection Analog Supply Voltage (ALVD flag interrupt when AVDD 2.8V). Disable Detection Analog Supply Voltage.
Extended Interrupt Enable (EIE)
EWDI Reset Value
EWDI
Enable Watchdog Interrupt. This enables/disables watchdog interrupt. Watchdog timer enabled WDTCON (SFR FFh) PDCON (SFR F1h) registers. Disable Watchdog Interrupt Enable Interrupt Request Generated Watchdog Timer External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt
Hardware Product Code Register (HWPC0) (read-only)
DEVICE MEMORY Reset Value 0000_00xxb
HWPC0.7-0 Hardware Product Code LSB. Read-only. bits
DEVICE MEMORY MODEL MSC1201Y2 MSC1201Y3 MSC1202Y2 MSC1202Y3 FLASH MEMORY
Hardware Product Code Register (HWPC1) (read-only)
Reset Value
HWPC1.7-0 Hardware Product Code MSB. Read-only. bits
MSC1201 MSC1202
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Hardware Version Register (HWVER)
Reset Value
Flash Memory Control (FMCON)
PGERA FRCM BUSY Reset Value
PGERA
Page Erase. Available both user program modes. Disable Page Erase Mode Enable Page Erase Mode Frequency Control Mode. bypass only used slow clocks save power. Bypass (default) Delay Line. Saves power (recommended). Write/Erase BUSY Signal. Idle Available Busy
FRCM
BUSY
Flash Memory Timing Control Register (FTCON)
FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 Reset Value
Refer Flash Timing Characteristics
FER3-0 bits Erase. Flash Erase Time FER) (MSEC tCLK. 11ms industrial temperature range. commercial temperature range. Write. Flash Write Time FWR) (USEC tCLK. 30µs 40µs.
FWR3-0 bits
Register
Reset Value
B.7-0 bits
Register. This register serves second accumulator certain arithmetic operations.
MSC1201 MSC1202
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Power-Down Control Register (PDCON)
PDICLK PDIDAC PDI2C PDADC PDWDT PDST PDSPI Reset Value
Turning peripheral modules puts MSC1201/02 lowest power mode.
PDICLK Internal Clock Control. Internal Oscillator (Internal Oscillator mode) Internal Oscillator Power Down (External Clock mode) IDAC Control. IDAC IDAC Power Down (default) Control. (only when PDSPI Power Down (default) Control. ADC, VREF, Summation registers powered down (default). Watchdog Timer Control. Watchdog Timer Watchdog Timer Power Down (default) System Timer Control. System Timer System Timer Power Down (default) System Control. System System Power Down (default)
PDIDAC
PDI2C
PDADC
PDWDT
PDST
PDSPI
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PSEN/ALE Select (PASEL)
PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 Reset Value
PSEN2-0 bits
PSEN Mode Select. Defines output P3.6 User Application mode Serial Flash Programming mode. 00000: General-purpose (default) 00001: SYSCLK 00011: Internal PSEN (refer Figure timing) 00101: Internal (refer Figure timing) 00111: fOSC (buffered oscillator clock) 01001: Memory (MOVX write) 01011: (overflow)(1) 01101: (overflow)(1) 01111: fMOD(2) 10001: SYSCLK/2 (toggles rising edge)(2) 10011: Internal PSEN/2(2) 10101: Internal ALE/2(2) 10111: fOSC(2) 11001: Memory WR/2 (MOVX write)(2) 11011: Out/2 (overflow)(2) 11101: Out/2 (overflow)(2) 11111: fMOD/2(2)
period these signals equal tCLK. Duty cycle 50%.
Phase Lock Loop Register (PLLL)
PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 Reset Value
PLL7-0 bits
Counter Value Least Significant Bit. Frequency External Crystal Frequency PLL9:0.
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Phase Lock Loop High Register (PLLH)
CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK PLL9 PLL8 Reset Value
CLKSTAT2-0 Active Clock Status (read-only). Derived from HCR2 setting; refer Table bits 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: High-Frequency (HF) Mode (must read PLLLOCK determine active clock status) 101: Low-Frequency (LF) Mode (must read PLLLOCK determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode PLLLOCK Lock Status Status Enable. Write (PLL Lock Status Enable): Effect Enable Lock Detection (must wait 20ms before PLLLOCK read status valid). Read (PLL Lock Status): Locked (PLL inactive; refer Table active clock mode) Locked (PLL active clock). Counter Value Most Significant Bits (refer PLLL, F4h).
PLL9-8 bits
Analog Clock (ACLK)
FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ6-0 bits
Clock Frequency This value divides system clock create clock. fOSC
fACLK fMOD ACLK ACLK where fCLK SYSCLK divider
Data Rate fDATA
Decimation Ratio
System Reset Register (SRST)
RSTREQ Reset Value
RSTREQ
Reset Request. Setting this then clearing will generate system reset.
MSC1201 MSC1202
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Extended Interrupt Priority (EIP)
PWDI Reset Value
PWDI
Watchdog Interrupt Priority. This controls priority watchdog interrupt. watchdog interrupt priority. watchdog interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority.
Seconds Timer Interrupt (SECINT)
SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 Reset Value
This system clock divided value 16-bit register MSECH:MSECL. Then, that timer tick divided register HMSEC which provides 100ms signal used this seconds timer. Therefore, this seconds timer generate interrupt which occurs from 100ms 12.8 seconds. Reading this register will clear Seconds Interrupt. This Interrupt monitored register.
Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. value loaded when current count expires. Write Immediately. counter loaded once completes write operation.
SECINT6-0 Seconds Count. Normal operation would 100ms clock interval. bits Seconds Interrupt SEC) (HMSEC (MSEC tCLK.
MSC1201 MSC1202
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Milliseconds Interrupt (MSINT)
MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 Reset Value
clock used this timer clock which results from dividing system clock values registers MSECH:MSECL. Reading this register necessary clearing interrupt; however, EICON (SFR D8h) must also cleared.
Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. MSINT value loaded when current count expires. Write Immediately. MSINT counter loaded once completes write operation. Milliseconds Count. Normal operation would clock interval. Interrupt Interval MSINT) (MSEC tCLK
MSINT6-0 bits
Microsecond Register (USEC)
FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ5-0 bits
Clock Frequency This value divides system clock create Clock. USEC CLK/(FREQ This clock used Flash write time. FTCON (SFR EFh).
Millisecond Register (MSECL)
MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 Reset Value
MSECL7-0 Millisecond Low. This value combination with next register used create clock. bits (MSECH MSECL tCLK. This clock used Flash erase time. FTCON (SFR EFh).
Millisecond High Register (MSECH)
MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 Reset Value
MSECH7-0 Millisecond High. This value combination with previous register used create clock. bits (MSECH MSECL tCLK.
Hundred Millisecond Register (HMSEC)
HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 Reset Value
Write Control. Determines whether write value immediately wait until current count finished. Read
HMSEC7-0 Hundred Millisecond. This clock divides clock create 100ms clock. bits 100ms (MSECH MSECL (HMSEC tCLK.
MSC1201 MSC1202
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Watchdog Timer Register (WDTCON)
EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 Reset Value
EWDT DWDT RWDT
Enable Watchdog (R/W). Write 1/Write sequence sets Watchdog Enable Counting bit. Disable Watchdog (R/W). Write 1/Write sequence clears Watchdog Enable Counting bit. Reset Watchdog (R/W). Write 1/Write sequence restarts Watchdog Counter.
WDCNT4-0 Watchdog Count (R/W). bits Watchdog expires (WDCNT HMSEC (WDCNT HMSEC, sequence asserted. There uncertainty count. NOTE: HCR0.3 (EWDR) watchdog timer expires, system reset generated. HCR0.3 (EWDR) cleared watchdog timer expires, interrupt generated (see Table
PACKAGE OPTION ADDENDUM
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30-Mar-2005
PACKAGING INFORMATION
Orderable Device MSC1201Y2RHHR MSC1201Y2RHHT MSC1201Y3RHHR MSC1201Y3RHHT MSC1202Y2RHHR MSC1202Y2RHHT MSC1202Y3RHHR MSC1202Y3RHHT
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500 2500 2500 2500
Lead/Ball Finish SNPB SNPB SNPB SNPB SNPB SNPB SNPB SNPB
Peak Temp Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM Level-1-235C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does

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