September 1997 Revised October 2003 High-Speed CMOS Logic 4-Bit B

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

September 1997 Revised October 2003 High-Speed CMOS Logic 4-Bit B

Datasheet Thumbnail

Top Searches for this datasheet

CD54HC194, CD74HC194, CD74HCT194
September 1997 Revised October 2003
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register
Description
'HC194 CD74HCT194 4-bit shift registers with Asynchronous Master Reset (MR). parallel mode high), data loaded into associated flip-flop appears output after positive transition clock input (CP). During parallel loading serial data flow inhibited. Shift left shift right accomplished synchronously positive clock edge with serial data entered shift left (DSL) serial input shift right mode, shift right (DSR) serial input shift left mode. Clearing register accomplished applied Master Reset (MR) pin.
Features /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit
Four Operating Modes Shift Right, Shift Left, Hold Reset Synchronous Parallel Serial Operation Typical fMAX 60MHz 15pF, 25oC Asynchronous Master Reset Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC194F3A CD74HC194E CD74HC194M CD74HC194MT CD74HC194M96 CD74HC194NSR CD74HC194PW CD74HC194PWR TEMP. RANGE (oC) PACKAGE CERDIP PDIP SOIC SOIC SOIC TSSOP TSSOP TSSOP PDIP
Pinout
CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) VIEW
CD74HC194PWT CD74HCT194E
NOTE: When ordering, entire part number. suffixes denote tape reel. suffix denotes small-quantity reel 250.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC194, CD74HC194, CD74HCT194 Functional Diagram
TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Hold Nothing) Shift Left Shift Right Parallel Load (Note (Note (Note (Note (Note (Note OUTPUT
High Voltage Level, High Voltage Level Set-up Time Prior High Clock Transition, Voltage Level, Voltage Level Set-up Time Prior High Clock Transition, (qn) Lower Case Letters Indicate State Referenced Input output) Set-up Time Prior High Clock Transition, Don't Care, Transition from High Level NOTE: High-to-Low transition Inputs 'HC194 CD74HCT194 should take place only while High Conventional Operation.
CD54HC194, CD74HC194, CD74HCT194
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) Package 67oC/W (SOIC) Package. 73oC/W (SOP) Package 64oC/W (TSSOP) Package 108oC/W Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads -0.02 -0.02 -0.02 High Level Output Voltage Loads Level Output Voltage CMOS Loads -5.2 0.02 0.02 0.02 Level Output Voltage Loads 3.15 3.98 5.48 1.35 0.26 0.26 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC194, CD74HC194, CD74HCT194
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 SYMBOL (mA) 25oC ±0.1 -40oC 85oC -55oC 125oC UNITS
-0.02
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT DSL, DSR, UNIT LOADS 0.55 0.25 1.10
NOTE: Unit Load limit specified Electrical Specifications table, e.g. 360µA 25oC.
CD54HC194, CD74HC194, CD74HCT194
Prerequisite Switching Function
25oC PARAMETER TYPES Max. Clock Frequency (Figure fMAX Pulse Width (Figure Clock Pulse Width (Figure Set-up Time Data Clock (Figure Removal Time, Clock (Figure tREM Set-Up Time Clock (Figure Set-up Time DSL, Clock (Figure Hold Time Clock (Figure Hold Time Data Clock (Figure TYPES Max. Clock Frequency (Figure Pulse Width (Figure Clock Pulse Width (Figure Set-up Time, Data Clock (Figure Removal Time Clock (Figure fMAX tREM SYMBOL TEST CONDITIONS -40oC 85oC -55oC 125oC UNITS
Prerequisite Switching Function
(Continued) 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER Set-up Time Clock (Figure Set-up Time DSL, Clock (Figure Hold Time Clock (Figure Hold Time Data Clock (Figure
SYMBOL
TEST CONDITIONS
Switching Specifications
PARAMETER TYPES Propagation Delay, Clock Output (Figure
Input TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
SYMBOL
tPLH, tPHL
50pF
Propagation Delay, Clock Output Transition Time (Figure
tPLH, tPHL tTLH, tTHL
50pF
Propagation Delay, Output (Figure
tPHL
50pF
Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes TYPES Propagation Delay, Clock Output (Figure Propagation Delay, Clock Output Transition Times (Figure Propagation Delay, Output (Figure Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes NOTES:
fMAX
tPLH, tPHL tPLH, tPHL tTLH, tTHL tPHL fMAX
50pF 50pF 50pF
used determine dynamic power consumption, gate. VCC2 VCC2) where Input Frequency, Output Load Capacitance, Supply Voltage.
Test Circuits Waveforms
INPUT LEVEL tPHL tTHL tTLH tPLH tREM tPHL INPUT LEVEL INPUT LEVEL
FIGURE CLOCK PREREQUISITE TIMES PROPAGATION OUTPUT TRANSITION TIMES
FIGURE MASTER RESET PREREQUISITE TIMES PROPAGATION DELAYS
VALID INPUT LEVEL DATA INPUT LEVEL
VALID INPUT LEVEL INPUT LEVEL
FIGURE DATA PREREQUISITE TIMES
FIGURE PARALLEL LOAD SHIFT-LEFT/SHIFT-RIGHT PREREQUISITE TIMES
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

September 1997 Revised October 2003 High-Speed CMOS Logic 4-Bit B

Top Searches for this datasheet

Other recent searches