15-V Digital ±7.5-V Peak-to-Peak Switching 125- Typical On-State Resis

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15-V Digital ±7.5-V Peak-to-Peak Switching 125- Typical On-State Resis

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CD4066B CMOS QUAD BILATERAL SWITCH
15-V Digital ±7.5-V Peak-to-Peak Switching 125- Typical On-State Resistance 15-V Operation Switch On-State Resistance Matched Within Over 15-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: Typical kHz, High Degree Linearity: <0.5% Distortion Typical kHz, p-p, Extremely Off-State Switch Leakage, Resulting Very Offset Current High Effective Off-State Resistance: Typical 25°C Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 1012 Typical Crosstalk Between Switches: Typical MHz,
Matched Control-Input Signal-Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch Typical 100% Tested Quiescent Current 5-V, 10-V, 15-V Parametric Ratings Meets Requirements JEDEC Tentative Standard 13-B, Standard Specifications Description Series CMOS Devices Applications: Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch Digital Signal Switching/Multiplexing Transmission-Gate Logic Implementation Analog-to-Digital Digital-to-Analog Conversion Digital Control Frequency, Impedance, Phase, Analog-Signal Gain
PACKAGE (TOP VIEW)
IN/OUT OUT/IN OUT/IN IN/OUT CONTROL CONTROL
CONTROL CONTROL IN/OUT OUT/IN OUT/IN IN/OUT
description/ordering information
CD4066B quad bilateral switch intended transmission multiplexing analog digital signals. pin-for-pin compatible with CD4016B, exhibits much lower on-state resistance. addition, on-state resistance relatively constant over full signal-input range. CD4066B consists four bilateral switches, each with independent controls. Both devices given switch biased simultaneously control signal. shown Figure well n-channel device each switch tied either input (when switch (when switch off). This configuration eliminates variation switch-transistor threshold voltage with input signal and, thus, keeps on-state resistance over full operating-signal range. advantages over single-channel switches include peak input-signal voltage swings equal full supply voltage more constant on-state impedance over input-signal range. However, sample-and-hold applications, CD4016B recommended.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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description/ordering information (continued)
ORDERING INFORMATION
CDIP PDIP SOIC TSSOP PACKAGE Tube Tube Tube -55°C 125°C Reel 2500 Reel Reel 2000 Tube Reel 2000 ORDERABLE PART NUMBER CD4066BF3A CD4066BE CD4066BM CD4066BM96 CD4066BMT CD4066BNSR CD4066BPW CD4066BPWR CD4066B CM066B CD4066BM TOP-SIDE MARKING CD4066BF3A CD4066BE
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Switch Control
Control
control inputs protected CMOS protection network. NOTES: substrates connected VDD. Normal operation control-line biasing: switch (logic VDD; switch (logic Signal-level range:
92CS-29113
Figure Schematic Diagram One-of-Four Identical Switches Associated Control Circuitry
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CD4066B CMOS QUAD BILATERAL SWITCH
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
supply-voltage range, (voltages referenced terminal) -0.5 Input voltage range, (all inputs) -0.5 input current, (any input) Package thermal impedance, (see Note package 80°C/W package 86°C/W package 76°C/W package 113°C/W Lead temperature (during soldering): distance 1/16 1/32 inch (1,59 0,79 from case 265°C Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE package thermal impedance calculated accordance with JESD 51-7.
recommended operating conditions
Supply voltage Operating free-air temperature UNIT
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electrical characteristics
LIMITS INDICATED TEMPERATURES PARAMETER TEST CONDITIONS Quiescent device current Signal Inputs (Vis) Outputs (Vos) VDD, returned On-state resistance difference between switches Total harmonic distortion -3-dB cutoff frequency (switch -50-dB feedthrough frequency (switch off) Input/output leakage current (switch off) (max) -50-dB crosstalk frequency Vis(p-p) (sine wave centered 1-kHz sine wave Vis(p-p) (sine wave centered Vis(p-p) (sine wave centered VC(A) VC(B) Vis(A) Vp-p, source, VDD, GND, (square wave centered ±0.1 ±0.1 1200 1300 1050 -55°C 0.25 -40°C 0.25 85°C 125°C 25°C 0.01 0.01 0.01 0.02 0.25 UNIT
On-state resistance (max)
±10-5 ±0.1
Propagation delay (signal input signal output) Input capacitance Output capacitance Feedthrough
Cios
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CD4066B CMOS QUAD BILATERAL SWITCH
electrical characteristics (continued)
LIMITS INDICATED TEMPERATURES CHARACTERISTIC Control (VC) VILC Control input, voltage (max) |Iis| VSS, VDD, VDD, VIHC Control input, high voltage Input current (max) Crosstalk (control input signal output) Turn-on turn-off propagation delay Figure VDD, (square wave), VDD, VDD, GND, GND, (square wave centered ±0.1 ±0.1 (MIN) (MIN) (MIN) ±10-5 ±0.1 TEST CONDITIONS -55°C -40°C 85°C 125°C 25°C UNIT
Maximum control input repetition rate
Input capacitance
switching characteristics
SWITCH INPUT (mA) -55°C 0.64 -0.64 -1.6 -4.2 -40°C 0.61 -0.61 -1.5 25°C 0.51 -0.51 -1.3 -3.4 85°C 0.42 -0.42 -1.1 -2.8 125°C 0.36 -0.36 -0.9 -2.4 13.5 SWITCH OUTPUT,
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TYPICAL CHARACTERISTICS
TYPICAL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
Channel On-State Resistance +25°C -55°C Supply Voltage (VDD VSS) 125°C Channel On-State Resistance +25°C -55°C -7.5 -2.5
TYPICAL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (VDD VSS) 125°C
Input Signal Voltage
92CS-27326RI
Input Signal Voltage
92CS-27327RI
Figure
TYPICAL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
Channel On-State Resistance Channel On-State Resistance Supply Voltage (VDD VSS) 125°C -7.5 -2.5 Input Signal Voltage
92CS-27329RI
Figure
TYPICAL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
125°C -7.5 -2.5 Supply Voltage (VDD VSS)
+25°C -55°C
Input Signal Voltage
92CS-27330RI
Figure
Figure
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CD4066B CMOS QUAD BILATERAL SWITCH
TYPICAL CHARACTERISTICS
CD4066B Switches |Vis Vos| |Iis|
92CS-30966
Figure Determination Test Condition Control-Input High-Voltage (VIHC) Specification
Keithley Digital Multimeter Range
Plotter Moseley 7030A
92CS-22716
Figure Channel On-State Resistance Measurement Circuit
POWER DISSIPATION PACKAGE SWITCHING FREQUENCY
Power Dissipation Package
TYPICAL CHARACTERISTICS CHANNELS
25°C
Output Voltage
Supply Voltage (VDD)
CD4066B
CD4066B Switches
unused terminals connected
Input Voltage
92CS-30919
Switching Frequency
Figure
Figure
92C-30920
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CD4066B CMOS QUAD BILATERAL SWITCH
TYPICAL CHARACTERISTICS
Cios
CD4066B Switches
92CS-30922
CD4066B Switches
92CS-30921
Measured Boonton capacitance bridge, model MHz); test-fixture capacitance nulled out.
unused terminals connected VSS.
Figure Typical Characteristics Four Channels
CD4066B Switches
92CS-30923
Figure Off-Switch Input Output Leakage
CD4066B Switches
92CS-30924
unused terminals connected VSS.
unused terminals connected VSS.
Figure Propagation Delay Time Signal Input (Vis) Signal Output (Vos)
Figure Crosstalk-Control Input Signal Output
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CD4066B CMOS QUAD BILATERAL SWITCH
TYPICAL CHARACTERISTICS
CD4066B Switches
NOTES: unused terminals connected VSS. Delay measured level +10% from ground (turn-on) on-state output level (turn-off).
92CS-30925
Figure Propagation Delay, tPLH, tPHL Control-Signal Output
Repetition Rate
CD4066B Switches
unused terminals connected VSS.
92CS-30925
Figure Maximum Allowable Control-Input Repetition Rate
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CD4066B CMOS QUAD BILATERAL SWITCH
TYPICAL CHARACTERISTICS
Inputs
92CS-27555
Measure inputs sequentially both VSS. Connect unused inputs either VSS. Measure control inputs only.
Figure Input Leakage-Current Test Circuit
Clock Reset External Reset Clock
CD4018B
CD4018B
CD4066B
CD4049B Signal Inputs CD4049B CD4001B CD4049B
CD4001B
Signal Outputs
Channel
Channel Channel Channel Channel
CD4066B
Channel
CD4066B
CD4066B
Package Count CD4001B CD4049B CD4066B CD4018B
Channel
Maximum Allowable Signal Level
Clock
(VDD VSS) Chan Chan Chan Chan
Channel
92CM-30928
Figure Four-Channel Multiplex System Diagram
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CD4066B CMOS QUAD BILATERAL SWITCH
TYPICAL CHARACTERISTICS
CD4054B CD4066B Digital Control Inputs
92CS-30927
Analog Inputs
Analog Outputs
Figure Bidirectional Signal Transmission Digital Control Logic
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CD4066B CMOS QUAD BILATERAL SWITCH
APPLICATION INFORMATION
applications that employ separate power sources drive signal inputs, current capability should exceed VDD/RL effective external load four CD4066B bilateral switches). This provision avoids permanent current flow clamp action supply when power applied removed from CD4066B. certain applications, external load-resistor current include both signal-line components. avoid drawing current when switch current flows into terminals voltage drop across bidirectional switch must exceed (calculated from values shown). current will flow through switch current flows into terminals
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MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
(R-PDIP-T**)
PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS
0.775 (19,69) 0.745 (18,92)
0.775 (19,69) 0.745 (18,92)
0.920 (23,37) 0.850 (21,59)
1.060 (26,92) 0.940 (23,88)
0.260 (6,60) 0.240 (6,10)
MS-100 VARIATION
0.070 (1,78) 0.045 (1,14)
0.045 (1,14) 0.030 (0,76)
0.020 (0,51)
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.010 (0,25) Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
0.430 (10,92)
14/18 ONLY vendor option
4040049/E 12/2002
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001, except minimum body lrngth (Dim lead shoulder width vendor option, either half full width.
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MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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15-V Digital ±7.5-V Peak-to-Peak Switching 125- Typical On-State Resis

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