16-Bit, High-Speed, 2.7V microPower Sampling ANALOG-TO-DIGITAL CONVERT
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ADS8320
16-Bit, High-Speed, 2.7V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
100kHz SAMPLING RATE MICRO POWER: 1.8mW 100kHz 2.7V 0.3mW 10kHz 2.7V POWER DOWN: MSOP-8 PACKAGE PIN-COMPATIBLE ADS7816 ADS7822 SERIAL (SPI/SSI) INTERFACE
DESCRIPTION
ADS8320 16-bit sampling analog-to-digital converter (A/D) with guaranteed specifications over 2.7V 5.25V supply range. requires very little power even when operating full 100kHz data rate. lower data rates, high speed device enables spend most time power-down mode-the average power dissipation less than 100µW 10kHz data rate. ADS8320 also features operation from 2.0V 5.25V, synchronous serial (SPI/SSI compatible) interface, differential input. reference voltage level within range 500mV VCC. Ultra-low power small size make ADS8320 ideal portable battery-operated systems. also perfect remote data acquisition modules, simultaneous multi-channel systems, isolated data acquisition. ADS8320 available MSOP-8 package.
APPLICATIONS
BATTERY OPERATED SYSTEMS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION SIMULTANEOUS SAMPLING, MULTI-CHANNEL SYSTEMS INDUSTRIAL CONTROLS ROBOTICS VIBRATION ANALYSIS
Control
VREF
DOUT CDAC Comparator Serial Interface DCLOCK CS/SHDN
International Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1999 Burr-Brown Corporation
PDS-1504C
Printed U.S.A. May, 2000
SBAS108
SPECIFICATIONS: +VCC
-40°C +85°C, VREF +5V,-IN GND, fSAMPLE 100kHz, fCLK fSAMPLE, unless otherwise specified. ADS8320E PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Missing Codes Integral Linearity Error Offset Error Offset Temperature Drift Gain Error Gain Temperature Drift Noise Power Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range REFERENCE INPUT Voltage Range Resistance Current Drain fSAMPLE 10kHz DIGITAL INPUT/OUTPUT Logic Family Logic Levels: Data Format POWER SUPPLY REQUIREMENTS Range(2) Quiescent Current Power Dissipation Power Down TEMPERATURE RANGE Specified Performance Specifications same ADS8320E. NOTES: means Least Significant Bit. Typical Performance Curves more information. 2.4MHz, clock cycles every 240. Power Dissipation section more information regarding lower sample rates. 5Vp-p 10kHz 5Vp-p 10kHz 5Vp-p 10kHz ±0.008 ±0.3 0.024 GND, fSAMPLE CMOS +5µA +5µA -250µA 250µA -0.3 Straight Binary Specified Performance 4.75 5.25 5.25 1700 ±0.018 ±0.05 (-In) -0.1 -0.1 ±0.006 ±0.5 ±0.012 ±0.024 CONDITIONS VREF +1.0 ADS8320EB UNITS Bits Bits µV/°C ppm/°C µVrms LSB(1) Cycles Cycles
+4.7V 5.25V
fSAMPLE 10kHz(3,
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
ADS8320
SPECIFICATIONS: +VCC +2.7V
-40°C +85°C, VREF 2.5V, GND, fSAMPLE 100kHz, fCLK fSAMPLE, unless otherwise specified. ADS8320E PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Missing Codes Integral Linearity Error Offset Error Offset Temperature Drift Gain Error Gain Temperature Drift Noise Power Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range REFERENCE INPUT Voltage Range Resistance Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: Data Format POWER SUPPLY REQUIREMENTS Range(3) Quiescent Current fSAMPLE 10kHz(4,5) Power Dissipation Power Down TEMPERATURE RANGE Specified Performance Specifications same ADS8320E. Notes: means Least Significant Bit. With VREF equal +5V, 0.039mV. maximum clock rate ADS8320 less than 2.4MHz this power supply range. Typical Performance Curves more information. 2.4MHz, clock cycles every 240. Power Dissipation section more information regarding lower sample rates. 2.7Vp-p 1kHz 2.7Vp-p 1kHz 2.7Vp-p 1kHz ±0.008 ±0.3 0.024 GND, fSAMPLE CMOS +5µA +5µA -250µA 250µA -0.3 Straight Binary Specified Performance Note 5.25 1300 ±0.018 ±0.05 (-In) -0.1 -0.1 ±0.006 ±0.5 CONDITIONS VREF +0.5 ADS8320EB UNITS Bits
±0.012
+2.7V +3.3V
Bits µV/°C ±0.024 ppm/°C µVrms LSB(1) Cycles Cycles
ADS8320
CONFIGURATION
View MSOP
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge cause damage ranging from performance degradation complete device failure. BurrBrown Corporation recommends that integrated circuits handled stored using appropriate protection methods. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
VREF
ADS8320
+VCC DCLOCK DOUT CS/SHDN
ASSIGNMENTS
NAME VREF CS/SHDN DOUT DESCRIPTION Reference Input. Inverting Input. Inverting Input. Connect ground remote ground sense point. Ground. Chip Select when LOW, Shutdown Mode when HIGH. serial output data word comprised bits data. operation data valid falling edge DCLOCK. second clock pulse after falling edge enables serial output. After null data valid next edges. Data Clock synchronizes serial data transfer determines conversion speed. Power Supply. Analog Input -0.3V (VCC 0.3V) Logic Input -0.3V Case Temperature +100°C Junction Temperature +150°C Storage Temperature +125°C External Reference Voltage +5.5V NOTE: Stresses above these ratings permanently damage device.
ABSOLUTE MAXIMUM RATINGS(1)
DCLOCK +VCC
PACKAGE/ORDERING INFORMATION
MAXIMUM INTEGRAL LINEARITY ERROR 0.018 MISSING CODE ERROR (LSB)
PRODUCT ADS8320E ADS8320E ADS8320EB ADS8320EB
PACKAGE MSOP-8
PACKAGE DRAWING NUMBER(1)
SPECIFICATION TEMPERATURE RANGE -40°C +85°C
PACKAGE MARKING(2)
ORDERING NUMBER(3) ADS8320E/250 ADS8320E/2K5 ADS8320EB/250 ADS8320EB/2K5
TRANSPORT MEDIA Tape Tape Tape Tape Reel Reel Reel Reel
0.012
MSOP-8
-40°C +85°C
NOTE: detail drawing dimension table, please data sheet Package Drawing File Web. Performance Grade information marked reel. Models with slash(/) available only Tape reel quantities indicated (e.g. /250 indicates units reel, /2K5 indicates 2500 devices reel). Ordering 2500 pieces "ADS8320E/2K5" will single 2500-piece Tape Reel. detailed Tape Reel mechanical information, refer www.burr-brown.com site under Applications Tape Reel Orientation Dimensions.
ADS8320
TYPICAL PERFORMANCE CURVES
+25°C, +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE, unless otherwise specified.
INTEGRAL LINEARITY ERROR CODE (+25°C)
Differential Linearity Error (LSB)
Integral Linearity Error (LSB)
DIFFERENTIAL LINEARITY ERROR CODE (+25°C) -1.0 -2.0 -3.0 0000H
-1.0 -2.0 -3.0 -4.0 -5.0 -6.0 0000H
4000H
8000H Code
C000H
FFFFH
4000H
8000H Code
C000H
FFFFH
SUPPLY CURRENT TEMPERATURE 1200 1000
POWER DOWN SUPPLY CURRENT TEMPERATURE
Supply Current (µA)
2.7V Temperature (°C)
Supply Current (nA)
Temperature (°C)
QUIESCENT CURRENT 1200 1000
MAXIMUM SAMPLE RATE
Quiescent Current (µA)
1000
Sample Rate (kHz)
ADS8320
TYPICAL PERFORMANCE CURVES (Cont.)
+25°C, +2.7V, VREF +2.5V, fSAMPLE 100kHz, fCLK fSAMPLE, unless otherwise specified.
CHANGE OFFSET REFERENCE VOLTAGE
Change Offset (LSB)
CHANGE OFFSET TEMPERATURE
Reference Voltage
Delta from 25°C (LSB)
Temperature (°C) 2.7V
CHANGE GAIN REFERENCE VOLTAGE
Change Gain (LSB)
CHANGE GAIN TEMPERATURE
Reference Voltage
Delta from 25°C (LSB)
Temperature (°C) 2.7V
FREQUENCY SPECTRUM (8192 Point FFT, 10.120kHz, -0.3dB)
PEAK-TO-PEAK NOISE REFERENCE VOLTAGE
Peak-to-Peak Noise (LSB)
Amplitude (dB)
-100 -120 -140 Frequency (kHz)
Reference Voltage
ADS8320
TYPICAL PERFORMANCE CURVES (Cont.)
+25°C, +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE, unless otherwise specified.
SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO FREQUENCY Frequency (kHz) Spurious Free Dynamic Range Signal-to-Noise Ratio
Total Harmonic Distortion (dB)
-100
TOTAL HARMONIC DISTORTION FREQUENCY
Spurious Free Dynamic Range Signal-to-Noise Ratio (dB)
Frequency (kHz)
SIGNAL-TO-(NOISE DISTORTION) FREQUENCY
SIGNAL-TO-(NOISE DISTORTION) INPUT LEVEL
Signal-to-(Noise Distortion) (dB)
Frequency (kHz)
Signal-to-(Noise Distortion) (dB)
Input Level (dB)
REFERENCE CURRENT SAMPLE RATE
REFERENCE CURRENT TEMPERATURE
Reference Current (µA)
Sample Rate (kHz)
Reference Current (µA)
2.7V
2.7V
Temperature (°C)
ADS8320
THEORY OPERATION
ADS8320 classic successive approximation register (SAR) analog-to-digital (A/D) converter. architecture based capacitive redistribution which inherently includes sample/hold function. converter fabricated 0.6µ CMOS process. architecture process allow ADS8320 acquire convert analog signal 100,000 conversions second while consuming less than 4.5mW from +VCC. ADS8320 requires external reference, external clock, single power source (VCC). external reference voltage between 500mV VCC. value reference voltage directly sets range analog input. reference input current depends conversion rate ADS8320. external clock vary between 24kHz (1kHz throughput) 2.4MHz (100kHz throughput). duty cycle clock essentially unimportant long minimum high times least 200ns (VCC 2.7V greater). minimum clock frequency leakage capacitors internal ADS8320. analog input provided input pins: -In. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function. digital result conversion clocked DCLOCK input provided serially, most significant first, DOUT pin. digital data that provided DOUT conversion currently progress-there pipeline delay. possible continue clock ADS8320 after conversion complete obtain serial data least significant first. digital timing section more information.
riod. After this capacitance been fully charged, there further input current. source analog input voltage must able charge input capacitance (45pF) 16-bit settling level within clock cycles. When converter goes into hold mode while powerdown mode, input impedance greater than Care must taken regarding absolute analog input voltage. maintain linearity converter, input should drop below 100mV exceed input should always remain within range 100mV 100mV. Outside these ranges, converter's linearity meet specifications. minimize noise, bandwidth input signals with lowpass filters should used.
REFERENCE INPUT
external reference sets analog input range. ADS8320 will operate with reference range 500mV VCC. There several important implications this. reference voltage reduced, analog voltage weight each digital output code reduced. This often referred Least Significant (LSB) size equal reference voltage divided 65,536. This means that offset gain error inherent converter will appear increase, terms size, reference voltage reduced. noise inherent converter will also appear increase with lower size. With reference, internal noise converter typically contributes only peak-to-peak potential error output code. When external reference 500mV, potential error contribution from internal noise will times larger- LSBs. errors internal noise gaussian nature reduced averaging consecutive conversion results. more information regarding noise, consult typical performance curve "Peak-to-Peak Noise Reference Voltage." Note that Effective Number Bits (ENOB) figure calculated based converter's signal-to-(noise distortion) ratio with 1kHz, input signal. SINAD related ENOB follows: SINAD 6.02 ENOB 1.76 With lower reference voltages, extra care should taken provide clean layout including adequate bypassing, clean power supply, low-noise reference, low-noise input signal. Because size lower, converter will also more sensitive external sources error such nearby digital signals electromagnetic interference.
ANALOG INPUT
input pins allow differential input signal. Unlike some converters this type, input re-sampled later conversion cycle. When converter goes into hold mode, voltage difference between captured internal capacitor array. range input limited -0.1V (-0.1V +0.5V when using 2.7V supply). Because this, differential input used reject only small signals that common both inputs. Thus, input best used sense remote signal ground that move slightly with respect local ground potential. input current analog inputs depends number factors: sample rate, input voltage, source impedance, power-down mode. Essentially, current into ADS8320 charges internal capacitor array during sample
ADS8320
NOISE noise floor ADS8320 itself extremely low, seen from Figures much lower than competing converters. tested applying noise input 5.0V reference ADS8320 initiating 5000 conversions. digital output
2510
2490
converter will vary output code internal noise ADS8320. This true 16-bit SAR-type converters. Using histogram plot output codes, distribution should appear bell-shaped with peak bell curve representing nominal code input value. distributions will represent 68.3%, 95.5%, 99.7%, respectively, codes. transition noise calculated dividing number codes measured this will yield distribution 99.7% codes. Statistically, codes could fall outside distribution when executing 1000 conversions. ADS8320, with output codes distribution, will yield ±0.5LSB transition noise. Remember, achieve this noise performance, peak-to-peak noise input signal reference must 50µV. AVERAGING noise converter compensated averaging digital codes. averaging conversion results, transition noise will reduced factor 1/n, where number averages. example, averaging conversion results will reduce transition noise ±0.25 LSBs. Averaging should only used input signals with frequencies near signals, digital filter used pass filter decimate output codes. This works similar manner averaging; every decimation signalto-noise ratio will improve 3dB.
Code
FIGURE Histogram 5000 Conversions Input Code Transition.
4864
DIGITAL INTERFACE
SIGNAL LEVELS digital inputs ADS8320 accommodate logic levels 5.5V regardless value VCC. Thus, ADS8320 powered still accept inputs from logic powered
Code
CMOS digital output (DOUT) will swing VCC. this output connected CMOS logic input, then that require more supply current than normal have slightly longer propagation delay.
FIGURE Histogram 5000 Conversions Input Code Center.
ADS8320
SERIAL INTERFACE ADS8320 communicates with microprocessors other digital systems synchronous 3-wire serial interface shown Figure Table DCLOCK signal synchronizes data transfer with each being transmitted falling edge DCLOCK. Most receiving systems will capture bitstream rising edge DCLOCK. However, minimum hold time DOUT acceptable, system falling edge DCLOCK capture each bit. falling signal initiates conversion data transfer. first clock periods conversion cycle used sample input signal. After fifth falling DCLOCK edge, DOUT enabled will output value clock period. next DCLOCK periods, DOUT will output conversion result, most significant first. After least significant (B0) been output, subsequent clocks will repeat output data least significant first format. After most significant (B15) been repeated, DOUT will tri-state. Subsequent clocks will have effect converter. conversion initiated only when been taken HIGH returned LOW.
SYMBOL SMPL CONV SUCS DESCRIPTION Analog Input Sample Time Conversion Time Throughput Rate Falling DCLOCK Falling DCLOCK Rising DCLOCK Falling Current DOUT Valid DCLOCK Falling Next DOUT Valid Rising DOUT Tri-State DCLOCK Falling DOUT Enabled DOUT Fall Time DOUT Rise Time UNITS Cycles Cycles
DATA FORMAT output data from ADS8320 Straight Binary format shown Table This table represents ideal output code given input voltage does include effects offset, gain error, noise.
DESCRIPTION Full Scale Range Least Significant (LSB) Full Scale Midscale Midscale 1LSB Zero ANALOG VALUE VREF VREF/65,536 BINARY CODE VREF VREF/2 VREF/2 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 CODE FFFF 8000 7FFF 0000
DIGITAL OUTPUT STRAIGHT BINARY
TABLE Ideal Input Voltages Output Codes.
POWER DISSIPATION
architecture converter, semiconductor fabrication process, careful design allow ADS8320 convert 100kHz rate while requiring very little power. Still, absolute lowest power dissipation, there several things keep mind. power dissipation ADS8320 scales directly with conversion rate. Therefore, first step achieving lowest power dissipation find lowest conversion rate that will satisfy requirements system. addition, ADS8320 power down mode under conditions: when conversion complete whenever HIGH (see Figure Ideally, each conversion should occur quickly possible, preferably 2.4MHz clock rate. This way, converter spends longest possible time power-down mode. This very important converter only uses power each DCLOCK transition typical digital CMOS components) also uses some current analog circuitry, such comparator. analog section dissipates power continuously, until power down mode entered.
TABLE Timing Specifications (VCC 2.7V above, -40°C +85°C.
Complete Cycle CS/SHDN tSUCS Sample DCLOCK tCSD DOUT Hi-Z tSMPL (MSB) tCONV (LSB) positive clock edge data transfer Hi-Z Conversion Power Down
NOTE: Minimum clock cycles required 16-bit conversion. Shown clock cycles. remains conversion, datastream with LSB-first shifted again.
FIGURE ADS8320 Basic Timing Diagrams.
ADS8320
1.4V
DOUT 100pF CLOAD Test Point
DOUT
Voltage Waveforms DOUT Rise Fall Times, Load Circuit tdDO,
Test Point DCLOCK tdDO DOUT thDO Voltage Waveforms DOUT Delay Times, tdDO DOUT 100pF CLOAD Load Circuit tdis tdis Waveform tdis Waveform
CS/SHDN
CS/SHDN DCLOCK
DOUT Waveform 1(1) tdis DOUT Waveform 2(2) Voltage Waveforms tdis
DOUT Voltage Waveforms
NOTES: Waveform output with internal conditions such that output HIGH unless disabled output control. Waveform output with internal conditions such that output unless disabled output control.
FIGURE Timing Diagrams Test Circuits Parameters Table
ADS8320
1000 25°C fCLK 2.4MHz
Supply Current (µA)
5.0V VREF 5.0V 2.7V VREF 2.5V
Figure shows current consumption ADS8320 versus sample rate. this graph, converter clocked 2.4MHz regardless sample rate-CS HIGH remaining sample period. Figure also shows current consumption versus sample rate. However, this case, DCLOCK period 1/24th sample period-CS HIGH DCLOCK cycle every There important distinction between power-down mode that entered after conversion complete full power-down mode which enabled when HIGH. will shut down only analog section. digital section completely shutdown only when HIGH. Thus, left conversion converter continually clocked, power consumption will when HIGH. Figure more information. Power dissipation also reduced lowering power supply voltage reference voltage. ADS8320 will operate over range 2.0V 5.25V. However, voltages below 2.7V, converter will 100kHz sample rate. typical performance curves more information regarding power supply voltage maximum sample rate. SHORT CYCLING Another saving power utilize signal short cycle conversion. Because ADS8320 places latest data DOUT line generated, converter easily short cycled. This term means that conversion terminated time. example, only bits conversion result needed, then conversion terminated pulling HIGH) after 14th been clocked out. This technique used lower power dissipation increase conversion rate) those applications where analog signal being monitored until some condition becomes true. example, signal outside predetermined range, full 16-bit conversion result needed. conversion terminated after first bits, where might This results lower power dissipation both converter rest system, they spend more time power-down mode.
Sample Rate (kHz)
FIGURE Maintaining fCLK Highest Possible Rate Allows Supply Current Drop Linearly with Sample Rate.
1000
Supply Current (µA)
25°C 5.0V VREF 5.0V fCLK fSAMPLE
Sample Rate (kHz)
FIGURE Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate.
1000 25°C 5.0V VREF 5.0V fCLK fSAMPLE
Supply Current (µA)
0.250 0.00
(GND)
LAYOUT
optimum performance, care should taken with physical layout ADS8320 circuitry. This will particularly true reference voltage and/or conversion rate high. 100kHz conversion rate, ADS8320 makes decision every 416ns. That each subsequent decision, digital output must updated with results last decision, capacitor array appropriately switched charged, input comparator settled 16-bit level within clock cycle.
HIGH (VCC)
Sample Rate (kHz)
FIGURE Shutdown Current with HIGH 50nA Typically, Regardless Clock. Shutdown Current with Varies with Sample Rate.
ADS8320
basic architecture sensitive spikes power supply, reference, ground connections that occur just prior latching comparator output. Thus, during single conversion n-bit converter, there "windows" which large external transient voltages easily affect conversion result. Such spikes might originate from switching power supplies, digital logic, high power devices, name few. This particular source error very difficult track down glitch almost synchronous converter's DCLOCK signal-as phase difference between changes with time temperature, causing sporadic misoperation. With this mind, power ADS8320 should clean well bypassed. 0.1µF ceramic bypass capacitor should placed close ADS8320 package possible. addition, 10µF capacitor series resistor used lowpass filter noisy supply. reference should similarly bypassed with 0.1µF capacitor. Again, series resistor large capacitor used lowpass filter reference voltage. reference voltage originates from amp, careful that drive bypass capacitor without oscillation (the series resistor help this case). Keep mind that while ADS8320 draws very little current from reference average, there still instantaneous current demands placed external input reference circuitry. Burr-Brown's OPA627 provides optimum performance buffering both signal reference inputs. cost, voltage, single-supply applications, OPA2350 OPA2340 dual amps recommended.
Also, keep mind that ADS8320 offers inherent rejection noise voltage variation regards reference input. This particular concern when reference input tied power supply. noise ripple from supply will appear directly digital results. While high frequency noise filtered described previous paragraph, voltage variation line frequency (50Hz 60Hz), difficult remove. ADS8320 should placed clean ground point. many cases, this will "analog" ground. Avoid connecting close grounding point microprocessor, microcontroller, digital signal processor. needed, ground trace directly from converter power supply connection point. ideal layout will include analog ground plane converter associated analog circuitry.
APPLICATION CIRCUITS
Figure shows basic data acquisition system. ADS8320 input range VCC, reference input connected directly power supply. resistor 10µF capacitor filter microcontroller "noise" supply, well high-frequency noise from supply itself. exact values should picked such that filter provides adequate rejection noise.
+2.7V +5.25V 10µF ADS8320 VREF 0.1µF DOUT DCLOCK 10µF Microcontroller
FIGURE Basic Data Acquisition System.
ADS8320
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE ADS8320E/250 ADS8320E/2K5 ADS8320EB/250 ADS8320EB/2K5 STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE VSSOP VSSOP VSSOP VSSOP PACKAGE DRAWING PINS PACKAGE 2500 2500
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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