8-BIT WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI,
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ST7DALI
8-BIT WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI
Memories Kbytes single voltage Flash Program memory with read-out protection, In-Circuit Programming In-Application programming (ICP IAP). write/erase cycles guaranteed, data retention: years 55°C. bytes bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: years 55°C. Clock, Reset Supply Management Enhanced reset system Enhanced voltage supervisor (LVD) main supply auxiliary voltage detector (AVD) with interrupt capability implementing safe power-down procedures Clock sources: Internal oscillator, crystal/ceramic resonator external clock Internal 32-MHz input clock Auto-reload timer Optional internal clock Five Power Saving Modes: Halt, Active-Halt, Wait Slow, Auto Wake From Halt Ports multifunctional bidirectional lines high sink outputs Timers Configurable Watchdog Timer 8-bit Lite Timers with prescaler, watchdog, realtime base input capture 12-bit Auto-reload Timer with Device Summary
SO20 300" outputs, input capture output compare functions Communication Interfaces synchronous serial interface DALI communication interface Interrupt Management interrupt vectors plus TRAP RESET external interrupt lines vectors) Converter input channels Fixed gain Op-amp 13-bit resolution VDD) 10-bit resolution VDD) Instruction 8-bit data manipulation basic instructions main addressing modes unsigned multiply instructions Development Tools Full hardware/software development package (Debug module)
Features Program memory bytes (stack) bytes Data EEPROM bytes Peripherals Operating Supply Frequency Operating Temperature Package
ST7DALI (128) Lite Timer with Watchdog, Autoreload Timer with 32-MHz input clock, SPI, 10-bit with Op-Amp, DALI 2.4V 5.5V 8Mhz 16MHz 1MHz PLLx8/4MHz) -40°C +85°C SO20 300"
Rev.
August 2003 1/140
Table Content1 INTRODUCTION DESCRIPTION REGISTER MEMORY FLASH PROGRAM MEMORY INTRODUCTION MAIN FEATURES PROGRAMMING MODES INTERFACE MEMORY PROTECTION RELATED DOCUMENTATION REGISTER DESCRIPTION
DATA EEPROM INTRODUCTION MAIN FEATURES MEMORY ACCESS POWER SAVING MODES ACCESS ERROR HANDLING DATA EEPROM READ-OUT PROTECTION REGISTER DESCRIPTION
CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
SUPPLY, RESET CLOCK MANAGEMENT INTERNAL OSCILLATOR ADJUSTMENT PHASE LOCKED LOOP REGISTER DESCRIPTION MULTI-OSCILLATOR (MO) RESET SEQUENCE MANAGER (RSM) SYSTEM INTEGRITY MANAGEMENT (SI)
INTERRUPTS MASKABLE SOFTWARE INTERRUPT EXTERNAL INTERRUPTS PERIPHERAL INTERRUPTS
POWER SAVING MODES INTRODUCTION SLOW MODE WAIT MODE HALT MODE ACTIVE-HALT MODE AUTO WAKE FROM HALT MODE
PORTS
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Table Content10.1 INTRODUCTION 10.2 FUNCTIONAL DESCRIPTION 10.3 PORT IMPLEMENTATION 10.4 UNUSED PINS 10.5 POWER MODES 10.6 INTERRUPTS 10.7 DEVICE-SPECIFIC PORT CONFIGURATION ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.2 12-BIT AUTORELOAD TIMER (AT2) 11.3 LITE TIMER (LT2) 11.4 DALI COMMUNICATION MODULE 11.5 SERIAL PERIPHERAL INTERFACE (SPI) 11.6 10-BIT CONVERTER (ADC) INSTRUCTION 12.1 ADDRESSING MODES 12.2 INSTRUCTION GROUPS ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS 13.2 ABSOLUTE MAXIMUM RATINGS 13.3 OPERATING CONDITIONS 13.4 SUPPLY CURRENT CHARACTERISTICS 13.5 CLOCK TIMING CHARACTERISTICS 13.6 MEMORY CHARACTERISTICS 13.7 CHARACTERISTICS 13.8 PORT CHARACTERISTICS 13.9 CONTROL CHARACTERISTICS 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.11 10-BIT CHARACTERISTICS PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA 14.2 SOLDERING GLUEABILITY INFORMATION DEVICE CONFIGURATION ORDERING INFORMATION 15.1 OPTION BYTES 15.2 DEVICE ORDERING INFORMATION 15.3 DEVELOPMENT TOOLS 15.4 APPLICATION NOTES IMPORTANT NOTES 16.1 EXECUTION BTJX INSTRUCTION 16.2 CONVERSION SPURIOUS RESULTS 16.3 CONVERTER ACCURACY FIRST CONVERSION
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ST7DALI
SUMMARY CHANGES
obtain most recent version this datasheet, please check www.st.com>products>technical literature>datasheet
Please also special attention Section "IMPORTANT NOTES" page 138.
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ST7DALI
INTRODUCTION
ST7DALI member microcontroller family. devices based common industry-standard 8-bit core, featuring enhanced instruction set. ST7DALI features FLASH memory with byteby-byte In-Circuit Programming (ICP) In-Application Programming (IAP) capability. Under software control, ST7DALI device placed WAIT, SLOW, HALT mode, reducing power consumption when application idle standby state. enhanced instruction addressing modes offer both power flexibility Figure General Block Diagram software developers, enabling design highly efficient compact application code. addition standard 8-bit data management, microcontrollers feature true manipulation, unsigned multiplication indirect addressing modes. easy reference, parametric data located section page 100.The devices feature on-chip Debug Module (DM) support in-circuit debugging (ICD). description registers, refer Protocol Reference Manual.
Int. 1MHz
8MHz 32MHz
CLKIN OSC1 OSC2
Ext. 1MHz 16MHz
12-Bit Auto-Reload TIMER 8-Bit LITE TIMER Internal CLOCK PA7:0 bits) PB6:0 bits)
PORT PORT
ADDRESS DATA
RESET POWER SUPPLY CONTROL 8-BIT CORE
OpAmp
DATA EEPROM Bytes)
PROGRAM MEMORY Bytes)
WATCHDOG
(384 Bytes)
DALI
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DESCRIPTION
Figure 20-Pin Package Pinout
RESET SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 AIN5/PB5 DALIIN/AIN6/PB6
OSC1/CLKIN OSC2 (HS)/LTIC (HS)/ATIC (HS)/ATPWM0 (HS)/ATPWM1 (HS)/ATPWM2 (HS)/ATPWM3/ICCDATA PA6/MCO/ICCCLK/BREAK PA7(HS)/DALIOUT
(HS) 20mA high sink capability associated external interrupt vector
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DESCRIPTION (Cont'd) Legend Abbreviations Table Type: input, output, supply In/Output level: CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration: Input: float floating, weak pull-up, interrupt, analog Output: open drain, push-pull RESET configuration each shown bold which valid long device reset state.
Table Device Description
SO20 (ST7DALI) Type Name Level Output Input Port Control Input float Output Main Function (after reset) Alternate Function
RESET PB0/AIN0/SS PB1/AIN1/SCK PB2/AIN2/MISO PB3/AIN3/MOSI
Ground Main power supply priority maskable interrupt (active low) Analog Input Port Slave Select (active low) Analog Input SePort rial Clock Analog Input Port Master Slave Data Analog Input Port Master Slave Data Analog Input ExterPort clock input Port Port Analog Input Analog Input DALI Input
PB4/AIN4/CLKIN PB5/AIN5
PB6/AIN6/DALIIN
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SO20 (ST7DALI) Type Name
Level Output Input
Port Control Input float Output Main Function (after reset) Alternate Function
PA7/DALIOUT
Port
DALI Output Main Clock Output Circuit Communication Clock External BREAK
/MCO/ ICCCLK/BREAK
Port
/ATPWM3/ ICCDATA
Port Port Port Port Port Port
Caution: During reset, this must held high level avoid entering mode unexpectedly (this guaranteed internal pull-up application leaves floating). Auto-Reload Timer PWM3 Circuit Communication Data Auto-Reload Timer PWM2 Auto-Reload Timer PWM1 Auto-Reload Timer PWM0 Auto-Reload Timer Input Capture Lite Timer Input Capture
PA4/ATPWM2 PA3/ATPWM1 PA2/ATPWM0 PA1/ATIC PA0/LTIC OSC2 OSC1/CLKIN
Resonator oscillator inverter output Resonator oscillator inverter input External clock input
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REGISTER MEMORY
shown Figure capable addressing bytes memories registers. available memory locations consist bytes register locations, bytes RAM, bytes data EEPROM Kbytes user program memory. space includes bytes stack from 180h 1FFh. highest address bytes contain user reset interrupt vectors. Flash memory contains sectors (see Figure mapped upper part adFigure Memory
0080h
dressing space reset interrupt vectors located Sector (F000h-FFFFh). size Flash Sector other device options configurable Option byte (refer section 15.1 page 132). IMPORTANT: Memory locations marked "Reserved" must never accessed. Accessing reseved area have unpredictable effects device.l
Short Addressing (zero page)
0000h 007Fh 0080h 01FFh 0200h
Registers (see Table (384 Bytes) Reserved
00FFh 0100h
16-bit Addressing
017Fh 0180h
Bytes Stack
01FFh
0FFFh 1000h 10FFh 1100h
Data EEPROM (256 Bytes)
1000h
RCCR0 RCCR1
1001h
Reserved
DFFFh E000h
FLASH PROGRAM MEMORY
section page
E000h
Flash Memory (8K)
FFDFh FFE0h
FBFFh FC00h FFFFh
Kbytes SECTOR Kbyte SECTOR FFDEh
Interrupt Reset Vectors (see Table
RCCR0 RCCR1
FFFFh
FFDFh
section page
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Table Hardware Register
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 002Dh 002Eh 0002Fh 00030h 0031h 0032h 0033h 0034h 0035h 0036h FLASH EEPROM WDGCR FCSR EECSR SPIDR SPICR SPICSR ADCCSR ADCDRH ADCDRL LTCSR2 LTARR LTCNTR LTCSR1 LTICR ATCSR CNTRH CNTRL ATRH ATRL PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL TRANCR BREAKCR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR Register Name Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Reserved Area bytes) Lite Timer Lite Timer Lite Timer Lite Timer Lite Timer Control/Status Register Auto-reload Register Counter Register Control/Status Register Input Capture Register 0X00 0000h 0X00 0000h Read Only Read Only Read Only Read Only Read Only Read Only Reset Status FFh1) Remarks R/W2)
Port
Port
LITE TIMER
AUTORELOAD TIMER
Timer Control/Status Register Counter Register High Counter Register Auto-Reload Register High Auto-Reload Register Output Control Register Control/Status Register Control/Status Register Control/Status Register Control/Status Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Input Capture Register High Input Capture Register Transfer Control Register Break Control Register Reserved area bytes) Watchdog Control Register Flash Control/Status Register Data EEPROM Control/Status Register Data Register Control Register Control Status Register Control Status Register Data Register High Amplifier Control/Data Register
Read Only
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Address 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 007Fh
Block Clock Reset
Register Label EICR MCCSR RCCR SICSR
Register Name External Interrupt Control Register Main Clock Control/Status Register oscillator Control Register System Integrity Control/Status Register Reserved area byte)
Reset Status 0000 0XX0h
Remarks
EISR
External Interrupt Selection Register Reserved area bytes)
DALI
DCMCLK DCMFA DCMFD DCMBD DCMCR DCMCSR
DALI DALI DALI DALI DALI DALI
Clock Register Forward Address Register Forward Data Register Backward Data Register Control Register Control/Status Register Reserved area bytes)
AWUPR AWUCSR DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L
Prescaler Register Control/Status Register Control Register Status Register Breakpoint Register High Breakpoint Register Breakpoint Register High Breakpoint Register Reserved area bytes)
DM3)
Legend: x=undefined, R/W=read/write Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always keep their reset value. description Debug Module registers, reference manual.
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ST7DALI
FLASH PROGRAM MEMORY
Introduction single voltage extended Flash (XFlash) non-volatile memory that electrically erased programmed either byte-by-byte basis bytes parallel. XFlash devices programmed off-board (plugged programming tool) on-board using In-Circuit Programming In-Application Programming. array matrix organisation allows each sector erased reprogrammed without affecting other sectors. Main Features
(In-Circuit Programming) (In-Application Programming) (In-Circuit Testing) downloading executing user application test patterns Sector size configurable option byte Read-out write protection against piracy
PROGRAMMING MODES programmed three different ways: Insertion programming tool. this mode, FLASH sectors option byte data EEPROM present) programmed erased. In-Circuit Programming. this mode, FLASH sectors option byte data EEPROM present) programmed erased without removing device from application board. In-Application Programming. this mode, sector data EEPROM present) programmed erased without removing
device from application board while application running. 4.3.1 In-Circuit Programming (ICP) uses protocol called (In-Circuit Communication) which allows plugged printed circuit board (PCB) communicate with external programming device connected cable. performed three steps: Switch mode (In-Circuit Communications). This done driving specific signal sequence ICCCLK/DATA pins while RESET pulled low. When enters mode, fetches specific RESET vector which points System Memory containing protocol routine. This routine enables receive bytes from interface. Download Driver code from ICCDATA Execute Driver code program FLASH memory Depending Driver code downloaded RAM, FLASH memory programming fully customized (number bytes program, program locations, selection serial communication interface downloading). 4.3.2 Application Programming (IAP) This mode uses Driver program previously programmed Sector user mode). This mode fully controlled user software. This allows adapted user application, (user-defined strategy entering programming mode, choice communications protocol used fetch data stored etc.) mode used program memory areas except Sector which write/erase protected allow recovery case errors occur during programming operation.
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FLASH PROGRAM MEMORY (Cont'd) interface needs minimum pins connected programming tool. These pins are: RESET: device reset VSS: device power supply ground ICCCLK: output serial clock ICCDATA: input serial data OSC1: main clock input external source (not required devices without OSC1/OSC2 pins) VDD: application board power supply (optional, Note Notes: ICCCLK ICCDATA pins only used outputs application, signal isolation necessary. soon Programming Tool plugged board, even session progress, ICCCLK ICCDATA pins available application. they used inputs application, isolation such serial resistor implemented case another device forces signal. Refer Programming Tool documentation recommended resistor values. During session, programming tool must control RESET pin. This lead conflicts between programming tool appliFigure Typical Interface
PROGRAMMING TOOL CONNECTOR Cable OPTIONAL (See Note OPTIONAL (See Note CONNECTOR HE10 CONNECTOR TYPE APPLICATION BOARD
cation reset circuit drives more than high level (push pull output pull-up resistor<1K). schottky diode used isolate application RESET circuit this case. When using classical network with R>1K reset management with open drain output pull-up resistor>1K, additional components needed. cases user must ensure that external reset generated application during session. connector depends Programming Tool architecture. This must connected when using most Programming Tools used monitor application power supply). Please refer Programming Tool manual. connected OSC1 when clock available application selected clock option programmed option byte. devices with multi-oscillator capability need have OSC2 grounded this case. During reset, this must held high level avoid entering mode unexpectedly (this guaranteed internal pull-up application leaves floating).
APPLICATION RESET SOURCE Note
APPLICATION POWER SUPPLY
Notes APPLICATION Note RESET ICCCLK ICCDATA
OSC2
OSC1
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FLASH PROGRAM MEMORY (Cont'd) Memory Protection There different types memory protection: Read Protection Write/Erase Protection which applied individually. 4.5.1 Read Protection Read protection, when selected, makes impossible extract memory content from microcontroller, thus preventing piracy. Both program data memory protected. flash devices, this protection removed reprogramming option. this case, both program data memory automatically erased device reprogrammed. Read-out protection selection depends device type: Flash devices enabled removed through FMP_R option byte. devices enabled mask option specified Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes impossible both overwrite erase program memory. does apply data. purpose provide advanced security applications prevent change being made memory content. Warning: Once set, Write/erase protection never removed. write-protected flash device longer reprogrammable. Write/erase protection enabled through FMP_W option byte. Related Documentation details Flash programming protocol, refer Flash Programming Reference Manual Protocol Reference Manual. Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read /Write Reset Value: 0000 (00h) RASS Key: 0101 0110 (56h) RASS Key: 1010 1110 (AEh)
Note: This register reserved programming using ICP, other programming methods. controls XFlash programming erasing operations. When another programming tool used socket mode), RASS keys sent automatically.
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DATA EEPROM
INTRODUCTION Electrically Erasable Programmable Read Only Memory used volatile backup storing data. Using EEPROM requires basic access protocol described this chapter. MAIN FEATURES
Bytes programmed same cycle EEPROM mono-voltage (charge pump) Chained erase programming cycles Internal control global programming cycle duration WAIT mode management Readout protection against piracy
Figure EEPROM Block Diagram
HIGH VOLTAGE PUMP
EECSR
E2LAT E2PGM
ADDRESS DECODER
DECODER
EEPROM MEMORY MATRIX BITS)
DATA MULTIPLEXER
BITS DATA LATCHES
ADDRESS
DATA
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DATA EEPROM (Cont'd) MEMORY ACCESS Data EEPROM memory read/write access modes controlled E2LAT EEPROM Control/Status register (EECSR). flowchart Figure describes these different memory access modes. Read Operation (E2LAT=0) EEPROM read normal location when E2LAT EECSR register cleared. read cycle, byte accessed data less than clock cycle. This means that reading data from EEPROM takes same time reading data from EPROM, this memory cannot used execute machine code. Write Operation (E2LAT=1) access write mode, E2LAT software (the E2PGM remains cleared). When write access EEPROM area occurs, Figure Data EEPROM Programming Flowchart value latched inside data latches according address. When software, previous bytes written data latches programmed EEPROM cells. effective high address (row) determined last EEPROM write sequence. avoid wrong programming, user must take care that bytes written between programming sequences have same high address: only five Least Significant Bits address change. programming cycle, bits cleared simultaneously. Note: Care should taken during programming cycle. Writing same memory location will over-program memory (logical between write access data result) because data latches only cleared programming cycle falling edge E2LAT bit. possible read latched data. This note ilustrated Figure
READ MODE E2LAT=0 E2PGM=0
WRITE MODE E2LAT=1 E2PGM=0
READ BYTES EEPROM AREA
WRITE BYTES EEPROM AREA (with same address)
START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set software)
CLEARED HARDWARE
E2LAT
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DATA EEPROM (Cont'd) Figure Data E2PROM Write Operation
Byte
DEFINITION
Physical Addres
Read operation impossible
00h.1Fh 20h.3Fh Nx20h.Nx20h+1Fh
Read operation possible
Byte
Byte PHASE
Byte
Programming cycle PHASE
Writing data latches E2LAT
USER application
Waiting E2PGM E2LAT fall
Cleared hardware
E2PGM
Note: programming cycle interrupted software reset action), integrity data memory guaranteed.
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DATA EEPROM (Cont'd) POWER SAVING MODES Wait mode DATA EEPROM enter WAIT mode execution instruction microcontroller when microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode there programming progress, otherwise DATA EEPROM will finish cycle then enter WAIT mode. Active-Halt mode Refer Wait mode. Halt mode DATA EEPROM immediately enters HALT mode microcontroller executes HALT instruction. Therefore EEPROM will stop function progress, data corrupted. ACCESS ERROR HANDLING read access occurs while E2LAT=1, then data will driven. write access occurs while E2LAT=0, then data will latched. programming cycle interrupted software/ RESET action), memory data will guaranteed. Data EEPROM Read-out Protection read-out protection enabled through option (see section 15.1 page 132). When this option selected, programs data stored EEPROM memory protected against read-out piracy (including re-write protection). Flash devices, when this protection removed reprogramming Option Byte, entire Program memeory EEPROM first automatically erased. Note: Both Program Memory data EEPROM protected using same option bit.
Figure Data EEPROM Programming Cycle
READ OPERATION POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE
tPROG
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DATA EEPROM (Cont'd) REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECSR) Read /Write Reset Value: 0000 0000 (00h)
E2LAT E2PGM
Bits Reserved, forced hardware E2LAT Latch Access Transfer This software. cleared hardware programming cycle. only cleared software E2PGM cleared. Read mode Write mode E2PGM Programming control status This software begin programming cycle. programming cycle, this cleared hardware. Programming finished started Programming cycle progress Note: E2PGM cleared during programming cycle, memory data guaranteed Table DATA EEPROM Register Reset ValueAddress (Hex.) 0030h Register Label EECSR Reset Value E2LAT E2PGM
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CENTRAL PROCESSING UNIT
INTRODUCTION This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation. MAIN FEATURES
basic instructions Fast 8-bit 8-bit multiply main addressing modes 8-bit index registers 16-bit stack pointer power modes Maskable hardware interrupts Non-maskable software interrupt
REGISTERS registers shown Figure present memory mapping accessed specific instructions. Figure Register7 RESET VALUE RESET VALUE RESET VALUE
Accumulator Accumulator 8-bit general purpose register used hold operands results arithmetic logic calculations manipulate data. Index Registers indexed addressing modes, these 8-bit registers used create either effective addresses temporary storage areas data manipulation. (The Cross-Assembler generates precede instruction (PRE) indicate that following instruction refers register.) register affected interrupt automatic procedures (not pushed popped from stack). Program Counter (PC) program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (Program Counter which LSB) (Program Counter High which MSB).
ACCUMULATOR
INDEX REGISTER
INDEX REGISTER
PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh-FFFFh CONDITION CODE REGISTER
RESET VALUE STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value
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REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
because hardware start routine reset IRET instruction routine. cleared software interrupt routine, pending interrupts serviced regardless priority level current interrupt routine. Negative. This cleared hardware. representative result sign last arithmetic, logical data manipulation. copy result. result last operation positive null. result last operation negative (i.e. most significant logic This accessed JRMI JRPL instructions. Zero. This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero. result last operation zero. This accessed JREQ JRNE test instructions.
8-bit Condition Code register contains interrupt mask four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions. Half carry. This hardware when carry occurs between bits during instruction. reset hardware during same instructions. half carry occurred. half carry occurred. This tested using JRNH instruction. useful arithmetic subroutines. Interrupt mask. This hardware when entering interrupt software disable interrupts except TRAP software interrupt. This cleared software. Interrupts enabled. Interrupts disabled. This controlled RIM, IRET instructions tested JRNM instructions. Note: Interrupts requested while latched processed when cleared. default interrupt routine interruptable
Carry/borrow. This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred. overflow underflow occurred. This driven instructions tested JRNC instructions. also affected "bit test branch", shift rotate instructions.
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REGISTERS (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 01FFh
Stack Pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure 10). Since stack bytes deep, most significant bits forced hardware. Following Reset, after Reset Stack Pointer instruction (RSP), Stack Pointer contains reset value (the bits set) which stack higher address. least significant byte Stack Pointer (called directly accessed instruction. Figure Stack Manipulation Example
CALL Subroutine 0180h Interrupt Event PUSH
Note: When lower limit exceeded, Stack Pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instructions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure When interrupt received, decremented context pushed stack. return from interrupt, incremented context popped from stack. subroutine call occupies locations interrupt five locations stack area.
IRET
01FFh
Stack Higher Address 01FFh Stack Lower Address 0180h
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SUPPLY, RESET CLOCK MANAGEMENT
device includes range utility features securing application critical situations (for example case power brown-out), reducing number external components. Main feature
RCCR
Conditions VDD=5V TA=25°C fRC=1MHz VDD=3V TA=25°C fRC=700KHz
ST7DALI Address 1000h FFDEh 1001h FFDFh
RCCR0
Clock Management internal oscillator (enabled option byte) 32kHz External crystal/ceramic resonator (selected option byte) External Clock Input (enabled option byte) multiplying frequency (enabled option byte) clock counter only: PLL32 multiplying frequency (enabled option byte). input frequency mandatory obtained following ways: PLLx8 external clock (internally divided MHz. external clock (internally divided PLLx8 -Crystal oscillator with output frequency (internally divided Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply voltage detection (LVD) with reset generation (enabled option byte) Auxiliary Voltage detector (AVD) with interrupt capability monitoring main supply (enabled option byte)
RCCR1
Note: "ELECTRICAL CHARACTERISTICS" page 100. more information frequency accuracy oscillator. improve clock stability, recommended place decoupling capacitor between pins. These bytes systematically programmed including FASTROM devices. Consequently, customers intending FASTROM service must these bytes. RCCR0 RCCR1 calibration values will erased read-out protection reset after been set. "Read Protection" page Caution: voltage temperature conditions change application, frequency need recalibrated. Refer application note AN1324 information calibrate frequency using external reference signal. PHASE LOCKED LOOP used multiply 1MHz frequency from oscillator external clock obtain fOSC MHz. enabled multiplication factor selected option bits. intended operation with 2.4V 3.3V range intended operation with 3.3V 5.5V range Refer Section 15.1 option byte description. disabled oscillator enabled, then fOSC 1MHz. both oscillator disabled, fOSC driven external clock.
INTERNAL OSCILLATOR ADJUSTMENT device contains internal oscillator with accuracy given device, temperature voltage range (4.5V-5.5V). must calibrated obtain frequency required application. This done software writing calibration value RCCR Control Register). Whenever microcontroller reset, RCCR returns default value (FFh), i.e. each time device reset, calibration value must loaded RCCR. Predefined calibration values stored EEPROM supply voltages 25°C, shown following table.
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PHASE LOCKED LOOP (Cont'd) Figure Output Frequency Timing Diagram LOCKED input freq. tSTAB Output freq. tLOCK Bits Reserved, must kept cleared. tSTARTUP Main Clock enable This read/write software cleared hardware after reset. This allows enable output clock. clock disabled, port free general purpose I/O. clock enabled. REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read Write Reset Value: 0000 0000 (00h)
When started, after reset wakeup from Halt mode AWUFH mode, outputs clock after delay tSTARTUP. When output signal reaches operating frequency, LOCKED SICSCR register set. Full accuracy (ACC PLL) reached after stabilization time tSTAB (see Figure 13.3.4 Internal Oscillator PLL) Refer section 7.6.4 page description LOCKED SICSR register.
Slow Mode select This read/write software cleared hardware after reset. This selects input clock fOSC fOSC/32. Normal mode (fCPU fOSC Slow mode (fCPU fOSC/32)
CONTROL REGISTER (RCCR) Read Write Reset Value: 1111 1111 (FFh)
CR70 CR60 CR50 CR40 CR30 CR20 CR10
Bits CR[7:0] Oscillator Frequency Adjustment Bits These bits must written immediately after reset adjust oscillator frequency obtain accuracy application store correct value each voltage range EEPROM write this register start-up. maximum available frequency lowest available frequency Note: tune oscillator, write series different values register until correct frequency reached. fastest method dichotomy starting with 80h.
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Figure Clock Management Block Diagram
RCCR 8MHz 32MHz 12-BIT TIMER PLLx4x8
Tunable Oscillator OSC,PLLOFF, OSCRANGE[2:0] Option bits CLKIN CLKIN CLKIN DIVIDER
fCPU
1MHz 8MHz 1MHz 4MHz CLKIN/2 CLKIN/2 OSC/2
fOSC
CLKIN /OSC1 OSC2
1-16 32kHz
DIVIDER
OSC,PLLOFF, OSCRANGE[2:0] Option bits 8-BIT LITE TIMER COUNTER fOSC DIVIDER fOSC/32 fLTIMER (1ms timebase fOSC)
fCPU PERIPHERALS
fOSC
MCCSR fCPU
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MULTI-OSCILLATOR (MO) main clock generated four different source types coming from multioscillator block 16MHz 32kHz): external source crystal ceramic resonator oscillators internal high frequency oscillator Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configurations shown Table Refer electrical characteristics section more details. External Clock Source this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground. Note: when Multi-Oscillator used, selected default external clock. Crystal/Ceramic Oscillators This family oscillators advantage producing very accurate rate main clock ST7. selection within list oscillators with different frequency ranges done option byte order reduce consumption (refer section 15.1 page more details frequency ranges). this mode multi-oscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during RESET phase avoid losing time oscillator start-up phase. Internal Oscillator this mode, tunable 1%RC oscillator used main clock source. oscillator pins have tied ground. Table Clock SourceHardware Configuration
External Clock
OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonator
OSC1 OSC2
LOAD CAPACITORS
Internal Oscillator
OSC1 OSC2
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RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction reset sequence manager includes three RESET sources shown Figure External RESET source pulse Internal RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources RESET always kept during delay phase. RESET service routine vector fixed addresses FFFEh-FFFFh memory map. basic RESET sequence consists phases shown Figure Active Phase depending RESET source 4096 clock cycle delay (see table below) RESET vector fetch 4096 clock cycle delay allows oscillator stabilise ensures that recovery taken place from Reset state. shorter longer clock cycle delay automatically selected depending clock source chosen option byte:
Clock Source Internal Oscillator External clock (connected CLKIN pin) External Crystal/Ceramic Oscillator (connected OSC1/OSC2 pins) clock cycle delay 4096
RESET vector fetch phase duration clock cycles. enabled option byte, outputs clock after additional delay tSTARTUP (see Figure 11). Figure RESET Sequence Phase
RESET
Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
7.5.2 Asynchronous External RESET RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies accordance with input voltage. pulled external circuitry reset device. Electrical Characteristic section more details. RESET signal originating from external source must have duration least th(RSTL)in order recognized (see Figure 15). This detection asynchronous therefore enter reset state even HALT mode.
Figure Reset Block Diagram
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET RESET
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RESET SEQUENCE MANAGER (Cont'd) RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section. 7.5.3 External Power-On RESET disabled option byte, start microcontroller correctly, user must ensure means external reset circuit that reset signal held until over minimum level specified selected fOSC frequency. proper reset signal slow rising supply generally provided external network connected RESET pin. 7.5.4 Internal Voltage Detector (LVD) RESET different RESET sequences caused internal circuitry distinguished: Power-On RESET Voltage Drop RESET device RESET acts output that pulled when VDD<VIT+ (rising edge) VDD<VIT- (falling edge) shown Figure filters spikes larger than tg(VDD) avoid parasitic resets. 7.5.5 Internal Watchdog RESET RESET sequence generated internal Watchdog counter overflow shown Figure Starting from Watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out.
Figure RESET Sequences
VIT+(LVD) VIT-(LVD)
RESET
EXTERNAL RESET
WATCHDOG RESET
ACTIVE PHASE
ACTIVE PHASE
ACTIVE PHASE
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 4096 TCPU) VECTOR FETCH
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SYSTEM INTEGRITY MANAGEMENT (SI) System Integrity Management block contains voltage Detector (LVD) Auxiliary Voltage Detector (AVD) functions. managed SICSR register. 7.6.1 Voltage Detector (LVD) Voltage Detector function (LVD) generates static reset when supply voltage below VIT-(LVD) reference value. This means that secures power-up well power-down keeping reset. VIT-(LVD) reference value voltage drop lower than IT+(LVD) reference value poweron order avoid parasitic reset when starts running sinks current supply (hysteresis). Reset circuitry generates reset when below: VIT+(LVD)when rising VIT-(LVD) when falling function illustrated Figure Figure Voltage Detector Reset
voltage threshold configured option byte low, medium high. Provided minimum value (guaranteed oscillator frequency) above VIT-(LVD), only modes: under full software control static safe reset these conditions, secure operation always ensured application without need external reset hardware. During Voltage Detector Reset, RESET held low, thus permitting reset other devices. Notes: allows device used without external RESET circuitry. optional function which selected option byte.
Vhys VIT+(LVD) VIT- (LVD)
RESET
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Figure Reset Supply Management Block Diagram
WATCHDOG TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR
WDGRF LOCKED LVDRF AVDF AVDIE
Interrupt Request
VOLTAGE DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.2 Auxiliary Voltage Detector (AVD) Voltage Detector function (AVD) based analog comparison between VIT-(AVD) VIT+(AVD) reference value main supply voltage (VAVD). VIT-(AVD) reference value falling voltage lower than IT+(AVD) reference value rising voltage order avoid parasitic detection (hysteresis). output comparator directly readable application software through real time status (AVDF) SICSR register. This read only. Caution: functions only enFigure Using Monitor Early Warning Interrupt (Power dropped, reset)
Vhyst
abled through option byte. 7.6.2.1 Monitoring Main Supply voltage threshold value relative selected threshold configured option byte (see section 15.1 page 132). interrupt enabled, interrupt generated when voltage crosses VIT+(LVD) VIT-(AVD) threshold (AVDF set). case drop voltage, interrupt acts early warning, allowing software shut down safely before resets microcontroller. Figure
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF INTERRUPT REQUEST AVDIE
RESET
INTERRUPT Cleared reset
INTERRUPT Cleared hardware
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.3 Power ModeMode WAIT HALT Description effect interrupts cause device exit from Wait mode. CRSR register frozen. remains active. Interrupt Event event Enable Event Control Flag AVDF AVDIE Exit from Wait Exit from Halt
interrupt mask register reset (RIM instruction).
7.6.3.1 Interrupts interrupt event generates interrupt corresponding Enable Control (AVDIE)
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read /Write LVDRF reset flag This indicates that last Reset generatReset Value: 0000 0xx0 (0xh) block. hardware (LVD reset) cleared software reading). When disabled OPTION BYTE, LVDRF value undefined.
LOCKED LVDRF AVDF AVDIE
Reserved, must kept cleared. WDGRF Watchdog reset flag This indicates that last Reset generated Watchdog peripheral. hardware (watchdog reset) cleared software (writing zero) Reset ensure stable cleared state WDGRF flag when starts). Combined with LVDRF flag information, flag description given following table.
RESET Sources External RESET Watchdog LVDRF WDGRF
AVDF Voltage Detector flag This read-only cleared hardware. AVDIE set, interrupt request generated when AVDF set. Refer Figure Section 7.6.2.1 additional details. over threshold under threshold AVDIE Voltage Detector interrupt enable This cleared software. enables interrupt generated when AVDF flag set. pending interrupt information automatically cleared when software enters interrupt routine. interrupt disabled interrupt enabled Application notes LVDRF flag cleared when another RESET type occurs (external watchdog), LVDRF flag remains keep trace original failure. this case, watchdog reset detected software while external reset not.
LOCKED Locked Flag This cleared hardware. automatically when reaches operating frequency. locked locked
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INTERRUPTS
core interrupted different methods: maskable hardware interrupts listed Interrupt Mapping Table nonmaskable software interrupt (TRAP). Interrupt processing flowchart shown Figure maskable interrupts must enabled clearing order serviced. However, disabled interrupts latched processed when they enabled (see external interrupts subsection). Note: After reset, interrupts disabled. When interrupt serviced: Normal processing suspended current instruction execution. registers saved onto stack. register prevent additional interrupts. then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer Interrupt Mapping Table vector addresses). interrupt service routine should finish with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, will cleared main program will resume. Priority Management default, servicing interrupt cannot interrupted because hardware entering interrupt routine. case when several interrupts simultaneously pending, hardware priority defines which will serviced first (see Interrupt Mapping Table). Interrupts Power Mode interrupts allow processor leave WAIT power mode. Only external specifically mentioned interrupts allow processor leave HALT power mode (refer "Exit from HALT" column Interrupt Mapping Table). MASKABLE SOFTWARE INTERRUPT This interrupt entered when TRAP instruction executed regardless state bit. will serviced according flowchart Figure EXTERNAL INTERRUPTS External interrupt vectors loaded into register corresponding external interrupt occurred cleared. These interrupts allow processor leave Halt power mode. external interrupt polarity selected through miscellaneous register interrupt register available). external interrupt triggered edge will latched interrupt request automatically cleared upon entering interrupt service routine. several input pins, connected same interrupt vector, configured interrupts, their signals logically NANDed before entering edge/level detection block. Caution: type sensitivity defined Miscellaneous Interrupt register available) applies source. case NANDed source described ports section), level configured input with interrupt, masks interrupt request even case risingedge sensitivity. PERIPHERAL INTERRUPTS Different peripheral interrupt flags status register able cause interrupt when they active both: register cleared. corresponding enable control register. these conditions false, interrupt latched thus remains pending. Clearing interrupt request done Writing corresponding status register Access status register while flag followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (i.e. waiting being enabled) will therefore lost clear sequence executed.
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INTERRUPTS (Cont'd) Figure Interrupt Processing Flowchart
FROM RESET SET?
INTERRUPT PENDING?
FETCH NEXT INSTRUCTION
IRET?
STACK LOAD FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE FROM STACK THIS CLEARS DEFAULT
Table Interrupt Mapping
Source Block RESET TRAP LITE TIMER DALI TIMER Reset Software Interrupt Auto Wake Interrupt External Interrupt External Interrupt External Interrupt External Interrupt LTCSR2 DCMCSR SICSR Lowest Priority DALI interrupt Register Label Exit Exit from from Priority Order HALT ACTIVE AWUFH -HALT Highest Priority yes1) Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Description
AWUCSR
LITE TIMER LITE TIMER RTC2 interrupt
TIMER Output Compare Interrupt PWMxCSR Input Capture Interrupt ATCSR TIMER Overflow Interrupt LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt Peripheral Interrupts used ATCSR LTCSR LTCSR SPICSR
Note This interrupt exits from "Auto Wake-up from Halt" mode only.
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read /Write Reset Value: 0000 0000 (00h)
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
EXTERNAL INTERRUPT SELECTION REGISTER (EISR) Read /Write Reset Value: 0000 1100 (0Ch)
ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00
IS3[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS2[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS1[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS0[1:0] sensitivity These bits define interrupt sensitivity (Port according Table Note: These bits written only when register set.
ei3[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei31 ei30
Reset State ei2[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei21 ei20
Table Interrupt Sensitivity BitISx1 ISx0 External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
Reset State
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INTERRUPTS (Cont'd) ei1[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei11 ei10 PA7*
Port used external interrupt according table below. External Interrupt selection
ei01 ei00
Reset State Bits Reserved.
Reset State ei0[1:0] selection These bits written software. They select
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POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, five main power saving modes implemented (see Figure 20): Slow Wait (and Slow-Wait) Active Halt Auto Wake From Halt (AWUFH) Halt After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided multiplied (fOSC2). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power Saving Mode TransitionfOSC
SLOW MODE This mode targets: reduce power consumption decreasing internal clock device, adapt internal clock frequency (fCPU) available supply voltage. SLOW mode controlled MCCSR register which enables disables Slow mode. this mode, oscillator frequency divided peripherals clocked this lower frequency. Note: SLOW-WAIT mode activated when entering WAIT mode while device already SLOW mode. Figure SLOW Mode Clock Transition
fOSC/32 fCPU fOSC
High SLOW WAIT SLOW WAIT ACTIVE HALT AUTO WAKE FROM HALT HALT POWER CONSUMPTION
NORMAL MODE REQUEST
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POWER SAVING MODES (Cont'd) WAIT MODE WAIT mode places power consumption mode stopping CPU. This power saving mode selected calling `WFI' instruction. peripherals remain active. During WAIT mode, register cleared, enable interrupts. other registers memory remain unchanged. remains WAIT mode until interrupt RESET occurs, whereupon Program Counter branches starting address interrupt Reset service routine. will remain WAIT mode until Reset Interrupt occurs, causing wake Refer Figure Figure WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS
INSTRUCTION
RESET INTERRUPT OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS
FETCH RESET VECTOR SERVICE INTERRUPT
Note: Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
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POWER SAVING MODES (Cont'd) HALT MODE HALT mode lowest power consumption mode MCU. entered executing `HALT' instruction when ACTIVE-HALT disabled (see section page more details) when AWUEN AWUCSR register cleared. exit HALT mode reception either specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting HALT mode means RESET interrupt, oscillator immediately turned 4096 cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 24). When entering HALT mode, register forced enable interrupts. Therefore, interrupt pending, wakes immediately. HALT mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. peripherals clocked except ones which their clock supply from another clock generator (such external auxiliary oscillator). compatibility Watchdog operation with HALT mode configured "WDGHALT" option option byte. HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET (see section 15.1 page more details). Figure HALT Timing Overview
HALT 4096 CYCLE DELAY RESET INTERRUPT FETCH VECTOR
Figure HALT Mode Flow-chart
HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=0) ENABLE WDGHALT WATCHDOG RESET OSCILLATOR PERIPHERALS WATCHDOG DISABLE
RESET
INTERRUPT
OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY5) OSCILLATOR PERIPHERALS
FETCH RESET VECTOR SERVICE INTERRUPT
HALT INSTRUCTION [Active Halt disabled]
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from HALT mode (such external interrupt). Refer Table Interrupt Mapping more details. Before servicing interrupt, register pushed stack. register during interrupt routine cleared whenthe register popped. enabled option byte, outputs clock after delay tSTARTUP (see Figure 11).
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POWER SAVING MODES (Cont'd) 9.4.1 Halt Mode Recommendations Make sure that external event available wake microcontroller from Halt mode. When using external interrupt wake microcontroller, reinitialize corresponding "Input Pull-up with Interrupt" before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant program memory with value 0x8E. HALT instruction clears interrupt mask register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt).
ACTIVE-HALT MODE ACTIVE-HALT mode lowest power consumption mode with real time clock available. entered executing `HALT' instruction. decision enter either ACTIVEHALT HALT mode given LTCSR/ATCSR register status shown following table:
ATCSR ATCSR ATCSR LTCSR1 OVFIE TB1IE Meaning ACTIVE-HALT mode disabled ACTIVE-HALT mode enabled
exit ACTIVE-HALT mode reception specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting ACTIVE-HALT mode means RESET, 4096 cycle delay occurs. After start delay, resumes operation fetching reset vector which woke (see Figure 26). When exiting ACTIVE-HALT mode means interrupt, immediately resumes operation servicing interrupt vector which woke (see Figure 26). When entering ACTIVE-HALT mode, register cleared enable interrupts. Therefore, interrupt pending, wakes immediately (see Note ACTIVE-HALT mode, only main oscillator selected timer counter (LT/AT) running keep wake-up time base. other peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator). Note: soon ACTIVE-HALT enabled, executing HALT instruction while Watchdog active does generate RESET. This means that device cannot spend more than defined delay this power saving mode.
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POWER SAVING MODES (Cont'd) Figure ACTIVE-HALT Timing Overview
ACTIVE 4096 HALT CYCLE DELAY RESET INTERRUPT
AUTO WAKE FROM HALT MODE Auto Wake From Halt (AWUFH) mode similar Halt mode with addition specific internal oscillator wake-up (Auto Wake from Halt Oscillator). Compared ACTIVE-HALT mode, AWUFH lower power consumption (the main clock kept running, there accurate realtime clock available. entered executing HALT instruction when AWUEN AWUCSR register been set. Figure AWUFH Mode Block Diagram oscillator fAWU_RC Timer input capture
HALT INSTRUCTION [Active Halt Enabled]
FETCH VECTOR
Figure ACTIVE-HALT Mode Flow-chart
OSCILLATOR PERIPHERALS
HALT INSTRUCTION (Active Halt enabled) (AWUCSR.AWUEN=0)
RESET INTERRUPT OSCILLATOR PERIPHERALS 4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS
divider
AWUFH prescaler/1
AWUFH interrupt (ei0 source)
FETCH RESET VECTOR SERVICE INTERRUPT
Notes: This delay occurs only exits ACTIVEHALT mode means RESET. Peripherals clocked with external clock source still active. Only RTC1 interrupt some specific interrupts exit from ACTIVE-HALT mode. Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
soon HALT mode entered, AWUEN been AWUCSR register, oscillator provides clock signal (fAWU_RC). frequency divided fixed divider programmable prescaler controlled AWUPR register. output this prescaler provides delay time. When delay elapsed AWUF flag hardware interrupt wakes-up from Halt mode. same time main oscillator immediately turned 4096 cycle delay used stabilize After this start-up delay, resumes operation servicing AWUFH interrupt. flag associated interrupt cleared software reading AWUCSR register. compensate frequency dispersion oscillator, calibrated measuring clock frequency fAWU_RC then calculating right prescaler value. Measurement mode enabled setting AWUM AWUCSR register mode. This connects fAWU_RC input capture 12-bit Auto-Reload timer, allowing fAWU_RC measured using main oscillator clock reference timebase.
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POWER SAVING MODES (Cont'd) Similarities with Halt mode following AWUFH mode behaviour same normal Halt mode: exit AWUFH mode means interrupt with exit from Halt capability reset (see Section HALT MODE). When entering AWUFH mode, register forced enable interrupts. Therefore, interrupt pending, wakes immediately. AWUFH mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. None peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator like oscillator). compatibility Watchdog operation with AWUFH mode configured WDGHALT option option byte. Depending this setting, HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET.
Figure AWUF Halt Timing Diagram tAWU MODE
fCPU fAWU_RC
HALT MODE
4096 tCPU
MODE
Clear software
AWUFH interrupt
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POWER SAVING MODES (Cont'd) Figure AWUFH Mode Flow-chart
HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WDGHALT WATCHDOG RESET MAIN PERIPHERALS I[1:0] BITS WATCHDOG DISABLE
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only AWUFH interrupt some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped. enabled option byte, outputs clock after additional delay tSTARTUP (see Figure 11).
RESET INTERRUPT MAIN PERIPHERALS I[1:0] BITS
4096 CLOCK CYCLE DELAY5) MAIN PERIPHERALS I[1:0] BITS
FETCH RESET VECTOR SERVICE INTERRUPT
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POWER SAVING MODES (Cont'd) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read /Write Reset Value: 0000 0000 (00h)
Bits 7:0= AWUPR[7:0] Auto Wake Prescaler These bits define AWUPR Dividing factor explained below:
AWUPR[7:0] Dividing factor Forbidden
Bits Reserved. AWUF Auto Wake Flag This hardware when module generates interrupt cleared software reading AWUCSR. Writing this does change value. interrupt occurred interrupt occurred AWUM Auto Wake Measurement This enables oscillator connects output inputcapture 12-bit Auto-Reload timer. This allows timer used measure oscillator dispersion then compensate this dispersion providing right value AWUPRE register. Measurement disabled Measurement enabled AWUEN Auto Wake From Halt Enabled This enables Auto Wake From Halt feature: once HALT mode entered, AWUFH wakes microcontroller after time delay dependent prescaler value. cleared software. AWUFH (Auto Wake From Halt) mode disabled AWUFH (Auto Wake From Halt) mode enabled AWUFH PRESCALER REGISTER (AWUPR) Read /Write Table Register Reset ValueAddress (Hex.) 0049h 004Ah Register Label
mode, period that stays Halt Mode (tAWU Figure page defined
AWUPR RCSTRT AWURC
This prescaler register programmed modify time that stays Halt mode before waking automatically. Note: written AWUPR, depending product, interrupt generated immediately after HALT instruction, AWUPR remains inchanged.
AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Reset Value AWUCSR AWUF AWUM AWUEN Reset Value
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PORTS
10.1 INTRODUCTION ports allow data transfer. port contain pins. Each programmed independently either digital input digital output. addition, specific pins have several other functions. These functions include external interrupt, alternate signal input/output onchip peripherals analog input. 10.2 FUNCTIONAL DESCRIPTION Data Register (DR) Data Direction Register (DDR) always associated with each port. Option Register (OR), which allows input/output options, implemented. following description takes into account register. Refer Port Configuration table device specific information. programmed using corresponding bits DDR, registers: corresponding port. Figure shows generic block diagram. 10.2.1 Input Modes Clearing DDRx selects input mode. this mode, reading returns digital value from that pin. available, different input modes configured software: floating pull-up. Refer Port Implementation section configuration. Notes: Writing modifies latch value does change state input pin. read/modify/write instructions (BSET/BRES) modify register. External Interrupt Function Depending device, setting while input mode configure input with interrupt. this configuration, signal edge level input generates interrupt request corresponding interrupt vector (eix). Falling rising edge sensitivity programmed independently each interrupt vector. External Interrupt Control Register (EICR) Miscellaneous Register controls this sensitivity, depending device. device have external interrupts. Several pins tied external interrupt vector. Refer Description which ports have external interrupts. several interrupt pins same interrupt vector selected simultaneously, they logically combined. this reason interrupt pins tied low, mask others. External interrupts hardware interrupts. Fetching corresponding interrupt vector automatically clears request latch. Modifying sensitivity bits will clear pending interrupts. 10.2.2 Output Modes Setting DDRx selects output mode. Writing bits applies digital value through latch. Reading bits returns previously stored value. available, different output modes selected software: push-pull opendrain. Refer Port Implementation section configuration. Value Output StatuDR Push-Pull Open-Drain Floating
10.2.3 Alternate Functions Many ST7s I/Os have more alternate functions. These include output signals from, input signals on-chip peripherals. Device Description table describes which peripheral signals input/output which ports. signal coming from on-chip peripheral output I/O. this, enable on-chip peripheral output (enable peripheral's control register). peripheral configures output takes priority over standard programming. I/O's state readable addressing corresponding data register. Configuring floating enables alternate function input. recommended configure pull-up this will increase current consumption. Before using alternate input, configure without interrupt. Otherwise spurious interrupts occur. Configure input floating on-chip peripheral signal which input output. Caution: I/Os which configured both analog digital alternate function need special attention. user must control peripherals that signals arrive same time same pin. external clock used, only clock alternate function should employed that other alternate function.
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PORTS (Cont'd) Figure Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT
From on-chip peripheral
P-BUFFER (see table below) PULL-UP (see table below)
ALTERNATE ENABLE
PULL-UP CONDITION
DATA
implemented
N-BUFFER CMOS SCHMITT TRIGGER
DIODES (see table below) ANALOG INPUT
ALTERNATE INPUT
Combinational Logic on-chip peripheral
EXTERNAL INTERRUPT REQUEST (eix)
SENSITIVITY SELECTION
FROM OTHER BITS Note: Refer Port Configuration
table device specific information.
Table Port Mode OptionConfiguration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up P-Buffer Diodes
Output
(see note)
Legend: implemented implemented activated implemented activated
Note: diode implemented true open drain pads. local protection between implemented protect device against positive stress.
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PORTS (Cont'd) Table ConfigurationHardware Configuration
NOTE PULL-UP CONDITION REGISTER ACCESS
REGISTER
DATA
INPUT
FROM OTHER PINS INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION
ALTERNATE INPUT on-chip peripheral EXTERNAL INTERRUPT SOURCE (eix)
ANALOG INPUT
OPEN-DRAIN OUTPUT
NOTE REGISTER ACCESS
REGISTER
DATA
PUSH-PULL OUTPUT
NOTE
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT From on-chip periphera
Notes: When port input configuration associated alternate function enabled output, reading register will read alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content. true open drain, these elements implemented.
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PORTS (Cont'd) Analog alternate function Configure floating input input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail, connected input. Analog Recommendations change voltage level loading while conversion progress. have clocking pins located close selected analog pin. WARNING: analog input voltage level must within limits stated absolute maximum ratings. 10.3 PORT IMPLEMENTATION hardware implementation each port depends settings registers specific port features such input open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they present unwanted side-effects such spurious interrupt generation.
Figure Interrupt Port State Transition01
INPUT floating/pull-up interrupt
INPUT floating (reset state)
OUTPUT open-drain
OUTPUT push-pull
DDR,
10.4 UNUSED PINS Unused pins must connected fixed voltage levels. Refer Section 13.8. 10.5 POWER MODES
Mode WAIT HALT Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from HALT mode.
10.6 INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with registers register cleared (RIM instruction).
Interrupt Event External interrupt selected external event Enable Event Control Flag DDRx Exit from Wait Exit from Halt
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PORTS (Cont'd) 10.7 DEVICE-SPECIFIC PORT CONFIGURATION port register configurations summarised follows. Standard Ports PA7:0, PB6:0
MODE floating input pull-up input open drain output push-pull output
Interrupt Ports Ports where external interrupt capability selected using EISR register
MODE floating input pull-up interrupt input open drain output push-pull output
Table Port Configuration (Standard ports)
Port
Port Port
name
PA7:0 PB6:0
Input
floating floating
Output
pull-up pull-up
open drain open drain
push-pull push-pull
Note: ports where external interrupt capability selected using EISR register, configuration will follows:
Port
Port Port
name
PA7:0 PB6:0
Input
floating floating
Output
pull-up interrupt pull-up interrupt
open drain open drain
push-pull push-pull
Table Port Register Reset ValueAddress (Hex.) 0000h 0001h 0002h 0003h 0004h 0005h Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value PBDR Reset Value PBDDR Reset Value PBOR Reset Value
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ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction Watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared. 11.1.2 Main Features Programmable free-running downcounter increments 16000 cycles) Programmable reset Reset watchdog activated) when reaches zero Figure Watchdog Block Diagram
RESET
Optional reset HALT instruction (configurable option byte) Hardware Watchdog selectable option byte
11.1.3 Functional Description counter value stored register (bits T[6:0]), decremented every 16000 machine cycles, length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit timer (bits T[6:0]) rolls over from becomes cleared), initiates reset cycle pulling reset typically 36µs.
WATCHDOG CONTROL REGISTER (CR) WDGA
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷16000
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WATCHDOG TIMER (Cont'd) application program must write register regular intervals during normal operation prevent reset. This downcounter freerunning: counts down even watchdog disabled. value stored register must between (see Table .Watchdog Timing): WDGA (watchdog enabled) prevent generating immediate reset T[5:0] bits contain number increments which represents time delay before watchdog produces reset. Following reset, watchdog disabled. Once activated cannot disabled, except reset. used generate software reset (the WDGA cleared). watchdog activated, HALT instruction will generate Reset. Table 12.Watchdog Timing
fCPU 8MHz Counter Code [ms] [ms]
Notes: timing variation shown Table unknown status prescaler when writing register. number clock cycles applied during RESET phase (256 4096) must taken into account addition these timings. 11.1.4 Hardware Watchdog Option Hardware Watchdog selected option byte, watchdog always active WDGA used. Refer Option Byte description section page 132. 11.1.4.1 Using Halt Mode with (WDGHALT option) Halt mode with Watchdog enabled option byte watchdog reset HALT instruction), recommended before executing HALT instruction refresh counter, avoid unexpected reset immediately after waking microcontroller. Same behavior active-halt mode.
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WATCHDOG TIMER (Cont'd) 11.1.5 Interrupts None. 11.1.6 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
WDGA
T[6:0] 7-bit timer (MSB LSB). These bits contain decremented value. reset produced when rolls over from becomes cleared).
WDGA Activation bit. This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled Note: This used hardware watchdog option enabled option byte.
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WATCHDOG TIMER (Cont'd) Table Watchdog Timer Register Reset ValueAddress (Hex.) 002Eh Register Label WDGCR Reset Value WDGA
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11.2 12-BIT AUTORELOAD TIMER (AT2) 11.2.1 Introduction 12-bit Autoreload Timer used general-purpose timing functions. based freerunning 12-bit upcounter with input capture register four output channels. There external pins: Four outputs ATIC Input Capture function BREAK forcing break condition outputs 11.2.2 Main Features 12-bit upcounter with 12-bit autoreload register (ATR) Figure Block Diagram
ATIC ATICR ATCSR fLTIMER timebase 8MHz) fCPU ICIE OVFIE CMPIE INTERRUPT REQUEST 12-BIT INPUT CAPTURE REGISTER INTERRUPT REQUEST INTERRUPT REQUEST
Maskable overflow interrupt Generation four independent PWMx signals Frequency 2KHz-4MHz fCPU) Programmable duty-cycles Polarity control Programmable output modes Maskable Compare interrupt Input Capture 12-bit input capture register (ATICR) Triggered rising falling edges Maskable interrupt
CMPF0 CMPF1 CMPF2 CMPF3 fCOUNTER CNTR 12-BIT UPCOUNTER
12-BIT AUTORELOAD REGISTER
Preload
Preload Event TRAN=1
CMPFx COMPPARE
GENERATION
fPWM POLARITY
OUTPUT CONTROL
DCR0H
DCR0L
PWMx
12-BIT DUTY CYCLE VALUE (shadow) Channel
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12-BIT AUTORELOAD TIMER (Cont'd) 11.2.3 Functional Description Mode This mode allows four Pulse Width Modulated signals generated PWMx output pins. PWMx output signals enabled disabled using bits PWMCR register. Frequency Duty Cycle four signals have same frequency (fPWM) which controlled counter period register value. fPWM fCOUNTER (4096 ATR) Following above formula, fCOUNTER MHz, maximum value fPWM (ATR register value 4092), minimum value (ATR register value fCOUNTER Mhz, maximum value fPWM (ATR register value 4094),the minimum value (ATR register value Note: maximum value 4094 because must lower than value which must 4095 this case. reset, counter starts counting from When upcounter overflow occurs (OVF event), preloaded Duty cycle values transferred Duty Cycle registers PWMx signals high level. When upcounter matches DCRx value PWMx signals level. obtain signal PWMx pin, Figure Function
4095 DUTY CYCLE REGISTER (DCRx)
contents corresponding DCRx register must greater than contents register. polarity bits used invert four output signals. inversion synchronized with counter overflow TRAN TRANCR register (reset value). Figure Figure Inversion Diagram
inverter PWMx PWMx
PWMxCSR Register
TRAN TRANCR Register counter overflow
maximum available resolution PWMx duty cycle Resolution (4096 ATR) Note: maximum resolution (1/4096), register must With this maximum resolution, 100% obtained changing polarity.
COUNTER
AUTO-RELOAD REGISTER (ATR)
PWMx OUTPUT
WITH OE=1 OPx=0 WITH OE=1 OPx=1
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12-BIT AUTORELOAD TIMER (Cont'd) Figure Signal from 100% Duty Cycle
fCOUNTER ATR= FFDh COUNTER PWMx OUTPUT WITH MOD00=1 OPx=0 FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh
DCRx=000h DCRx=FFDh DCRx=FFEh
PWMx OUTPUT WITH MOD00=1 OPx=1
DCRx=000h
Output Compare Mode This mode always available. this function, load 12-bit value DCRxH DCRxL registers. When 12-bit upcounter (CNTR) reaches value stored DCRxH DCRxL registers, CMPF PWMxCSR register interrupt request generated CMPIE set. Note: output compare function only available DCRx values other than (reset value). Break Function break function used perform emergency shutdown power converter. break function activated external BREAK (active low). order BREAK must previously enabled software setting BPEN BREAKCR register.
When level detected BREAK pin, break function activated. Software activate break function without using BREAK pin. When break function activated =1): break pattern (PWM[3:0] bits BREAKCR) forced directly PWMx output pins (after inverter). 12-bit counter reset value. ARR, DCRx corresponding shadow registers their reset values. PWMCR register reset. When break function deactivated after applying break goes from software): control outputs transferred port registers.
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Figure Block Diagram Break Function
BREAK (Active Low)
BREAKCR Register BPEN PWM3 PWM2 PWM1 PWM0
PWM0 PWM1 PWM2
PWM0 PWM1 PWM2 PWM3 (Inverters) Note: BREAK value latched bit. When set: counter Reset value DCRx Reset value Mode Reset value
PWM3
11.2.3.1 Input Capture 12-bit ATICR register used latch value 12-bit free running upcounter after rising falling edge detected ATIC pin. When input capture occurs, ATICR register contains value Figure Input Capture Timing Diagram
fCOUNTER
free running upcounter. interrupt generated ICIE set. reset reading ATICR register when set. ATICR read only register always contains free running upcounter value which corresponds most recent input capture. further input capture inhibited while set.
COUNTER
ATIC INTERRUPT FLAG REGISTER ATICR READ INTERRUPT
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12-BIT AUTORELOAD TIMER (Cont'd) 11.2.4 Power Modes Mode Description input frequency divided SLOW WAIT effect timer timer halted except CK0=1, ACTIVE-HALT CK1=0 OVFIE=1 HALT timer halted 11.2.5 InterruptInterrupt Event1) Overflow Event Event Event Enable Exit Event Control from Flag Wait OVIE Exit Exit from from ActiveHalt Halt Yes2)
event mapped separate vector (see Interrupts chapter). They generate interrupt enable ATCSR register interrupt mask register reset (RIM instruction). Note Only CK0=1 CK1=0
ICIE CMPF0 CMPIE
Note events connected same interrupt vector.
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12-BIT AUTORELOAD TIMER (Cont'd) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read Write Reset Value: 0x00 0000 (x0h)
ICIE OVFIE CMPIE
Overflow Flag. This hardware cleared software reading TCSR register. indicates transition counter from value. counter overflow occurred Counter overflow occurred
Reserved.
OVFIE Overflow Interrupt Enable. This read/write software cleared hardware after reset. interrupt disabled. interrupt enabled.
Input Capture Flag. This hardware cleared software reading ATICR register read access ATICRH ATICRL will clear this flag). Writing this does change value. input capture input capture occurred
CMPIE Compare Interrupt Enable. This read/write software cleared hardware after reset. used mask interrupt generated when CMPF set. CMPF interrupt disabled. CMPF interrupt enabled.
ICIE Interrupt Enable. This cleared software. Input capture interrupt disabled Input capture interrupt enabled
COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (000h)
CNTR CNTR CNTR9 CNTR8
Bits CK[1:0] Counter Clock Selection. These bits cleared software cleared hardware after reset. They select clock frequency counter. change becomes effective after overflow.
Counter Clock Selection fLTIMER timebase MHz) fCPU
COUNTER REGISTER (CNTRL) Read only Reset Value: 0000 0000 (000h)
CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0
Note mode available this frequency. Note ATICR counter return inaccurate results when read. therefore recommended Input Capture mode this frequency.
Bits 15:12 Reserved. Bits 11:0 CNTR[11:0] Counter Value. This 12-bit register read software cleared hardware after reset. counter incremented continuously soon counter clok selected. obtain 12-bit value, software should read counter value consecutive read operations, first. When counter overflow occurs, counter restarts from value specified register.
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12-BIT AUTORELOAD TIMER (Cont'd) AUTORELOAD REGISTER (ATRH) Read Write Reset Value: 0000 0000 (00h)
ATR11 ATR10 ATR9 ATR8 CMPFx
PWMx CONTROL STATUS REGISTER (PWMxCSR) Read Write Reset Value: 0000 0000 (00h)
AUTORELOAD REGISTER (ATRL) Read Write Reset Value: 0000 0000 (00h)
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Bits 7:2= Reserved, must kept cleared. PWMx Output Polarity. This read/write software cleared hardware after reset. This selects polarity signal. signal inverted. signal inverted. CMPFx PWMx Compare Flag. This hardware cleared software reading PWMxCSR register. indicates that upcounter value matches DCRx register value. Upcounter value does match value. Upcounter value matches value.
Bits 11:0 ATR[11:0] Autoreload Register. This 12-bit register which written software. register value automatically loaded into upcounter when overflow occurs. register value used frequency.
OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h)
BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h)
Bits OE[3:0] PWMx output enable. These bits cleared software cleared hardware after reset. mode disabled. PWMx Output Alternate Function disabled (I/O free general purpose I/O) mode enabled
BPEN
PWM3
PWM2
PWM1
PWM0
Bits Reserved. Forced hardware Break Active. This read/write software, cleared hardware after reset hardware when BREAK low. activates/deactivates Break function. Break active Break active
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12-BIT AUTORELOAD TIMER (Cont'd) BPEN Break Enable. This read/write software cleared hardware after Reset. Break disabled Break enabled PWM[3:0] Break Pattern. These bits read/write software cleared hardware after reset. They used force four PWMx output signals into stable state when Break function active.
INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h)
ICR11 ICR10 ICR9 ICR8
INPUT CAPTURE REGISTER (ATICRL) Read only Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read Write Reset Value: 0000 0000 (00h)
DCR11 DCR10 DCR9
Bits 15:12 Reserved.
DCR8
PWMx DUTY CYCLE REGISTER (DCRxL) Read Write Reset Value: 0000 0000 (00h)
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Bits 11:0 ICR[11:0] Input Capture Data. This 12-bit register which readable software cleared hardware after reset. ATICR register contains captured value 12-bit CNTR register when rising falling edge occurs ATIC pin. Capture will only performed when flag cleared. TRANSFER CONTROL REGISTER (TRANCR) Read/Write Reset Value: 0000 0001 (01h)
Bits 15:12 Reserved. Bits 11:0 DCR[11:0] PWMx Duty Cycle Value This 12-bit value written software. definesthe duty cycle corresponding output signal (see Figure 35). mode (OEx=1 PWMCR register) DCR[11:0] bits define duty cycle PWMx output signal (see Figure 35). Output Compare mode, they define value compared with 12-bit upcounter value.
TRAN
Bits Reserved. Forced hardware TRAN Transfer enable This read/write software, cleared hardware after each completed transfer hardware after reset. allows value DCRx registers transferred DCRx shadow registers after next overflow event. bits transferred shadow bits same way.
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12-BIT AUTORELOAD TIMER (Cont'd) Table Register Reset ValueAddress (Hex.) Register Label ATCSR Reset Value CNTRH Reset Value CNTRL Reset Value ATRH Reset Value ATRL Reset Value PWMCR Reset Value PWM0CSR Reset Value PWM1CSR Reset Value PWM2CSR Reset Value PWM3CSR Reset Value DCR0H Reset Value DCR0L Reset Value DCR1H Reset Value DCR1L Reset Value DCR2H Reset Value DCR2L Reset Value DCR3H Reset Value DCR3L Reset Value ATICRH Reset Value ATICRL Reset Value CNTR8 ATR6 DCR6 DCR6 DCR6 DCR6 ICR6 ICIE CNTR7 ATR5 DCR5 DCR5 DCR5 DCR5 ICR5 CNTR6 ATR4 DCR4 DCR4 DCR4 DCR4 ICR4 CNTR11 CNTR3 ATR11 ATR3 DCR11 DCR3 DCR11 DCR3 DCR11 DCR3 DCR11 DCR3 ICR11 ICR3 CNTR10 CNTR2 ATR10 ATR2 DCR10 DCR2 DCR10 DCR2 DCR10 DCR2 DCR10 DCR2 ICR10 ICR2 OVFIE CNTR9 CNTR1 ATR9 ATR1 DCR9 DCR1 DCR9 DCR1 DCR9 DCR1 DCR9 DCR1 ICR9 ICR1 CMPIE CNTR8 CNTR0 ATR8 ATR0 CMPF0 CMPF1 CMPF2 CMPF3 DCR8 DCR0 DCR8 DCR0 DCR8 DCR0 DCR8 DCR0 ICR8 ICR0
CNTR7 ATR7 DCR7 DCR7 DCR7 DCR7 ICR7
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Address (Hex.)
Register Label TRANCR Reset Value BREAKCR Reset Value
TRAN PWM0
BPEN
PWM3
PWM2
PWM1
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11.3 LITE TIMER (LT2) 11.3.1 Introduction Lite Timer used general-purpose timing functions. based free-running 8bit upcounters, 8-bit input capture register. 11.3.2 Main Features Realtime Clock 8-bit upcounter timebase period fOSC) Figure Lite Timer Block Diagram
fOSC/32 LTCNTR 8-bit TIMEBASE COUNTER LTCSR2
TB2IE TB2F
8-bit upcounter with autoreload programmable timebase period from 1.024ms increments fOSC) Maskable timebase interrupts Input Capture 8-bit input capture register (LTICR) Maskable interrupt with wakeup from Halt Mode capability
LTTB2 Interrupt request
LTARR 8-bit AUTORELOAD REGISTER fLTIMER 12-bit TImer
8-bit TIMEBASE COUNTER fLTIMER
Timebase 8MHz fOSC)
LTICR LTIC 8-bit INPUT CAPTURE REGISTER LTCSR1
ICIE
TB1IE TB1F
LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST
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LITE TIMER (Cont'd) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 8-bit value Counter cannot read written software. After reset, starts incrementing from frequency fOSC/32. overflow event occurs when counter rolls over from 00h. fOSC MHz, then time period between counter overflow events This period doubled setting LTCSR1 register. When Counter overflows, TB1F hardware interrupt request generated TB1IE set. TB1F cleared software reading LTCSR1 register. 11.3.3.2 Timebase Counter Counter 8-bit autoreload upcounter. read accessing LTCNTR register. After reset, increments frequency fOSC/32 starting from value stored LTARR register. counter overflow event occurs when counter rolls over from Figure Input Capture Timing Diagram.
8MHz fOSC)
fCPU OSC/32 CLEARED READING LTIC REGISTER
LTARR reload value. Software write value anytime LTARR register, this value will automatically loaded counter when next overflow occurs. When Counter overflows, TB2F LTCSR2 register hardware interrupt request generated TB2IE set. TB2F cleared software reading LTCSR2 register. 11.3.3.3 Input Capture 8-bit input capture register used latch free-running upcounter (Counter after rising falling edge detected ICAP1 pin. When input capture occurs, LTICR1 register contains Counter interrupt generated ICIE set. cleared reading LTICR register. LTICR read-only register always contains data from last input capture. Input capture inhibited set.
8-bit COUNTER
LTIC FLAG LTICR REGISTER
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LITE TIMER (Cont'd) opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant with value 0x8E. HALT instruction clears register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt). 11.3.4 Power Modes Description effect Lite timer SLOW (this peripheral driven directly OSC/32) WAIT effect Lite timer ACTIVE-HALT effect Lite timer HALT Lite timer stops counting 11.3.5 InterruptInterrupt Event Enable Event Control Flag TB1IE TB2IE ICIE Exit from Wait Exit from Active Halt Exit from Halt
11.3.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR2) Read Write Reset Value: 0x00 0000 (x0h)
TB2IE TB2F
Bits Reserved, must kept cleared. TB2IE Timebase Interrupt enable. This cleared software. Timebase (TB2) interrupt disabled Timebase (TB2) interrupt enabled TB2F Timebase Interrupt Flag This hardware cleared software reading LTCSR register. Writing this effect. Counter overflow Counter overflow occurred LITE TIMER AUTORELOAD (LTARR) Read Write Reset Value: 0000 0000 (00h)
Mode
Timebase TB1F Event Timebase TB2F Event Event
REGISTER
Note: TBxF interrupt events connected separate interrupt vectors (see Interrupts chapter). They generate interrupt enable LTCSR1 LTCSR2 register interrupt mask register reset (RIM instruction).
Bits AR[7:0] Counter Reload Value. These bits register read/write software. LTARR value automatically loaded into Counter (LTCNTR) when overflow occurs.
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LITE TIMER (Cont'd) LITE TIMER COUNTER (LTCNTR) Read only Reset Value: 0000 0000 (00h)
CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0
Timebase period selection. This cleared software. Timebase period tOSC 8000 (1ms MHz) Timebase period tOSC 16000 (2ms MHz) TB1IE Timebase Interrupt enable. This cleared software. Timebase (TB1) interrupt disabled Timebase (TB1) interrupt enabled TB1F Timebase Interrupt Flag. This hardware cleared software reading LTCSR register. Writing this effect. counter overflow counter overflow occurred Bits Reserved
Bits CNT[7:0] Counter Reload Value. This register read software. LTARR value automatically loaded into Counter (LTCNTR) when overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read Write Reset Value: 0x00 0000 (x0h)
ICIE TB1IE TB1F
ICIE Interrupt Enable. This cleared software. Input Capture (IC) interrupt disabled Input Capture (IC) interrupt enabled Input Capture Flag. This hardware cleared software reading LTICR register. Writing this does change value. input capture input capture occurred Note: After reset, software must initialise reading LTICR register
LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits ICR[7:0] Input Capture Value These bits read software cleared hardware after reset. LTCSR cleared, value 8-bit up-counter will captured when rising falling edge occurs LTIC pin.
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LITE TIMER (Cont'd) Table Lite Timer Register Reset ValueAddress (Hex.) Register Label LTCSR2 Reset Value LTARR Reset Value LTCNTR Reset Value LTCSR1 Reset Value LTICR Reset Value TB2IE CNT1 ICR1 TB2F CNT0 ICR0
CNT7 ICIE ICR7
CNT6 ICR6
CNT5 ICR5
CNT4 TB1IE ICR4
CNT3 TB1F ICR3
CNT2 ICR2
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11.4 DALI COMMUNICATION MODULE 11.4.1 Introduction DALI Communication Module (DCM) serial communication circuit designed controllable electronic ballasts. Ballasts devices used provide required starting voltage operating current fluorescent, mercury, other electric-discharge lamps. supports DALI (Digital Addressable Lighting Interface) communications standard (IEC standard). 11.4.2 Main Features 8-bit forward address register addressing digital ballasts transmission rate ±10% 8-bit forward backward data registers bi-directional communications Maskable interrupt
Figure Dali Communication Module Block Diagram
4-bit sample clock counter fCPU 1/16 16-bit Shift Register 4-bit Pre-shift Register fDALI
DALIOUT DALIIN
8-bit DCMCLK Register 8-bit DCMFA Register 8-bit DCMFD Register 8-bit DCMBD Register fCPU Arbitration
Edge Detector
Error Detection
DCMCSR Register
Interrupt Request DCMCR Register
DCME
Note: 4-bit preshift register always active, except when Halt mode DCME
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DALI COMMUNICATION MODULE (Cont'd) 11.4.3 DALI Standard Protocol DALI protocol uses bi-phase Manchester asynchronous serial data format. bits frame bi-phase encoded except stop bits. transmission rate about kHz. biphase period 833.33 ±10%. forward frame consists bi-phase encoded bits: start (0->1: logical '1') address byte (8-bit address) data byte (8-bit data) high level stop bits change phase) backward frame consists bi-phase encoded bits: start (0->1: logical '1') data byte (8-bit data) high level stop bits change phase)
forward frame consists bi-phase encoded bits: start (logical '1'), address byte data byte. frame terminated stop bits (idle). stop bits contain change phase. backward frame consists bi-phase encoded bits: start (logical '1') data byte. frame terminated stop bits (idle). stop bits contain change phase. transmission rate, expressed bandwidth, specified forward channel backward channel. settling time between subsequent forward frames 9.17 (minimum). settling time between forward backward frames between 2.92 9.17 backward frame been started after 9.17 this interpreted answer". event code violation, frame ignored. After code violation occurred, system ready again data reception.
Figure DALI Standard Frame
FORWARD FRAME start address byte data byte stop bits
start
BACKWARD FRAME data byte
stop bits
BI-PHASE LEVELS Logical Logical
833.33 ±10%
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DALI COMMUNICATION MODULE (Cont'd) 11.4.4 General Description able receive transmit serial DALI signal using 16-bit shift register, edge detector, several data/control registers arbitration logic. receives DALI standard signal from lighting control network, checks errors loads address/data bytes "forward frame" corresponding DCMFA/DCMFD registers sends back data byte "backward frame" (written software DCMBD register) DALI standard format. data rate changed writing DCMCLK register fDATA fDALI). DATA fCPU/[(N+1)*16] DALI standard data rate fDALI kHz. integer value DCMCLK register. Following above formula, fCPU MHz, integer value DCMCLK register "207". biphase period 833.33 ±10%. polarity bi-phase start configurable. start logical '1'. polarity stop bits configurable. stop bits high level. error detected during reception, frame will ignored will return Receive state. 11.4.5 Functional Description user must write DCMCLK register select data rate according DALI signal frequency. After Reset, Receive state waits bi-phase start (logical '1') "forward frame". checks data format "forward frame" with 4-bit pre-shift register. error
occurs during reception, will skip data return Receive state. there error "forward frame", data will shifted Most Significant Bit-first into 16bit shift register. address byte data byte will loaded corresponding DCMFA DCMFD registers. will send interrupt signal setting DCMCSR register. software receives interrupt signal from DCM, reads DCMFA DCMFD registers. Depending command, able send back receive data. interrupt routine, either before same time bit. software asks send back "backward frame", software must first write DCMBD register switch Transmit state setting bits DCMCR register during interrupt routine. DCMBD register will shifted from 16-bit shift register DALI format, Most Significant Bit-first. When "backward frame" been transmitted, will send interrupt signal setting DCMCSR register. software asks receive "forward frame", software must switch Receive state clearing setting DCMCR register during interrupt routine. interrupt flag DCMCSR register, software must DCMCR register allow perform next DALI signal reception transmission. DALIIN signal always taken into account 4-bit pre-shifter.
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DALI COMMUNICATION MODULE (Cont'd) 11.4.6 Special Functions 11.4.6.1 Forced Transmission (Test mode) must receive "forward frame" before sending back "backward frame". possible force into Transmit state setting DCMCR register. DCMBD register will shifted DALI format, Most Significant Bit-first. Preferably before forcing into Transmit state, user should reset/set DCME DCMCR register. interrupt flag will generated after forced transmission (the DCMCSR register). Procedure: Reset DCME DCMCR register. Write backward value DCMBD register. both DCME bits DCMCR register. When interrupt generated (end transmission, DCMCSR register), DCMCR register re-start transmission. return normal DALI communications, reset/set DCME reset DCMCR register. 11.4.6.2 Normal Transmission After "forward frame" reception, software must write backward data byte DCMBD register both bits DCMCR register start transmission. possible send backward frame just after having sent backward frame (see DALI standard protocol).
11.4.6.3 Enable user enable disable writing DCME DCMCR register. This also used reset entire internal finite state machine. 11.4.7 DALI Interface Failure DALI input signal level 2-bit period (1.66 ms), then generates error flag setting DCMCSR register. This cleared reading DCMCSR register. interface failure detected Receive state only. 11.4.8 Power Modes Mode WAIT HALT ACTIVE HALT Description effect registers frozen effect
11.4.9 InterruptInterrupt Event Event Flag Enable Control Exit from Wait Exit from Halt
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DALI COMMUNICATION MODULE (Cont'd) 11.4.10 Bi-phase Detection clock used sampling DALI signal programmed DCMCLK register. Each phase sampled times. phase level determined three sample clock pulses (pulses 6,7,8). phase levels biphase shifted into 4-bit pre-shift register sample clock pulse. Figure DALI Signal Sampling DALI Signal
Only second phase level bi-phase shifted into 16-bit shifter. 4-bit pre-shifter used detect errors received frame. When change phase detected (edge trigger), 4-bit sample clock counter (integer range to15) cleared.
4-bit sample clock counter
Phase Detector
Shifter Clock
4-bit Pre-shifter
16-bit Shifter xxxx
xxx1
Edge Trigger
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DALI COMMUNICATION MODULE (Cont'd) example shown Figure DCMCSR[3:0] bits updated automatically each edge trigger (DALI signal change phase). same time value 4-bit sample clock Figure Example DALI Signal Sampling 833.33µs DALI Signal
counter reset. reading DCMCSR[3:0] bits software detect changes DALI signal pulse length.
tCPU Edge Trigger
tCPU
tCPU
4-bit sample clock counter (/16 divider) 0000 0001 1111 0000 xxxx 0000
DCMCSR[3:0] bits Legend: tCPU= fCPU
0000
1111
xxxx
(DCMCLK integer value+1) tCPU Example: fDALI= fCPU= (DCMCLK) tCPU 125ns (208 125ns)
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DALI COMMUNICATION MODULE (Cont'd) 11.4.11 Register Description DATA RATE CONTROL REGISTER (DCMCLK) Read Write Reset Value: 0000 0000 (00h)
FORWARD DATA REGISTER (DCMFD) Read only Reset Value: 0000 0000 (00h)
Bits DCMCLK[7:0] Clock Prescaler. These bits set/cleared software cleared hardware after reset. These bits used tuning DALI data rate. fDATA CPU/[(N+1)*16] where integer value DCMCLK register. FORWARD ADDRESS REGISTER (DCMFA) Read only Reset Value: 0000 0000 (00h)
Bits DCMFD[7:0] Forward Data. These bits read software set/cleared hardware. These bits used store "forward frame" data byte. BACKWARD DATA REGISTER (DCMBD) Read Write Reset Value: 0000 0000 (00h)
Bits DCMFA[7:0] Forward Address. These bits read software set/cleared hardware. These bits used store "forward frame" address byte.
Bits DCMBD[7:0] Backward Data. These bits set/cleared software cleared hardware after reset. These bits used store "backward frame" data byte. sofware writes this register before enabling transmit operation.
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DALI COMMUNICATION MODULE (cont'd) CONTROL REGISTER (DCMCR) Read Write Reset Value: 0000 0000 (00h)
DCME
CONTROL/STATUS REGISTER (DCMCSR) Read only (except Reset Value: 0000 0000 (00h)
Bits Reserved. Forced hardware DCME DALI Communication Enable. This set/cleared software cleared hardware after reset. When set, enables DALI communication. also resets entire internal finite state machine. enable receive/transmit enable receive/transmit Receive/Transmit Acknowledge. This reset hardware after been software. cleared after reset. This must set, after first DALI frame reception transmission, allow perform next DALI communication. acknowledge Acknowledge Receive/Transmit state. This set/cleared software cleared hardware after reset. This must after forward frame received, backward frame required. This must cleared after backward frame transmitted, forward frame required. Receive state Transmit state Force Transmit state. This set/cleared software cleared hardware after reset. When this set, forced into Transmit state. Preferably before forcing into Transmit state, user should reset DCME DCMCR register. interrupt flag (ITF) generated after forced transmission. forced Transmit state forced Transmit state Interrupt Enable. This set/cleared software cleared hardware after reset. When set, this allows generation DALI interrupts. interrupt (ITF) disabled interrupt (ITF) enabled Interrupt Flag. (Read only) This set/cleared hardware read software. This after "backward frame" transmission "forward frame" reception. cleared setting DCMCR register. after forced transmission (see bit). reception/transmission reception/transmission Error Flag. (Read only) This set/cleared hardware. cleared reading DCMCSR register. This when either DALI data format received wrong interface failure detected. data format error during reception Data format error during reception Receive/Transmit Flag. (Read only) This set/reset hardware read software. Transmit state Receive state Bits DCMCSR[3:0] Clock counter value. (Read only) These bits set/cleared hardware read software. value 4-bit sample clock counter (integer range 15). clock counter value loaded DCMCSR register when DALI change phase signal detected (edge trigger). Refer Figure
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Table Register Reset ValueAddress (Hex.) 0040h 0041h 0042h 0043h 0044h 0045h Register Label DCMCLK Reset Value DCMFA Reset Value DCMFD Reset Value DCMBD Reset Value DCMCR Reset Value DCMCSR Reset Value DCME
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11.5 SERIAL PERIPHERAL INTERFACE (SPI) 11.5.1 Introduction Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. system consist master more slaves system which devices either masters slaves. 11.5.2 Main Features Full duplex synchronous transfers lines) Simplex synchronous transfers lines) Master slave operation master mode frequencies (fCPU max.) fCPU/2 max. slave mode frequency Management software hardware Programmable clock polarity phase transfer interrupt flag Write collision, Master Mode Fault Overrun flags 11.5.3 General Description Figure shows serial peripheral interface (SPI) block diagram. There registers: Control Register (SPICR) Control/Status Register (SPICSR) Data Register (SPIDR) connected external devices through pins: MISO: Master Slave data MOSI: Master Slave data SCK: Serial Clock masters input slaves Slave select: This input signal acts `chip select' master communicate with slaves individually avoid contention data lines. Slave inputs driven standard ports master Device.
Figure Serial Peripheral Interface Block Diagram
Data/Address SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
SPIF WCOL MODF
SPICSR
Write
STATE CONTROL
SPIE
SPICR
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.3.1 Functional Description basic example interconnections between single master single slave illustrated Figure MOSI pins connected together MISO pins connected together. this data transferred serially between master slave (most significant first). communication always initiated master. When master device transmits data slave device MOSI pin, slave device reFigure Single Master/ Single Slave Application
SLAVE LSBit MISO MISO MSBit LSBit
sponds sending data master device MISO pin. This implies full duplex communication with both data data synchronized with same clock signal (which provided master device pin). single data line, MISO MOSI pins must connected each node this case only simplex communication possible). Four possible data/clock timing relationships chosen (see Figure master slave must programmed with same timing mode.
MASTER MSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
CLOCK GENERATOR
used managed software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.3.2 Slave Select Management alternative using control Slave Select signal, application choose manage Slave Select signal software. This configured SPICSR register (see Figure software management, external free other application uses internal signal level driven writing SPICSR register. Master mode: internal must held high continuously
Slave Mode: There cases depending data/clock timing relationship (see Figure 47): CPHA=1 (data latched clock edge): internal must held during entire transmission. This implies that single slave applications either tied VSS, made free standard managing function software (SSM= SSI=0 SPICSR register) CPHA=0 (data latched clock edge): internal must held during byte transmission pulled high between each byte allow slave write shift register. pulled high, Write Collision error will occur when slave writes shift register (see Section 11.5.5.3).
Figure Generic Timing Diagram
MOSI/MISO Master Slave CPHA=0) Slave CPHA=1)
Byte
Byte
Byte
Figure Hardware/Software Slave Select Management
external
internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.3.3 Master Mode Operation master mode, serial clock output pin. clock frequency, polarity phase configured software (refer description SPICSR register). Note: idle state must correspond polarity selected SPICSR register pulling CPOL=1 pulling down CPOL=0). operate master mode, perform following steps order SPICSR register written first, SPICR register setting taken into account): Write SPICSR register: Select clock frequency configuring SPR[2:0] bits. Select clock polarity clock phase configuring CPOL CPHA bits. Figure shows four possible configurations. Note: slave must have same CPOL CPHA settings master. Either clear high complete byte transmit sequence. Write SPICR register: MSTR bits Note: MSTR bits remain only high). transmit sequence begins when software writes byte SPIDR register. 11.5.3.4 Master Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MOSI most significant first. When data transfer complete: SPIF hardware interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF read SPIDR register. Note: While SPIF set, writes SPIDR register inhibited until SPICSR register read.
11.5.3.5 Slave Mode Operation slave mode, serial clock received from master device. operate slave mode: Write SPICSR register perform following actions: Select clock polarity clock phase configuring CPOL CPHA bits (see Figure 49). Note: slave must have same CPOL CPHA settings master. Manage described Section 11.5.3.2 Figure CPHA=1 must held continuously. CPHA=0 must held during byte transmission pulled between each byte slave write shift register. Write SPICR register clear MSTR enable functions. 11.5.3.6 Slave Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MISO most significant first. transmit sequence begins when slave device receives clock signal most significant data MOSI pin. When data transfer complete: SPIF hardware interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF set. write read SPIDR register. Notes: While SPIF set, writes SPIDR register inhibited until SPICSR register read. SPIF cleared during second transmission; however, must cleared before second SPIF order prevent Overrun condition (see Section 11.5.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.4 Clock Phase Clock Polarity Four possible timing relationships chosen software, using CPOL CPHA bits (See Figure 49). Note: idle state must correspond polarity selected SPICSR register pulling CPOL=1 pulling down CPOL=0). combination CPOL clock polarity CPHA (clock phase) bits selects data capture clock edge Figure Data Clock Timing Diagram
Figure shows transfer with four combinations CPHA CPOL bits. diagram interpreted master slave timing diagram where pin, MISO pin, MOSI directly connected between master slave device. Note: CPOL changed communication byte boundaries, must disabled resetting bit.
CPHA
(CPOL (CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
CPHA
(CPOL (CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
Note: This figure should used replacement parametric information. Refer Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.5 Error Flags 11.5.5.1 Master Mode Fault (MODF) Master mode fault occurs when master device pulled low. When Master mode fault occurs: MODF interrupt request generated SPIE set. reset. This blocks output from Device disables peripheral. MSTR reset, thus forcing Device into slave mode. Clearing MODF done through software sequence: read access SPICSR register while MODF set. write SPICR register. Notes: avoid conflicts application with multiple slaves, must pulled high during MODF clearing sequence. MSTR bits restored their original state during after this clearing sequence. Hardware does allow user MSTR bits while MODF except MODF clearing sequence. slave device, MODF set, multi master configuration Device slave mode with MODF set. MODF indicates that there might have been multi-master conflict allows software handle this using interrupt routine either perform reset return application default state.
11.5.5.2 Overrun Condition (OVR) overrun condition occurs, when master device sent data byte slave device cleared SPIF issued from previously transmitted byte. When Overrun occurs: interrupt request generated SPIE set. this case, receiver buffer contains byte sent after SPIF last cleared. read SPIDR register returns this byte. other bytes lost. cleared reading SPICSR register. 11.5.5.3 Write Collision Error (WCOL) write collision occurs when software tries write SPIDR register while data transfer taking place with external device. When this happens, transfer continues uninterrupted; software write will unsuccessful. Write collisions occur both master slave mode. also Section 11.5.3.2 Slave Select Management. Note: "read collision" will never occur since received data byte placed buffer which access always synchronous with operation. WCOL SPICSR register write collision occurs. interrupt generated when WCOL (the WCOL status flag only). Clearing WCOL done through software sequence (see Figure 50).
Figure Clearing WCOL (Write Collision Flag) Software Sequence Clearing sequence after SPIF (end data byte transfer) Step Read SPICSR
RESULT
Step
Read SPIDR
SPIF WCOL=0
Clearing sequence before SPIF (during data byte transfer) Step Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing SPIDR register instead reading does reset WCOL
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.5.5.4 Single Master Multimaster Configurations There types systems: Single Master System Multimaster System Single Master System typical single master system configured, using device master four devices slaves (see Figure 51). master device selects individual slave devices using four pins parallel port control four pins slave devices. pins pulled high during reset since master device ports will forced inputs that time, thus disabling slave devices. Note: prevent conflict MISO line master allows only active slave device during transmission.
more security, slave device respond master with received data byte. Then master will receive previous byte back from slave device MISO MOSI pins connected slave written SPIDR register. Other transmission security methods ports handshake lines data bytes with command fields. Multi-Master System multi-master system also configured user. Transfer master control could implemented using handshake method through ports exchange code messages through serial peripheral interface system. multi-master system principally handled
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