Mbit Boot Block) Supply Count Flash Memory SUPPLY VOLTAGE 3.6V Pr

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Mbit Boot Block) Supply Count Flash Memory SUPPLY VOLTAGE 3.6V Pr

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M50LPW116
Mbit Boot Block) Supply Count Flash Memory
SUPPLY VOLTAGE 3.6V Program, Erase Read Operations Fast Program Fast Erase INTERFACES Count (LPC) Standard Interface embedded operation with Chipsets. Address/Address Multiplexed (A/A Mux) Interface programming equipment compatibility. COUNT (LPC) HARDWARE INTERFACE MODE Signal Communication Interface supporting Read Write Operations Hardware Write Protect Pins Block Protection Register Based Read Write Protection Additional General Purpose Inputs platform design flexibility Synchronized with 33MHz clock BYTE PROGRAMMING TIME Single Byte Mode: 10µs (typical) Quadruple Byte Mode: 2.5µs (typical) MEMORY BLOCKS Boot Block Parameter Main Blocks PROGRAM/ERASE CONTROLLER Embedded Byte Program Block/Chip Erase algorithms Status Register Bits PROGRAM ERASE SUSPEND ELECTRONIC SIGNATURE Manufacturer Code: Device Code:
Figure Packages
TSOP40 20mm
April 2005
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TABLE CONTENTS
FEATURES SUMMARY Figure Packages DESCRIPTION Figure Figure Table Table Figure Table Logic Diagram (LPC Interface) Logic Diagram (A/A Interface) Signal Names (LPC Interface) Signal Names (A/A Interface) TSOP Connections Memory Identification Input Configuration
SIGNAL DESCRIPTIONS Count (LPC) Signal Descriptions Input/Output Communications (LAD0-LAD3). Input Communication Frame (LFRAME). Identification Inputs (ID0-ID3). General Purpose Inputs (GPI0-GPI4). Interface Configuration (IC). Interface Reset (RP). Reset (INIT). Clock (CLK). Block Lock (TBL). Write Protect (WP). Reserved Future (RFU). Table Block Addresses Address/Address Multiplexed (A/A Mux) Signal Descriptions Address Inputs (A0-A10). Data Inputs/Outputs (DQ0-DQ7). Output Enable (G). Write Enable (W). Row/Column Address Select (RC). Ready/Busy Output (RB). Supply Signal Descriptions Supply Voltage. Optional Supply Voltage. Ground. OPERATIONS. Count (LPC) Operations Read. Write. Abort. Standby.
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Reset. Block Protection. Table Read Field Definitions Figure Read Waveforms Table Write Field Definitions. Figure Write Waveforms Address/Address Multiplexed (A/A Mux) Operations. Read. Write. Output Disable. Reset. Table Operations Table Manufacturer Device Codes COMMAND INTERFACE Read Memory Array Command Read Status Register Command Read Electronic Signature Command Table Read Electronic Signature Program Command Quadruple Byte Program Command (A/A Mode). Chip Erase Command. Block Erase Command Clear Status Register Command Program/Erase Suspend Command Program/Erase Resume Command Table Commands STATUS REGISTER Program/Erase Controller Status (Bit Erase Suspend Status (Bit Erase Status (Bit Program Status (Bit Status (Bit Program Suspend Status (Bit Block Protection Status (Bit Reserved (Bit Table Status Register Bits COUNT (LPC) INTERFACE CONFIGURATION REGISTERS. Lock Registers Write Lock Read Lock Lock Down. General Purpose Input Register. Table Count Register Configuration
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Table Lock Register Definitions(1) Table General Purpose Input Register Definition(1). PROGRAM ERASE TIMES Table Program Erase Times. MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS. Table Operating Conditions Table Interface Measurement Conditions Table Interface Measurement Conditions Figure Interface Testing Input Output Waveforms Figure Interface Testing Input Output Waveform Table Impedance Table Characteristics. Figure Interface Clock Waveform Table Interface Clock Characteristics Figure 10.LPC Interface Signal Timing Waveforms Table Interface Signal Timing Characteristics Figure 11.Reset Waveforms Table Reset Characteristics. Figure 12.A/A Interface Read Waveforms Table Interface Read Characteristics Figure 13.A/A Interface Write Waveforms Table Interface Write Characteristics PACKAGE MECHANICAL Figure 14.TSOP40 lead Plastic Thin Small Outline, 10x20 Package Outline Table TSOP40 lead Plastic Thin Small Outline, 10x20 Package Mechanical Data. PART NUMBERING Table Ordering Information Scheme FLOWCHARTS PSEUDO CODES. Figure 15.Program Flowchart Pseudo Code Figure 16.Quadruple Byte Program Flowchart Pseudo Code (A/A Interface Only) Figure 17.Program Suspend Resume Flowchart Pseudo Code Figure 18.Chip Erase Flowchart Pseudo Code (A/A Interface Only) Figure 19.Block Erase Flowchart Pseudo Code Figure 20.Erase Suspend Resume Flowchart Pseudo Code REVISION HISTORY Table Revision History.
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DESCRIPTION
M50LPW116 Mbit (2Mb non-volatile memory that read, erased reprogrammed. These operations performed using single voltage (3.0 3.6V) supply. fast programming, fast erasing, optional power supply used reduce programming erasing times. memory divided into blocks that erased independently possible preserve valid data while data erased. Blocks protected individually (except Blocks which have global protection) prevent accidental Program Erase commands from modifying memory. Program Erase commands written Command Interface memory. on-chip Program/Erase Controller simplifies process programming erasing memory taking care special operations that required update memory contents. program erase operation detected error conditions identified. command required control memory consistent with JEDEC standards. M50LPW116 features asymmetrical block architecture. array blocks: Boot Block 16KBytes, Parameter Blocks 8KBytes, Main Block 32KBytes, Main Blocks 64KBytes Parameter Blocks 4KBytes. different interfaces supported memory. primary interface Count LPC) Standard Interface. This been designed remove need current Chipsets; M50LPW116 acts BIOS Count these Chipsets. secondary interface, Address/Address Multiplexed Mux) Interface, designed compatible with current Flash Programmers production line programming prior fitting Motherboard. memory offered TSOP40 20mm) package supplied with bits erased (set '1').
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Figure Logic Diagram (LPC Interface)
ID0-ID3 GPI0GPI4 LFRAME INIT
Table Signal Names (LPC Interface)
LAD0-LAD3 LFRAME ID0-ID3 Input/Output Communications Input Communication Frame Identification Inputs General Purpose Inputs Interface Configuration Interface Reset Reset Clock Block Lock Write Protect Reserved Future Use. Leave disconnected. Supply Voltage Optional Supply Voltage Fast Program Fast Erase Operations Ground Connected Internally
LAD0LAD3
GPI0-GPI4 INIT
M50LPW116
AI05466
Figure Logic Diagram (A/A Interface) Table Signal Names (A/A Interface)
Interface Configuration Address Inputs Data Inputs/Outputs Output Enable Write Enable Row/Column Address Select Ready/Busy Output Interface Reset Supply Voltage Optional Supply Voltage Fast Program Fast Erase Operations Ground Connected Internally
A0-A10 DQ0-DQ7
A0-A10 DQ0-DQ7
M50LPW116
AI05468
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Figure TSOP Connections
(VIH) (VIL) GPI4 GPI3 GPI2 GPI1 GPI0 LFRAME INIT LAD3 LAD2 LAD1 LAD0
M50LPW116
AI05467B
Table Memory Identification Input Configuration
Memory Number (Boot) floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating
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SIGNAL DESCRIPTIONS
There different interfaces available this part. active interface selected before power-up during Reset using Interface Configuration Pin, signals each interface discussed Count (LPC) Signal Descriptions section Address/Address Multiplexed (A/A Mux) Signal Descriptions section below. supply signals discussed Supply Signal Descriptions section below. Count (LPC) Signal Descriptions Count (LPC) Interface Figure Table address sequence bits long. M50LPW116 responds addresses mapped GByte memory space, from FFFF FFFFh. Address bits A31-A26 must A25-A23 A21, Table array access, register access. A20-A0 array addresses. Input/Output Communications (LAD0-LAD3). Input Output Communication with memory take place these pins. Addresses Data Read Write operations encoded these pins. Input Communication Frame (LFRAME). Input Communication Frame (LFRAME) signals start operation. When Input Communication Frame Low, VIL, rising edge Clock operation initiated. Input Communication Frame Low, VIL, during operation then operation aborted. When Input Communication Frame High, VIH, current operation proceeding idle. Identification Inputs (ID0-ID3). Identification Inputs (ID0-ID3) allow address memories bus. value addresses A21,A23A25 compared hardware strapping ID0-ID3 pins select which memory being addressed. address correspondent left floating driven Low, VIL; internal pull-down resistor included with value RIL. address correspondent must driven High, VIH; there will leakage current ILI2 through each when pulled VIH; Table convention boot memory must have ID0ID3 pins left floating driven Low, value A21,A23-A25 additional memories take sequential ID0-ID3 configuration, shown Table General Purpose Inputs (GPI0-GPI4). General Purpose Inputs used digital inputs read. General Purpose Input Register holds values these pins. pins must have stable data from before start cycle that reads General Purpose Input Register until after cycle complete. These pins must left float, they should driven Low, VIL, High, VIH. Interface Configuration (IC). Interface Configuration input selects whether Count (LPC) Address/Address Multiplexed (A/A Mux) Interface used. chosen interface must selected before power-up during Reset and, thereafter, cannot changed. state Interface Configuration, should changed during operation. select Count (LPC) Interface Interface Configuration should left float driven Low, VIL; select Address/Address Multiplexed (A/A Mux) Interface should driven High, VIH. internal pull-down resistor included with value RIL; there will leakage current ILI2 through each when pulled VIH; Table Interface Reset (RP). Interface Reset (RP) input used reset memory. When Interface Reset (RP) Low, VIL, memory Reset mode: outputs high impedance current consumption minimized. When High, VIH, memory normal operation. After exiting Reset mode, memory enters Read mode. Reset (INIT). Reset, INIT, used Reset memory when reset. behaves identically Interface Reset, internal Reset line logical (electrical AND) INIT. Clock (CLK). Clock, CLK, input used clock signals Input/Output Communication Pins, LAD0-LAD3. Clock conforms specification. Block Lock (TBL). Block Lock input used prevent Block (Block from being changed. When Block Lock, TBL, Low, VIL, Program Block Erase operations Block have effect, regardless state Lock Register. When Block Lock, TBL, High, VIH, protection Block determined Lock Register. state Block Lock, TBL, does affect protection other Blocks (Blocks 48). Block Lock, TBL, must prior Program Block Erase operation initiated must changed until operation completes unpredictable results occur. Care should taken avoid unpredictable behavior changing during Program Erase Suspend. Write Protect (WP). Write Protect input used prevent Blocks from being
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changed. When Write Protect, Low, VIL, Program Block Erase operations Blocks have effect, regardless state Lock Register. When Write Protect, High, VIH, protection Block determined Lock Register. state Write Protect, does affect protection Block (Block 49). Write Protect, must prior Program Block Erase operation initiated must changed until operation completes unpredictable results occur. Care should taken avoid unpredictable behavior changing during Program Erase Suspend. Reserved Future (RFU). These pins have assigned functions this revision part. They must left disconnected. Table Block Addresses
Size (Kbytes) Address Range 1FC000h-1FFFFFh 1FA000h-1FBFFFh 1F8000h-1F9FFFh 1F0000h-1F7FFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh Block Number Block Type Boot (Top) Parameter Parameter Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 00F000h-00FFFFh 00E000h-00EFFFh 00D000h-00DFFFh 00C000h-00CFFFh 00B000h-00BFFFh 00A000h-00AFFFh 009000h-009FFFh 008000h-008FFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter Parameter
Note: A23, Table
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Address/Address Multiplexed (A/A Mux) Signal Descriptions Address/Address Multiplexed (A/A Mux) Interface Figure Table Address Inputs (A0-A10). Address Inputs used Address bits (A0-A10) Column Address bits (A11-A20). They latched during operation Row/Column Address Select input, Data Inputs/Outputs (DQ0-DQ7). Data Inputs/Outputs hold data that written read from memory. They output data stored selected address during Read operation. During Write operations they represent commands sent Command Interface internal state machine. Data Inputs/Outputs, DQ0-DQ7, latched during Write operation. Output Enable (G). Output Enable, controls Read operation memory. Write Enable (W). Write Enable, controls Write operation memory's Command Interface. Row/Column Address Select (RC). Row/ Column Address Select input selects whether Address Inputs should latched into Address bits (A0-A10) Column Address bits (A11-A20). Address bits latched falling edge whereas Column Address bits latched rising edge. Ready/Busy Output (RB). Ready/Busy gives status memory's Program/Erase Controller. When Ready/Busy Low, VOL, memory busy with Program Erase operation will accept additional Program Erase command except Program/Erase Suspend command. When Ready/Busy High, VOH, memory ready Read, Program Erase operation. Supply Signal Descriptions Supply Signals same both interfaces. Supply Voltage. Supply Voltage supplies power operations (Read, Program, Erase etc.). Command Interface disabled when Supply Voltage less than Lockout Voltage, VLKO. This prevents Write operations from accidentally damaging data during power power down power surges. Program/ Erase Controller programming erasing during this time then operation aborts memory contents being altered will invalid. After becomes valid Command Interface reset Read mode. 0.1µF capacitor should connected between Supply Voltage pins Ground decouple current surges from power supply. Both Supply Voltage pins must connected power supply. track widths must sufficient carry currents required during program erase operations. Optional Supply Voltage. Optional Supply Voltage used select Fast Program (see Quadruple Byte Program Command description) Fast Erase options memory protect memory. When VPPLK Program Erase operations cannot performed error reported Status Register attempt change memory contents made. When Program Erase operations take place normal. When VPPH Fast Program operations (using Quadruple Byte Program command, 30h, from Table 10.) Fast Erase operations used. other voltage input will result undefined behavior should used. should VPPH more than hours during life memory. Ground. reference voltage measurements.
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OPERATIONS
interfaces have similar operations signals timings completely different. Count (LPC) Interface usual interface functionality part available through this interface. Only subset functions available through Address/Address Multiplexed (A/A Mux) Interface. Follow section Count (LPC) Operations below section Address/Address Multiplexed (A/A Mux) Interface Operations below description operations each interface. Count (LPC) Operations Count (LPC) Interface consists four data signals (LAD0-LAD3), control line (LFRAME) clock (CLK). addition protection against accidental malicious data corruption achieved using further signals (TBL WP). Finally reset signals INIT) available memory into known state. data signals, control signal clock designed compatible with electrical specifications. interface operates with clock speeds 33MHz. following operations performed using appropriate cycles: Read, Write, Standby, Reset Block Protection. Read. Read operations read from memory cells, specific registers Command Interface Count Registers. valid Read operation starts when Input Communication Frame, LFRAME, Low, VIL, Clock rises correct Start cycle LAD0-LAD3. following clock cycles Host will send Cycle Type Dir, Address other control bits LAD0-LAD3. memory responds outputting Sync data until wait-states have elapsed followed Data0-Data3 Data4-Data7. Table Figure description Field definitions each clock cycle transfer. Table 23., Figure 10., details timings signals. Write. Write operations write Command Interface Count Registers. valid Write operation starts when Input Communication Frame, LFRAME, Low, VIL, Clock rises correct Start cycle LAD0-LAD3. following Clock cycles Host will send Cycle Type Dir, Address, other control bits, Data0-Data3 Data4-Data7 LAD0-LAD3. memory outputs Sync data until waitstates have elapsed. Table Figure description Field definitions each clock cycle transfer. Table 23., Figure 10., details timings signals. Abort. Abort operation used immediately abort current operation. Abort occurs when LFRAME driven Low, VIL, during operation; memory will tristate Input/Output Communication pins, LAD0-LAD3. Note that, during Write operation, Command Interface starts executing command soon data fully received; Abort during final cycles guaranteed abort command; bus, however, will released immediately. Standby. When LFRAME High, VIH, memory into Standby mode where LAD0-LAD3 into high-impedance state Supply Current reduced Standby level, ICC1. Reset. During Reset mode internal circuits switched off, memory deselected outputs high-impedance. memory Reset mode when Interface Reset, Reset, INIT, Low, VIL. INIT must held Low, VIL, tPLPH. memory resets Read mode upon return from Reset mode Lock Registers return their default states regardless their state before Reset, Table INIT goes Low, VIL, during Program Erase operation, operation aborted memory cells affected longer contain valid data; memory take tPLRH abort Program Erase operation. Block Protection. Block Protection forced using signals Block Lock, TBL, Write Protect, regardless state Lock Registers.
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Table Read Field Definitions
Clock Cycle Number Clock Cycle Count Field LAD0LAD3 Memory Description rising edge with LFRAME Low, contents LAD0-LAD3 must 0000b indicate start cycle. Indicates type cycle selects 1-byte reading. Bits must 01b. indicates direction transfer: read. reset 32-bit address phase transferred starting with most significant nibble first. A26-A31 must Array, registers access. A21, A23A25 values, Table host drives LAD0-LAD3 1111b indicate turnaround cycle. Flash Memory takes control LAD0-LAD3 during this cycle. Flash Memory drives LAD0-LAD3 0101b (short wait-sync) clock cycles, indicating that data available. wait-states always included. Flash Memory drives LAD0-LAD3 0000b, indicating that data will available during next clock cycle. Data transfer cycles, starting with least significant nibble. Flash Memory drives LAD0-LAD3 1111b indicate turnaround cycle. Flash Memory floats outputs, host takes control LAD0-LAD3.
START
0000b
CYCTYPE
0100b
3-10
ADDR
XXXX
1111b 1111b (float)
13-14
WSYNC
0101b
RSYNC
0000b
16-17
DATA
XXXX 1111b 1111b (float)
Figure Read Waveforms
LFRAME
LAD0-LAD3 Number clock cycles
START
CYCTYPE
ADDR
SYNC
DATA
AI04429
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Table Write Field Definitions
Clock Cycle Number Clock Cycle Count Field LAD0LAD3 Memory Description rising edge with LFRAME Low, contents LAD0-LAD3 must 0000b indicate start cycle. Indicates type cycle. Bits must 01b. indicates direction transfer: write. don't care (X). 32-bit address phase transferred starting with most significant nibble first. A26-A31 must Array, registers access. A21, A23-A25 values, refers Table Data transfer cycles, starting with least significant nibble. host drives LAD0-LAD3 1111b indicate turnaround cycle. Flash Memory takes control LAD0-LAD3 during this cycle. Flash Memory drives LAD0-LAD3 0000b, indicating received data command. Flash Memory drives LAD0-LAD3 1111b, indicating turnaround cycle. Flash Memory floats outputs host takes control LAD0-LAD3.
START CYCTY
0000b
011Xb
3-10
ADDR
XXXX
11-12
DATA SYNC
XXXX 1111b 1111b (float) 0000b 1111b 1111b (float)
Figure Write Waveforms
LFRAME
LAD0-LAD3 Number clock cycles
START
CYCTYPE
ADDR
DATA
SYNC
AI04430
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Address/Address Multiplexed (A/A Mux) Operations Address/Address Multiplexed (A/A Mux) Interface more traditional style interface. signals consist multiplexed address signals (A0A10), data signals, (DQ0-DQ7) three control signals (RC, additional signal, used reset memory. Address/Address Multiplexed (A/A Mux) Interface included Flash Programming equipment faster factory programming. Only subset features available Count (LPC) Interface available; these include Commands exclude Security features other registers. following operations performed using appropriate cycles: Read, Write, Output Disable Reset. When Address/Address Multiplexed (A/A Mux) Interface selected blocks unprotected. possible protect blocks through this interface. Read. Read operations used output contents Memory Array, Electronic Signature Status Register. valid Read operation begins latching Address Column Address signals into memory using Address Inputs, A0-A10, Row/Column Address Select Then Write Table Operations
Operation Read Write Output Disable Reset Don't Care VPPH Don't Care Don't Care DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z
Enable Interface Reset (RP) must High, VIH, Output Enable, Low, VIL, order perform Read operation. Data Inputs/ Outputs will output value, Figure 12., Table 25., details when output becomes valid. Write. Write operations write Command Interface. valid Write operation begins latching Address Column Address signals into memory using Address Inputs, A0-A10, Row/Column Address Select data should Data Inputs/Outputs; Output Enable, Interface Reset, must High, Write Enable, must Low, VIL. Data Inputs/ Outputs latched rising edge Write Enable, Figure 13., Table 26., details timing requirements. Output Disable. data outputs high-impedance when Output Enable, VIH. Reset. During Reset mode internal circuits switched off, memory deselected outputs high-impedance. memory Reset mode when Low, VIL. must held Low, tPLPH. goes Low, VIL, during Program Erase operation, operation aborted memory cells affected longer contain valid data; memory take tPLRH abort Program Erase operation.
Table Manufacturer Device Codes
Operation Manufacturer Code Device Code A20-A1 DQ7-DQ0
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COMMAND INTERFACE
Write operations memory interpreted Command Interface. Commands consist more sequential Write operations. After power-up Reset operation memory enters Read mode. commands summarized Table Table conjunction with text descriptions below. Read Memory Array Command. Read Memory Array command returns memory Read mode where behaves like EPROM. Write cycle required issue Read Memory Array command return memory Read mode. Once command issued memory remains Read mode until another command issued. From Read mode Read operations will access memory array. While Program/Erase Controller executing Program Erase operation memory will accept Read Memory Array command until operation completes. Read Status Register Command. Read Status Register command used read Status Register. Write cycle required issue Read Status Register command. Once command issued subsequent Read operations read Status Register until another command issued. section Status Register details definitions Status Register bits. Read Electronic Signature Command. Read Electronic Signature command used read Manufacturer Code Device Code. Write cycle required issue Read Electronic Signature command. Once command issued subsequent Read operations read Manufacturer Code Device Code until another command issued. After Read Electronic Signature Command issued Manufacturer Code Device Code read using Read operations using addresses Table Table Read Electronic Signature
Code Manufacturer Code Device Code Address 000000h 000001h Data
Program Command. Program command used program value address memory array time. Write operations required issue command; sec-
Write cycle latches address data internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. address falls protected block then Program operation will abort, data memory array will changed Status Register will output error. During Program operation memory will only accept Read Status Register command Program/Erase Suspend command. other commands will ignored. Typical Program times given Table Note that Program command cannot change back attempting will cause modification value. Erase commands must used bits block `1'. Figure 15., suggested flowchart using Program command. Quadruple Byte Program Command (A/A Mode). Quadruple Byte Program Command used program four adjacent bytes memory array time. four bytes must differ only addresses Programming should attempted when VPPH. Five Write operations required issue command. second, third fourth Write cycle latches respectively address data first, second third byte internal state machine. fifth Write cycle latches address data fourth byte internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. During Quadruple Byte Program operation memory will only accept Read Status register command Program/Erase Suspend command. other commands will ignored. Typical Quadruple Byte Program times given Table Note that Quadruple Byte Program command cannot change back attempting will cause modification value. Erase commands must used bits block `1'. Figure 16., suggested flowchart using Quadruple Byte Program command.
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Chip Erase Command. Chip Erase Command only used mode erase entire chip time. Erasing should attempted when VPPH. operation also executed below VPPH, result could uncertain. Write operations required issue command start Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. During Chip Erase operation memory will only accept Read Status Register command. other commands will ignored. Typical Chip Erase times given Table Chip Erase command sets bits memory `1'. Figure 18., suggested flowchart using Chip Erase command. Block Erase Command. Block Erase command used erase block. Write operations required issue command; second Write cycle latches block address internal state machine starts Program/Erase Controller. Once command issued subsequent Read operations read Status Register. section Status Register details definitions Status Register bits. block protected then Block Erase operation will abort, data block will changed Status Register will output error. During Block Erase operation memory will only accept Read Status Register command Program/Erase Suspend command. other commands will ignored. Typical Block Erase times given Table Block Erase command sets bits block `1'. previous data block lost. Figure 19., suggested flowchart using Erase command. Clear Status Register Command. Clear Status Register command used reset bits Status Register `0'. Write required issue Clear Status Register command. Once command issued memory returns previous mode, subsequent Read operations continue output same data. bits Status Register sticky automatically return when Program Erase command issued. error occurs then essential clear error bits Status Register issuing Clear Status Register command before attempting Program Erase command. Program/Erase Suspend Command. Program/Erase Suspend command used pause Program Block Erase operation. Write cycle required issue Program/ Erase Suspend command pause Program/Erase Controller. Once command issued necessary poll Program/Erase Controller Status find when Program/ Erase Controller paused; other commands will accepted until Program/Erase Controller paused. After Program/Erase Controller paused, memory will continue output Status Register until another command issued. During polling period between issuing Program/Erase Suspend command Program/ Erase Controller pausing possible operation complete. Once Program/Erase Controller Status indicates that Program/Erase Controller longer active, Program Suspend Status Erase Suspend Status used determine operation completed suspended. timing delay between issuing Program/Erase Suspend command Program/Erase Controller pausing Table During Program/Erase Suspend Read Memory Array, Read Status Register, Read Electronic Signature Program/Erase Resume commands will accepted Command Interface. Additionally, suspended operation Block Erase then Program command will also accepted; only blocks being erased read programmed correctly. Figure 17., Figure 20., suggested flowcharts using Program/Erase Suspend command. Program/Erase Resume Command. Program/Erase Resume command used restart Program/Erase Controller after Program/Erase Suspend paused Write cycle required issue Program/Erase Resume command. Once command issued subsequent Read operations read Status Register.
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Table Commands
Cycles Write Operations Addr Data Addr Data Addr Data Addr Data Addr Data Command
Read Memory Array Read Status Register Read Electronic Signature
Program Quadruple Byte Program (A/A Mode) Chip Erase Block Erase Clear Status Register Program/Erase Suspend Program/Erase Resume Invalid/Reserved
Note: Don't Care, Program Address, Program Data, A1,2,3,4 Consecutive Addresses, address Block. Read Memory Array. After Read Memory Array command, read memory normal until another command issued. Read Status Register. After Read Status Register command, read Status Register normal until another command issued. Read Electronic Signature. After Read Electronic Signature command, read Manufacturer Code, Device Code until another command issued. Block Erase, Program. After these commands read Status Register until command completes another command issued. Quadruple Byte Program (A/A Mode). Addresses must consecutive addresses differing only address After this command, user should repeatedly read Status Register until command completed, which point another command issued. Chip Erase. This command only valid mode. After this command read Status Register until command completes another command issued. Clear Status Register. After Clear Status Register command bits Status Register reset `0'. Program/Erase Suspend. After Program/Erase Suspend command been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) Program/Erase resume commands. Program/Erase Resume. After Program/Erase Resume command suspended Program/Erase operation resumes, read Status Register until Program/Erase Controller completes memory returns Read Mode. Invalid/Reserved. Invalid Reserved commands.
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STATUS REGISTER
Status Register provides information current previous Program Erase operation. Different bits Status Register convey different information errors operation. read Status Register Read Status Register command issued. Status Register automatically read after Program, Erase Program/Erase Resume commands issued. Status Register read from address. Status Register bits summarized Table Table conjunction with text descriptions below. Program/Erase Controller Status (Bit Program/Erase Controller Status indicates whether Program/Erase Controller active inactive. When Program/Erase Controller Status `0', Program/Erase Controller active; when `1', Program/Erase Controller inactive. Program/Erase Controller Status immediately after Program/Erase Suspend command issued until Program/Erase Controller pauses. After Program/Erase Controller pauses `1'. During Program Erase operation Program/Erase Controller Status polled find operation. other bits Status Register should tested until Program/Erase Controller completes operation `1'. After Program/Erase Controller completes operation Erase Status, Program Status, Status Block Protection Status bits should tested errors. Erase Suspend Status (Bit Erase Suspend Status indicates that Block Erase operation been suspended waiting resumed. Erase Suspend Status should only considered valid when Program/Erase Controller Status (Program/Erase Controller inactive); after Program/Erase Suspend command issued memory still complete operation rather than entering Suspend mode. When Erase Suspend Status Program/Erase Controller active completed operation; when Program/Erase Suspend command been issued memory waiting Program/Erase Resume command. When Program/Erase Resume command issued Erase Suspend Status returns `0'. Erase Status (Bit Erase Status used identify memory applied maximum number erase pulses block(s) still failed verify that block(s) erased correctly. Erase Status should read once Program/Erase Controller Status (Program/Erase Controller inactive). When Erase Status memory successfully verified that block(s) erased correctly; when Erase Status Program/Erase Controller applied maximum number pulses block(s) still failed verify that block(s) erased correctly. Once Erase Status only reset Clear Status Register command hardware reset. should reset before Program Erase command issued, otherwise command will appear fail. (When `1', wrong command sequence been attempted). Program Status (Bit Program Status used identify memory applied maximum number program pulses byte still failed verify that byte programmed correctly. Program Status should read once Program/Erase Controller Status (Program/Erase Controller inactive). When Program Status memory successfully verified that byte programmed correctly; when Program Status Program/Erase Controller applied maximum number pulses byte still failed verify that byte programmed correctly. Once Program Status only reset Clear Status Register command hardware reset. should reset before Program Erase command issued, otherwise command will appear fail. (When `1', wrong command sequence been attempted). Status (Bit Status used identify invalid voltage during Program Erase operations. only sampled beginning Program Erase operation. Indeterminate results occur becomes invalid during Program Erase operation. When Status voltage sampled valid voltage; when Status voltage that below Lockout Voltage, VPPLK, memory protected; Program Erase operation cannot performed. (The status Quadruple Byte Program command issued signal voltage less than VPPH applied it.) Once Status only reset Clear Status Register command
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hardware reset. should reset before Program Erase command issued, otherwise command will appear fail. Program Suspend Status (Bit Program Suspend Status indicates that Program operation been suspended waiting resumed. Program Suspend Status should only considered valid when Program/Erase Controller Status (Program/Erase Controller inactive); after Program/Erase Suspend command issued memory still complete operation rather than entering Suspend mode. When Program Suspend Status Program/Erase Controller active completed operation; when Program/ Erase Suspend command been issued memory waiting Program/Erase Resume command. When Program/Erase Resume command issued Program Suspend Status returns `0'. Table Status Register Bits
Operation Program active Program suspended Program completed successfully Program failure Error Program failure Block Protection (LPC Interface only) Program failure cell failure Erase active Block Erase suspended Erase completed successfully Erase failure Error Block Erase failure Block Protection (LPC Interface only) Erase failure failed cell(s) Sequence command error X(1) X(1) X(1) X(1) X(1) X(1)
Block Protection Status (Bit Block Protection Status used identify Program Block Erase operation tried modify contents protected block. When Block Protection Status Program Block Erase operations have been attempted protected blocks since last Clear Status Register command hardware reset; when Block Protection Status Program Block Erase operation been attempted protected block. Once Block Protection Status only reset Clear Status Register command hardware reset. should reset before Program Block Erase command issued, otherwise command will appear fail. Using Interface Block Protection Status always `0'. Reserved (Bit Status Register reserved. value should masked.
Note: Program operations during Erase Suspend `1', otherwise `0'.
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M50LPW116
COUNT (LPC) INTERFACE CONFIGURATION REGISTERS
When Count Interface selected several additional registers accessed. These registers control protection status Blocks read General Purpose Input pins. Table example Register Configuration map, valid boot memory, i.e. ID0-ID3 floating driven LOW, A21, A23-A25 `1'. Lock Registers Lock Registers control protection status Blocks. Each Block Lock Register. Blocks have same Lock Register. Three bits within each Lock Register control protection each block, Write Lock Bit, Read Lock Lock Down Bit. Lock Registers read written, though care should taken when writing once Lock Down set, `1', further modifications Lock Register cannot made until cleared, `0', reset power-up. Table details definitions Lock Registers. Write Lock. Write Lock determines whether contents Block modified (using Program Block Erase Command). When Write Lock set, `1', block write protected; operations that attempt change data block will fail Status Register will report error. When Write Lock reset, `0', block write protected through Lock Register modified unless write protected through some other means. When less than VPPLK blocks protected cannot modified, regardless state Write Lock Bit. Block Lock, TBL, Low, VIL, then Block (Block write protected cannot modified. Similarly, Write Protect, Low, VIL, then Blocks write protected cannot modified. After power-up reset Write Lock always (write protected). Read Lock. Read Lock determines whether contents Block read (from Read mode). When Read Lock set, `1', block read protected; operation that attempts read contents block will read instead. When Read Lock reset, `0', read operations Block return data programmed into block expected. After power-up reset Read Lock always reset (not read protected). Lock Down. Lock Down provides mechanism protecting software data from simple hacking malicious attack. When Lock Down set, `1', further modification Write Lock, Read Lock Lock Down Bits cannot performed. reset power-up required before changes these bits made. When Lock Down reset, `0', Write Lock, Read Lock Lock Down Bits changed. General Purpose Input Register General Purpose Input Register holds state General Purpose Input pins, GPI0GPI4. When this register read, state these pins returned. This register read-only writing effect. signals General Purpose Input pins should remain constant throughout whole Read cycle order guarantee that correct data read.
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M50LPW116
Table Count Register Configuration
Mnemonic T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS00_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK T_MINUS16_LK T_MINUS17_LK T_MINUS18_LK T_MINUS19_LK T_MINUS20_LK T_MINUS21_LK T_MINUS22_LK T_MINUS23_LK T_MINUS24_LK T_MINUS25_LK T_MINUS26_LK T_MINUS27_LK T_MINUS28_LK T_MINUS29_LK T_MINUS30_LK T_MINUS31_LK T_MINUS32_LK T_MINUS33_LK T_MINUS34_LK MANUF_REG DEV_REG GPI_REG Register Name Block Lock Register (Block Block[-01] Lock Register (Block Block[-02] Lock Register (Block Block[-03] Lock Register (Block Block[-04] Lock Register (Block Block[-05] Lock Register (Block Block[-06] Lock Register (Block Block[-07] Lock Register (Block Block[-08] Lock Register (Block Block[-09] Lock Register (Block Block[-10] Lock Register (Block Block[-11] Lock Register (Block Block[-12] Lock Register (Block Block[-13] Lock Register (Block Block[-14] Lock Register (Block Block[-15] Lock Register (Block Block[-16] Lock Register (Block Block[-17] Lock Register (Block Block[-18] Lock Register (Block Block[-19] Lock Register (Block Block[-20] Lock Register (Block Block[-21] Lock Register (Block Block[-22] Lock Register (Block Block[-23] Lock Register (Block Block[-24] Lock Register (Block Block[-25] Lock Register (Block Block[-26] Lock Register (Block Block[-27] Lock Register (Block Block[-28] Lock Register (Block Block[-29] Lock Register (Block Block[-30] Lock Register (Block Block[-31] Lock Register (Block Block[-32] Lock Register (Block Block[-33] Lock Register (Block Block[-34] Lock Register (Block Manufacturer Code Register Device Code Register General Purpose Input Register Memory Address FFBFC002h FFBFA002h FFBF8002h FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFB70002h FFB60002h FFB50002h FFB40002h FFB30002h FFB20002h FFB10002h FFB00002h FFAF0002h FFAE0002h FFAD0002h FFAC0002h FFAB0002h FFAA0002h FFA90002h FFA80002h FFA70002h FFA60002h FFA50002h FFA40002h FFA30002h FFA20002h FFA10002h FFA00002h FFBC0000h FFBC0001h FFBC0100h Default Value Access
Note: This referred boot memory (ID0-ID3 floating driven Low, VIL, A21,A23-A25 `1').
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M50LPW116
Table Lock Register Definitions(1)
Read-Lock Name Value Reserved Read operations this Block always return 00h. read operations this Block return Memory Array contents. (Default value). Changes Read-Lock Write-Lock cannot performed. Once written Lock-Down cannot cleared `0'; always reset following Reset (using INIT) after power-up. Read-Lock Write-Lock changed writing values them. (Default value). Program Block Erase operations this Block will error Status Register. memory contents will changed. (Default value). Program Block Erase operations this Block executed will modify Block contents. Function
Lock-Down Write-Lock
Note: Applies Block Lock Register (T_BLOCK_LK) Block [-1] Lock Register (T_MINUS01_LK) Block [-34] Lock Register (T_MINUS34_LK).
Table General Purpose Input Register Definition(1)
GPI4 GPI3 GPI2 GPI1 GPI0 Input GPI0 Input GPI1 Input GPI0 Input GPI2 Input GPI1 Input GPI3 Input GPI2 Input GPI4 Input GPI3 Name Value Reserved Input GPI4 Function
Note: Applies General Purpose Input Register (GPI_REG).
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M50LPW116
PROGRAM ERASE TIMES
Program Erase times shown Table Table Program Erase Times
Parameter Byte Program Quadruple Byte Program Chip Erase Block Program Kbytes) Block Erase Kbytes) Program/Erase Suspend Program pause Program/Erase Suspend Block Erase pause
Note: 25°C, 3.3V This time obtained executing Quadruple Byte Program Command. Sampled only, 100% tested. Time program four bytes.
Interface
Test Condition
Unit
0.75
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M50LPW116
MAXIMUM RATING
Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum Ratings
Symbol TSTG TLEAD VESD Storage Temperature Lead Temperature during Soldering Input Output range Supply Voltage Program Voltage Electrostatic Discharge Voltage (Human Body model) Parameter Min. Max. Unit
plied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
note -0.60 -0.60 -0.6 -2000 2000
Note: Compliant with JEDEC J-STD-020B (for small body, Sn-Pb assembly), ECOPACK® 7191395 specification, European directive Restrictions Hazardous Substances (RoHS) 2002/95/EU Minimum voltage undershoot less than 20ns during transitions. Maximum voltage overshoot less than 20ns during transitions. JEDEC JESD22-A114A (C1=100 R1=1500 R2=500
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M50LPW116
PARAMETERS
This section summarizes operating measurement conditions, characteristics device. parameters characteristics Tables that follow, derived from tests performed under Measurement Table Operating Conditions
Symbol Supply Voltage Ambient Operating Temperature (Device Grade Ambient Operating Temperature (Device Grade Parameter Unit
Conditions summarized Table 17., Table Table Designers should check that operating conditions their circuit match operating conditions when relying quoted parameters.
Table Interface Measurement Conditions
Parameter Load Capacitance (CL) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages Value Unit
Table Interface Measurement Conditions
Parameter Load Capacitance (CL) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages Value Unit
Figure Interface Testing Input Output Waveforms
Input Output Testing Waveform
Output Tri-state Testing Waveform
AI03404
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M50LPW116
Figure Interface Testing Input Output Waveform
1.5V
AI01417
Table Impedance
Symbol CIN(1) CCLK(1) LPIN(2) Parameter Input Capacitance Clock Capacitance Recommended Inductance Test Condition(3) Unit
Note: Sampled only, 100% tested. Specification. 25°C, 1MHz.
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M50LPW116
Table Characteristics
Symbol Parameter Input High Voltage Interface VIH(INIT) VIL(INIT) ILI(2) ILI2 Input Voltage INIT Input High Voltage INIT Input Voltage Input Leakage Current Input Leakage Current Input Pull Resistor Output High Voltage VPP1 VPPH VPPLK(1) VLKO(1) ICC1 Output Voltage Output Leakage Current Voltage Voltage (Fast Program/Fast Erase) Lockout Voltage Lockout Voltage Supply Current (Standby) LFRAME VCC, other inputs 3.6V, f(CLK) 33MHz LFRAME VCC, other inputs 3.6V, f(CLK) 33MHz max, f(CLK) 33MHz IOUT VIH, 6MHz Program/Erase Controller Active 1.8mA VOUT 11.4 0.45 12.6 -100µA 1.5mA -500µA ID0, ID1, ID2, Test Condition -0.5 -0.5 1.35 -0.5 Unit
ICC2
Supply Current (Standby) Supply Current (Any internal operation active) Supply Current (Read) Supply Current (Program/Erase) Supply Current (Read/Standby) Supply Current (Program/Erase active)
ICC3 ICC4 ICC5(1) IPP1(1)
Note: Sampled only, 100% tested. Input leakage currents include High-Z output leakage bi-directional buffers with tri-state outputs.
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M50LPW116
Figure Interface Clock Waveform
tCYC tHIGH
AI03403
tLOW
VCC, p-to-p (minimum)
Table Interface Clock Characteristics
Symbol tCYC tHIGH tLOW Parameter Cycle Time(1) High Time Time Slew Rate peak peak V/ns Test Condition Value Unit V/ns
Note: Devices must work with clock frequency between 33MHz. Below 16MHz devices guaranteed design rather than tested. Refer Specification.
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M50LPW116
Figure Interface Signal Timing Waveforms
tCHQV tCHQZ tCHQX LAD0-LAD3 VALID OUTPUT DATA FLOAT OUTPUT DATA tCHDX VALID VALID INPUT DATA
AI04431
tDVCH
Table Interface Signal Timing Characteristics
Symbol Symbol tval toff Parameter Test Condition tCHQV tCHQX(1) tCHQZ tAVCH tDVCH tCHAX tCHDX Data Active (Float Active Delay) Inactive (Active Float Delay) Input Set-up Time(2) Input Hold Time(2) Value Unit
Note: timing measurements Active/Float transitions defined when current through equals leakage current specification. Applies inputs except CLK.
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M50LPW116
Figure Reset Waveforms
INIT tPLPH LFRAME tPHWL, tPHGL, tPHFL
tPLRH
AI04432
Table Reset Characteristics
Symbol tPLPH tPLRH Parameter INIT Reset Pulse Width Program/Erase Inactive INIT Reset Program/Erase Active INIT Slew Rate(1) tPHFL tPHWL tPHGL INIT High LFRAME High Write Enable Output Enable Rising edge only Interface only Interface only Test Condition Value Unit mV/ns
Note: Chapter Specification.
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M50LPW116
Figure Interface Read Waveforms
tAVAV A0-A10 tAVCL tCLAX tCHQV tGLQV tGLQX DQ0-DQ7 tGHQZ tGHQX VALID ADDR VALID COLUMN ADDR VALID tAVCH tCHAX NEXT ADDR VALID
tPHAV
AI03406
Table Interface Read Characteristics
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV(1) tGLQV(1) tPHAV tGLQX tGHQZ tGHQX Parameter Read Cycle Time Address Valid Address Transition Column Address Valid high High Column Address Transition High Output Valid Output Enable Output Valid High Address Valid Output Enable Output Transition Output Enable High Output Hi-Z Output Hold from Output Enable High Test Condition Value Unit
Note: delayed tCHQV tGLQV after rising edge without impact tCHQV.
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Figure Interface Write Waveforms
Write erase program setup A0-A10 tCLAX tAVCL tWHWL tWLWH tVPHWH tWHRL tQVVPL tDVWH DQ0-DQ7 DIN1 DIN2 tWHDX VALID
AI04194
Write erase confirm valid address data tAVCH tCHAX
Automated erase program delay
Read Status Register Data
Ready write another command
tCHWH
tWHGL
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M50LPW116
Table Interface Write Characteristics
Symbol tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPHWH(1) tWHGL tWHRL tQVVPL(1,2) Parameter Write Enable Write Enable High Data Valid Write Enable High Write Enable High Data Transition Address Valid Address Transition Column Address Valid High High Column Address Transition Write Enable High Write Enable High Write Enable High High Write Enable High Write Enable High Output Enable Write Enable High Output Valid, High Test Condition Value Unit
Note: Sampled only, 100% tested. Applicable seen logic input (VPP 3.6V).
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M50LPW116
PACKAGE MECHANICAL
Figure TSOP40 lead Plastic Thin Small Outline, 10x20 Package Outline
TSOP-a
Note: Drawing scale.
Table TSOP40 lead Plastic Thin Small Outline, 10x20 Package Mechanical Data
millimeters Symbol 0.500 19.800 18.300 9.900 0.500 0.050 0.950 0.170 0.100 1.200 0.150 1.050 0.270 0.210 0.100 20.200 18.500 10.100 0.700 0.0197 0.7795 0.7205 0.3898 0.0197 0.0020 0.0374 0.0067 0.0039 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.7953 0.7283 0.3976 0.0276 inches
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M50LPW116
PART NUMBERING
Table Ordering Information Scheme
Example: Device Type Architecture Count Interface Operating Voltage 3.6V Device Function Mbit (2Mb x8), Boot Block Package TSOP40: Device Grade Temperature range Device tested with standard test flow Temperature range Device tested with standard test flow Option blank Standard Packing Tape Reel Packing Plating Technology blank Standard SnPb plating Lead-Free, RoHS compliant, Sb2O3-free TBBA-free Tape Reel Packing
M50LPW116
Devices shipped from factory with memory content bits erased '1'. list available options (Speed, Package, etc.) further information aspect this device, please contact your nearest Sales Office.
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M50LPW116
FLOWCHARTS PSEUDO CODES
Figure Program Flowchart Pseudo Code
Start
Write
Write Address Data
Program command: write write Address Data (memory enters read status state after Program command)
Read Status Register Suspend Suspend Loop
-read Status Register Program/Erase Suspend command been executed Enter Program Suspend loop
Interface Only
Invalid Error
invalid error: error handler
Program Error
Program error: error handler
Program Protected Block Error
Program protected block error: error handler
AI04433b
Note: Status check (Protected Block), (VPP invalid) (Program Error) made after each Program operation following correct command sequence. error found, Status Register must cleared before further Program/Erase Controller operations.
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Figure Quadruple Byte Program Flowchart Pseudo Code (A/A Interface Only)
Start
Write
Write Address Data
Write Address Data
Quadruple Byte Program command: write write Address Data write Address Data write Address Data write Address Data (memory enters read status state after Quadruple Byte Program command)
Write Address Data
Write Address Data read Status Register Program/Erase Suspend command been executed Enter Program Suspend loop
Read Status Register Suspend Suspend Loop
Invalid Error
invalid error: error handler
Program Error
Program error: error handler
AI03982b
Note: Status check (VPP invalid) (Program Error) made after each Program operation following correct command sequence. error found, Status Register must cleared before further Program/Erase Controller operations. Address Address Address Address must consecutive addresses differing only address bits
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M50LPW116
Figure Program Suspend Resume Flowchart Pseudo Code
Start
Write
Write
Program/Erase Suspend command: write write read Status Register
Read Status Register
Write read Command
while
Program Complete
Program completed
Read data from another address
Write
Write
Program Continues
Read Data
Program/Erase Resume command: write resume program Program operation completed then this necessary. device returns Read normal Program/Erase suspend issued).
AI03408
Note: error occurs, Status Register must cleared before performing further Program/Erase operations. address within bank used.
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M50LPW116
Figure Chip Erase Flowchart Pseudo Code (A/A Interface Only)
Start
Write
Chip Erase command: write write (memory enters read Status Register after Chip Erase command)
Write read Status Register
Read Status Register
while
AI04195b
Invalid Error
invalid error: error handler
Command Sequence Error
Command sequence error: error handler
Erase Error
Erase error: error handler
Note: error found, Status Register must cleared before further Program/Erase Controller operations.
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M50LPW116
Figure Block Erase Flowchart Pseudo Code
Start
Write
Write Block Address
Block Erase command: write write Block Address (memory enters read Status Register after Block Erase command)
Read Status Register
Suspend
-read Status Register Program/Erase Suspend command been executed Enter Program Suspend loop
Suspend Loop
Interface Only
AI04434b
Invalid Error
invalid error: error handler
Command Sequence Error
Command sequence error: error handler
Erase Error
Erase error: error handler
Erase Protected Block Error
Erase protected block error: error handler
Note: error found, Status Register must cleared before further Program/Erase Controller operations.
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M50LPW116
Figure Erase Suspend Resume Flowchart Pseudo Code
Start
Write
Write
Program/Erase Suspend command: write write read Status Register
Read Status Register
while
Erase Complete
Erase completed
Read data from another block Program
Write
Write
Erase Continues
Read Data
Program/Erase Resume command: write resume erase Erase operation completed then this necessary. device returns Read normal Program/Erase suspend issued).
AI03410b
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M50LPW116
REVISION HISTORY
Table Revision History
Date September 2001 12-Dec-2001 16-Jan-2002 01-Mar-2002 30-Jul-2002 22-Nov-2002 13-Feb-2003 Version First Issue Extensions descriptions Quadruple Byte Programming Device code announced: pins must left disconnected Quadruple Byte Mode, mode, removed Revision numbering modified: minor revision will indicated incrementing digit after dot, major revision, incrementing digit before (revision version equals 5.0). Document promoted Product Preview. Datasheet promoted from Product Preview Preliminary Data status. Datasheet status updated Full Datasheet. Document reformatted. Reserved Future (RFU). Temperature Range ordering information replaced Device Grade, Standard packing option added Plating Technology added. TLEAD parameter added Absolute Maximum Ratings TBIAS parameter removed. Flowcharts Figures modified. Notes added below Figure 17., Program Suspend Resume Flowchart Pseudo Code. Revision Details
14-Apr-2005
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M50LPW116
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2005 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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Mbit Boot Block) Supply Count Flash Memory SUPPLY VOLTAGE 3.6V Pr

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