Single-chip 32-bit microcontrollers; ISP/IAP Flash with kB/32 kB/16

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Single-chip 32-bit microcontrollers; ISP/IAP Flash with kB/32 kB/16

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LPC2104/2105/2106
Single-chip 32-bit microcontrollers; ISP/IAP Flash with kB/32 kB/16
Rev. December 2004 Product data
LPC2104/2105/2106 based 16/32 ARM7TDMI-SCPU with real-time emulation embedded trace support, together with kbytes (kB) embedded high speed flash memory. wide memory interface unique accelerator architecture enable code execution maximum clock rate. critical code size applications, alternative 16-bit ThumbMode reduces code more than with minimal performance penalty. their tiny size power consumption, these microcontrollers ideal applications where miniaturization requirement, such access control point-of-sale. With wide range serial communications interfaces on-chip SRAM options they very well suited communication gateways protocol converters, soft modems, voice recognition imaging, providing both large buffer size high processing power. Various timers, channels GPIO lines make these microcontrollers particularly suitable industrial control medical systems.
Features
features
16/32 ARM7TDMI-S processor. 16/32/64 on-chip Static RAM. on-chip Flash Program Memory. wide interface/accelerator enables high speed operation. In-System Programming (ISP) In-Application Programming (IAP) on-chip boot-loader software. Flash programming takes byte line. Single sector full chip erase takes Vectored Interrupt Controller with configurable priorities vector addresses. EmbeddedICE-RT interface enables breakpoints watch points. Interrupt service routines continue execute whilst foreground task debugged with on-chip RealMonitorsoftware. Embedded Trace Macrocell enables non-intrusive high speed real-time tracing instruction execution. Multiple serial interfaces including UARTs (16C550), Fast (400 kbits/s) SPITM. 32-bit timers capture/compare channels), unit outputs), Real Time Clock Watchdog. thirty-two tolerant general purpose pins tiny LQFP48 mm2) package.
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
maximum clock available from programmable on-chip Phase-Locked Loop with settling time On-chip crystal oscillator with operating range MHz. power modes, Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 power supply range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2104BBD48 LPC2105BBD48 LPC2106FBD48 LPC2106FHN48 LQFP48 LQFP48 LQFP48 Description Version plastic profile quad flat package; leads; SOT313-2 body plastic profile quad flat package; leads; SOT313-2 body plastic profile quad flat package; leads; SOT313-2 body SOT619-1 Type number
HVQFN48 plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
Ordering options
Table Part options Flash memory Temperature range +70, LQFP +70, LQFP +85, LQFP +85, HVQFN Type number LPC2104BBD48 LPC2105BBD48 LPC2106FBD48 LPC2106FHN48
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Block diagram
TRST(1) TMS(1) TCK(1) TDI(1) TDO(1)
RTCK
XTAL1 system clock
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
SYSTEM FUNCTIONS
ARM7TDMI-S
BRIDGE ARM7 LOCAL
VECTORED INTERRUPT CONTROLLER
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER BRIDGE DIVIDER
DECODER
16/32/64 SRAM
FLASH
APB(2) EINT0* EINT1* EINT2* EXTERNAL INTERRUPTS SERIAL INTERFACE SCL* SDA*
CAP0.2* MAT0.2*
CAPTURE/ COMPARE TIMER
SERIAL INTERFACE
CAP0.3* MAT0.3*
CAPTURE/ COMPARE TIMER
UART0
GPIO PINS)
GENERAL PURPOSE
UART1
PWM1.6*
PWM0
WATCHDOG TIMER
REAL TIME CLOCK
SYSTEM CONTROL
*Shared with GPIO
When test/debug interface used, GPIO/other function sharing these pins available. with Ready signal.
Block diagram.
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Product data
Rev. December 2004
XTAL2 SCK* MOSI* MISO* SSEL* TxD* RxD* TxD* RxD*
MODEM CONTROL PINS)*
002aaa412
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Pinning information
Pinning
P0.16/EINT0/MAT0.2
handbook, full pagewidth
P0.19/MAT1.2/TCK P0.20/MAT1.3/TDI P0.21/PWM5/TDO VDD1.8 (CORE) VSS1 P0.27/TRACEPKT0/TRST P0.28/TRACEPKT1/TMS
P0.12/DSR1/MAT1.0
P0.13/DTR1/MAT1.1
P0.17/CAP1.2/TRST
P0.26/TRACESYNC
P0.18/CAP1.3/TMS
P0.14/DCD1/EINT1
P0.25/PIPESTAT2
P0.15/RI1/EINT2
VDD3-1 (I/O)
VSS4
P0.11/CTS1/CAP1.1 P0.10/RTS1/CAP1.0 P0.24/PIPESTAT1 P0.23/PIPESTAT0 P0.22/TRACECLK VSS3 P0.9/RxD1/PWM6 P0.8/TxD1/PWM4 P0.7/SSEL/PWM2 DBGSEL RTCK
LPC2104/2105/2106
P0.29/TRACEPKT2/TCK
P0.0/TxD0/PWM1
P0.1/RxD0/PWM3
P0.30/TRACEPKT3/TDI
P0.31/EXTIN0/TDO
VDD3-2 (I/O)
P0.2/SCL/CAP0.0
VSS2
P0.3/SDA/MAT0.0
P0.4/SCK/CAP0.1
P0.5/MISO/MAT0.1
P0.6/MOSI/CAP0.2
002aaa411
Pinning.
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. P0.0 Port TxD0 Transmitter output UART PWM1 Pulse Width Modulator output P0.1 Port RxD0 Receiver input UART PWM3 Pulse Width Modulator output P0.2 Port clock input/output. Open drain output (for compliance). CAP0.0 Capture input Timer channel P0.3 Port data input/output. Open drain output (for compliance). MAT0.0 Match output Timer channel P0.4 Port Serial clock. clock output from master input slave. CAP0.1 Capture input Timer channel P0.5 Port MISO Master Slave Out. Data input master data output from slave. MAT0.1 Match output Timer channel P0.6 Port MOSI Master Slave Data output from master data input slave. CAP0.2 Capture input Timer channel P0.7 Port SSEL Slave Select. Selects interface slave. PWM2 Pulse Width Modulator output P0.8 Port TxD1 Transmitter output UART PWM4 Pulse Width Modulator output P0.9 Port RxD1 Receiver input UART PWM6 Pulse Width Modulator output
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table Symbol
description.continued Type Description P0.10 Port RTS1 Request Send output UART CAP1.0 Capture input Timer channel P0.11 Port CTS1 Clear Send input UART CAP1.1 Capture input Timer channel P0.12 Port DSR1 Data Ready input UART MAT1.0 Match output Timer channel P0.13 Port DTR1 Data Terminal Ready output UART MAT1.1 Match output Timer channel P0.14 Port DCD1 Data Carrier Detect input UART EINT1 External interrupt input. P0.15 Port Ring Indicator input UART EINT2 External interrupt input. P0.16 Port EINT0 External interrupt input. MAT0.2 Match output Timer channel P0.17 Port CAP1.2 Capture input Timer channel TRST Test Reset JTAG interface, primary JTAG group. P0.18 Port CAP1.3 Capture input Timer channel Test Mode Select JTAG interface, primary JTAG group. P0.19 Port MAT1.2 Match output Timer channel Test Clock JTAG interface, primary JTAG group. P0.20 Port MAT1.3 Match output Timer channel Test Data JTAG interface, primary JTAG group P0.21 Port PWM5 Pulse Width Modulator output Test Data JTAG interface, primary JTAG group. P0.22 Port TRACECLK Trace Clock. Standard port with internal pull-up. P0.23 Port PIPESTAT0 Pipeline Status, Standard port with internal pull-up. P0.24 Port
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Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table Symbol
description.continued Type Description PIPESTAT1 Pipeline Status, Standard port with internal pull-up. P0.25 Port PIPESTAT2 Pipeline Status, Standard port with internal pull-up. P0.26 Port TRACESYNC Trace Synchronization Standard port with internal pull-up. P0.27 Port TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRST Test Reset JTAG interface, secondary JTAG group. P0.28 Port TRACEPKT1 Trace Packet, Standard port with internal pull-up. Test Mode Select JTAG interface, secondary JTAG group P0.29 Port TRACEPKT2 Trace Packet, Standard port with internal pull-up. Test Clock JTAG interface, secondary JTAG group. P0.30 Port TRACEPKT3 Trace Packet, Standard port with internal pull-up. Test Data JTAG interface, secondary JTAG group. P0.31 Port EXTIN0 External Trigger Input. Standard port with internal pull-up. Test Data JTAG interface, secondary JTAG group. Returned Test Clock output: Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Also used during debug mode entry select primary secondary JTAG pins with 48-pin package. Bi-directional with internal pull-up. Debug Select: When LOW, part operates normally. When HIGH, debug mode entered. Input with internal pull-down. External Reset input: this resets device, causing ports peripherals take their default states, processor execution begin address Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference. Core Power Supply: This power supply voltage internal circuitry. Power Supply: This power supply voltage ports. Connected: These pins connected package.
RTCK
DBGSEL
VSS1 VSS4 VDD1.8 VDD3
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Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. ARM® architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-Chip Flash program memory
LPC2104/2105/2106 incorporate Flash memory system. This memory used both code data storage. Programming Flash memory accomplished several ways. programmed System serial port. application program also erase and/or program Flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When on-chip bootloader used, Flash memory available user code. LPC2104/2105/2106 Flash memory provides minimum 100,000 erase/write cycles years data retention.
On-Chip static
On-Chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2104 provides static RAM, LPC2105 provides static RAM, LPC2106 provides static RAM.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Memory
LPC2104, LPC2105 LPC2106 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either Flash memory (the default) on-chip static RAM. This described Section 6.17 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 3FFF KBYTE ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF KBYTE ON-CHIP FLASH MEMORY 0x0000 0000
002aaa415
LPC2104 memory map.
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Product data
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF KBYTE ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF KBYTE ON-CHIP FLASH MEMORY 0x0000 0000
002aaa414
LPC2105 memory map.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF KBYTE ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0002 0000 0x0001 FFFF KBYTE ON-CHIP FLASH MEMORY 0x0000 0000
002aaa413
LPC2106 memory map.
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes, them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active. 6.5.1 Interrupt sources Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF reserved Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) channel
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Interrupt sources.continued Flag(s) channel
Table Block
System Control External Interrupt (EINT0) System Control External Interrupt (EINT1) System Control External Interrupt (EINT2)
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module contains registers shown Table
Table Address 0xE002C000 0xE002C004 Name PINSEL0 PINSEL1 Description function select register function select register Access Read/Write Read/Write
function select register (PINSEL0 0xE002C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
Table PINSEL0 function select register (PINSEL0 0xE002C000) name P0.0 Value P0.1 P0.2 P0.3 P0.4 Function GPIO Port (UART PWM1 GPIO Port (UART PWM3 GPIO Port (I2C) Capture (Timer GPIO Port (I2C) Match (Timer GPIO Port (SPI) Capture (Timer Value after Reset
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
function select register (PINSEL0 0xE002C000).continued name P0.5 Value Function GPIO Port MISO (SPI) Match (Timer GPIO Port MOSI (SPI) Capture (Timer GPIO Port SSEL (SPI) PWM2 GPIO Port UART PWM4 GPIO Port (UART PWM6 GPIO Port 0.10 (UART1) Capture (Timer GPIO Port 0.11 (UART1) Capture (Timer GPIO Port 0.12 (UART1) Match (Timer GPIO Port 0.13 (UART Match (Timer GPIO Port 0.14 (UART EINT1 GPIO Port 0.15 (UART1) EINT2 Value after Reset
Table PINSEL0 11:10
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
27:26
P0.13
29:28
P0.14
31:30
P0.15
function select register (PINSEL1 0xE002C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Function control pins P0.17 P0.31 effective only when DBGSEL input pulled during RESET.
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
function select register (PINSEL1 0xE002C004) Name P0.16 Value Function GPIO Port 0.16 EINT0 Match (Timer GPIO Port 0.17 Capture (Timer GPIO Port 0.18 Capture (Timer GPIO Port 0.19 Match (Timer GPIO Port 0.20 Match (Timer GPIO Port 0.21 PWM5 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 TRST GPIO Port 0.28 GPIO Port 0.29 GPIO Port 0.30 GPIO Port 0.31 Value after Reset
Table PINSEL1
11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30
P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 P0.28 P0.29 P0.30 P0.31
General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins. 6.9.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset.
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.10 UARTs
LPC2104, LPC2105 LPC2106 each contain UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines. 6.10.1 Features
byte Receive Transmit FIFOs. Register locations conform `550 industry standard. Receiver FIFO trigger points bytes Built-in baud rate generator. Standard modem interface signals included UART
6.11 serial controller
bi-directional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g. driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected implemented LPC2104, LPC2105 LPC2106 supports rate kbit/s (Fast I2C). 6.11.1 Features
Standard compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption
serial data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
used test diagnostic purposes.
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Single-chip 32-bit microcontrollers
6.12 serial controller
full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master. 6.12.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate. 6.13 General purpose timers
Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. 6.13.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. four (TImer three (Timer 32-bit capture channels, that take
snapshot timer value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four (Timer three (Timer external outputs corresponding match
registers, with following capabilities: match. HIGH match. Toggle match. nothing match.
6.14 Watchdog timer
purpose Watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, Watchdog will generate system reset user program fails `feed' reload) Watchdog within predetermined amount time.
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Single-chip 32-bit microcontrollers
6.14.1
Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset Watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate Watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (tpclk (tpclk multiples
tpclk
6.15 Real time clock
Real Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode). 6.15.1 Features
Measures passage time maintain calendar clock. Ultra Power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
6.16 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2104, LPC2105 LPC2106. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. also includes four capture inputs save timer value when input signal transitions, optionally generate interrupt when those events occur. function addition these features, based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single
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Single-chip 32-bit microcontrollers
edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge). 6.16.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs.
Single edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive
going negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must "release" match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler.
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Single-chip 32-bit microcontrollers
6.17 System control
6.17.1 Crystal oscillator oscillator supports crystals range MHz. oscillator output frequency called FOSC processor clock frequency referred cclk purposes rate equations, etc. FOSC cclk same value unless running connected. Refer Section 6.17.2 "PLL" additional information. 6.17.2 accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time 6.17.3 Reset wake-up timer Reset sources LPC2104, LPC2105 LPC2106: Watchdog Reset. Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip Flash controller completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer. Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.17.4
External interrupt inputs LPC2104, LPC2105 LPC2106 include three External Interrupt Inputs selectable functions. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.17.5
Memory Mapping Control Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x00000000. Vectors mapped bottom on-chip Flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.17.6
Power Control LPC2104, LPC2105 LPC2106 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.17.7
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.18 Emulation debugging
LPC2104, LPC2105 LPC2106 support emulation debugging JTAG serial port. trace port allows tracing program execution. Each these functions requires trade-off debugging features versus device pins. Because LPC2104,
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
LPC2105 LPC2106 provided small package, there room permanently assigned JTAG Trace pins. alternate JTAG port allows option debug functions assigned pins used primary JTAG port. 6.18.1 Embedded Standard EmbeddedICElogic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function in-built. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic. 6.18.2 Embedded trace Since LPC2104, LPC2105 LPC2106 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction. 6.18.3 RealMonitorRealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2104, LPC2105 LPC2106 contain specific configuration RealMonitor software programmed into on-chip Flash memory.
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD1.8 VDD3 Tstg Supply voltage, internal rail Supply voltage, external rail input voltage, tolerant pins[2][3] input voltage, other pins[4][2] supply current supply pin[5] ground current ground pin[5] Storage temperature[6] Power dissipation (based package heat transfer, device power consumption) Conditions -0.5 -0.5 -0.5 -0.5 +2.5 +3.6 VDD3 Unit
following applies Limiting values: Stresses above those listed under Limiting values cause permanent damage device. This stress rating only functional operation device these conditions other than those described Section "Static characteristics" Section "Dynamic characteristics" this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. Only valid when VDD3 supply voltage present. exceed peak current limited times corresponding maximum current. Dependent package type.
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Static characteristics
Table Static characteristics Tamb commercial, unless otherwise specified. Symbol Parameter VDD1.8 VDD3 Ilatchup Vhys IDD1.8 Supply voltage External rail supply voltage level input current, pull-up HIGH level input current, pull down 3-state output leakage, pull-up/down latch-up current Input voltage[2][3][4] Output voltage, output active HIGH level input voltage level input voltage Hysteresis voltage HIGH level output level output HIGH level output voltage[5] voltage[5] current[5] VDD3 VDD3 VDD3 VDD3 -(0.5 VDD3) (1.5 VDD3) VDD3 V[7] VDD3 Conditions 1.65 Typ[1] 1.95 Unit
Standard Port pins, RST, RTCK, DBGSEL
level output current[5] HIGH level short circuit current[6] level short circuit current[6]
Pull-down current (applies V[7] DBGSEL) Pull-up current (applies P0.22 P0.31) Active Mode VDD3 VDD1.8 cclk MHz, Tamb code while(1){} executed from FLASH, active peripherals Power-down Mode VDD1.8 Tamb VDD1.8 Tamb
VTOL
VTOL
VTOL
pins HIGH level input voltage level input voltage Hysteresis voltage level output voltage[5] VTOL from VTOL from VTOL from
Vhys
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Table Static characteristics.continued Tamb commercial, unless otherwise specified. Symbol Parameter Ilkg Input leakage Conditions VDD3 Oscillator pins input Voltages output Voltages On-chip Flash program memory endurance (write erase) data retention
100,000
Typ[1]
VDD1.8 VDD1.8
Unit
cycles years
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. capacitance characterized tested. Including voltage outputs 3-state mode. VDD3 supply voltages must present. 3-state outputs into 3-state mode when VDD3 grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Dynamic characteristics
Table Characteristics Tamb commercial, industrial, VDD1.8, VDD3 over specified ranges[1] Symbol External Clock fosc Oscillator frequency supplied external oscillator (signal generator) External clock frequency supplied external crystal oscillator External clock frequency on-chip used External clock frequency used initial code download tCHCX tCLCX tCLCH tCHCL Port Pins tRISE tFALL pins Output fall time from Cb[2] Port output rise time (except P0.2, P0.3) Port output fall time (except P0.2, P0.3) External oscillator clock period Clock HIGH time Clock time Clock rise time Clock fall time 1000 Parameter Conditions Typ[1] Unit
Parameters valid over operating temperature range unless otherwise specified. capacitance from
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Timing
0.45
tCHCX
tCHCL
tCLCX
tCLCH
002aaa416
External clock timing.
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
SOT313-2 (LQFP48).
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
HVQFN48: plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85
SOT619-1
terminal index area
detail
terminal index area DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 5.25 4.95 5.25 4.95
scale 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT619-1 REFERENCES -JEDEC MO-220 JEITA -EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
SOT619-1 (HVQFN48).
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Revision history
Table Date 20041222 Revision history CPCN Description Product data (9397 14476) Modifications:
20040205 20031007 20030611 20030425
Added device LPC2106FBD48, removed device LPC2106BBD48. Section "On-Chip Flash program memory" page updated text. Section 6.17.2 "PLL" page updated text. Section 6.17.7 "VPB bus" page updated text. Table "Limiting values" page updated text. Table "Static characteristics" page added On-chip Flash program memory specs.
Product data (9397 12792); 853-2425 01-A15458f January 2004 Product data (9397 12142); 853-2425 30389 September 2003 Product data (9397 11499); 853-2425 29919 2003 Product data (9397 11414); 853-2425 29855 April 2003
9397 14476
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Data sheet status
Level Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Licenses
Purchase Philips components Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or
Trademarks
registered trademark ARM, Inc. ARM7TDMI-S trademark ARM, Inc. EmbeddedICE trademark ARM, Inc. Embedded Trace Macrocell trademark ARM, Inc. RealMonitor trademark ARM, Inc. trademark Motorola, Inc. Thumb trademark ARM, Inc.
Contact information
additional information, please visit sales office addresses, send e-mail
9397 14476
Fax: 24825
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Contents
6.5.1 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.17.2 6.17.3 6.17.4 6.17.5 6.17.6 6.17.7 6.18 6.18.1 6.18.2 6.18.3 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-Chip Flash program memory On-Chip static Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002C000). function select register (PINSEL1 0xE002C004). General purpose parallel I/O. Features UARTs Features serial controller Features serial controller. Features General purpose timers Features Watchdog timer. Features Real time clock Features Pulse width modulator Features System control Crystal oscillator Reset wake-up timer External interrupt inputs Memory Mapping Control Power Control Emulation debugging Embedded Embedded trace RealMonitorTM. Limiting values Static characteristics Dynamic characteristics Timing Package outline Revision history Data sheet status. Definitions Disclaimers Licenses Trademarks
Koninklijke Philips Electronics N.V. 2004. Printed U.S.A.
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: December 2004 Document order number: 9397 14476

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