Li-Ion battery charger Three battery voltage options Selectable 12.525

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Li-Ion battery charger Three battery voltage options Selectable 12.525

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High Frequency Switch Mode Li-Ion Battery Charger ADP3806
Li-Ion battery charger Three battery voltage options Selectable 12.525 V/16.700 Selectable 12.600 V/16.800 Adjustable High end-of-charge voltage accuracy ±0.4% 25°C ±0.6% 55°C ±0.7% 85°C Programmable charge current with rail-to-rail sensing System current sense with reverse input protection Soft start charge current Undervoltage lockout Bootstrapped synchronous drive external NMOS Programmable oscillator frequency Oscillator SYNC current flag Trickle charge
ADP3806 complete Li-Ion battery-charging device combines high output voltage accuracy with constant current control simplify implementation constantcurrent, constant-voltage (CCCV) chargers. ADP3806 available three options. ADP3806-12.6 guarantees final battery voltage selected 12.6 16.8 0.6%. ADP3806-12.5 guarantees 12.525 V/16.7 0.6%, ADP3806 adjustable using external resistors battery voltage. current sense amplifier rail-to-rail inputs operate accurately under dropout short-circuit conditions. charge current programmable with voltage ISET. second differential amplifier senses system current across external sense resistor outputs linear voltage ISYS pin. bootstrapped synchronous driver allows NMOS transistors lower system cost.
APPLICATIONS
Portable computers Fast chargers
FUNCTIONAL BLOCK DIAGRAM
DRVH
DRVL
PGND
SYS+ SYS-
ISYS
BOOTSTRAPPED SYNCHRONOUS DRIVER DRVLSD DRVLSD
VREF VREG UVLO BIAS
AMP1
AMP2
VREF
BSTREG
2.5V
LIMIT
LOGIC CONTROL
OSCILLATOR
ADP3806
AGND
SYNC
COMP
BATSEL
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
02611-001
ISET
SELECT 12.6V/16.8V
VREF
ADP3806 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Revision History Specifications. Absolute Maximum Ratings. Caution. Configuration Function Descriptions. Typical Performance Characteristics Theory Operation Charge Current Control Final Battery Voltage Control Oscillator Bootstrap Regulator Bootstrapped Synchronous Driver Precision Reference. Regulator System Current Sense Shutdown. UVLO. Start-up Sequence. Loop Feed Forward Application Information. Design Procedure Battery Voltage Settings. Outline Dimensions Ordering Guide
REVISION HISTORY
11/06-Rev. Rev. Updated Format.Universal Changes Table Changes Table Updated Outline Dimensions Changes Ordering Guide 2/04-Rev. Rev. Changes Specifications.2 Changes Ordering Guide Updated Outline Dimensions. 6/03-Rev. Rev. Updated Specifications Updated Absolute Maximum Ratings Changes Ordering Guide Updated Outline Dimensions. 2002-Revision Initial Version
Rev. Page
ADP3806 SPECIFICATIONS
100°C, unless otherwise noted. Table
Parameter BATTERY SENSE INPUT ADP3806-12.6 16.8 ADP3806-12.525 16.7 Input Resistance Input Current BATTERY SENSE INPUT VBAT Input Current Operating Input Current Shutdown OSCILLATOR Maximum Frequency Frequency Variation Charge Current Duty Cycle Threshold Maximum Duty Cycle Threshold SYNC Input High SYNC Input SYNC Input Current GATE DRIVE Resistance Rise, Fall Time Overlap Protection Delay Bias Current Refresh Threshold CURRENT SENSE AMPLIFIER Input Common-Mode Range Input Differential Mode Range Input Offset Voltage Gain5 Input Bias Current Input Offset Current Input Bias Current DRVL Shutdown Threshold SYSTEM CURRENT SENSE Input Common-Mode Range Input Differential Range Input Offset Voltage Input Bias Current, SYS+ Input Bias Current, SYS- Voltage Gain ISYS Output Range Limit Output Threshold Limit Output Voltage Symbol VBAT VBAT VBAT RBAT IBAT(SD) VBAT VBAT Conditions 25°C, 55°C 85°C Part operation Part shutdown 25°C, 85°C BATSEL open, part operation BATSEL GND, part shutdown -0.4 -0.6 -0.7 +0.4 +0.6 +0.7 +0.5 +0.7 Unit
-0.5 -0.7 1000
COMP COMP
SYNCH SYNCL ISYNC DRVL DRVH DRVL falling DRVH rising, DRVH falling DRVL rising Part shutdown, 12.6 VBST VCS+ VCS- VCS(CM) VCS(CM) VCC, part operation VCS(CM) Part shutdown Measured between VCS+ VCS- SYS+ SYS-, VISYS (VSYS+) (VSYS-) VSYS(DM) VSYS(CM) VSYS(DM) VSYS(CM) VSYS(CM) VSYS(CM) VLIMIT pull VISYS 2.65 ISINK
VCS(CM) VCS(DM) VCS(VOS) VCS(IB) VCS(IOS) VCS(SD) VSYS(CM) VSYS(DM) IB(SYS+) IB(SYS-) VISYS VTH(LIMIT) VO(LIMIT)
51.5
48.5
Rev. Page
ADP3806
Parameter ISET INPUT Charge Current Programming Function Programming Function Accuracy Symbol VISET/VCS Conditions VISET VISET VCS(CM) VISET 0.50 VCS(CM) 55°C, VISET VCS(CM) VISET VBSTREG IBSTREG VREG IREG VREF IREF 2.47 ISYON ISYOFF VUVLO external loads, UVLO external loads, Turn Turn High current mode ISINK current mode IDISCH VCS(OC) VBAT(OV) floating, VBAT 12.6 External 6.25 ±1.0 Unit
-46.7
ISET Bias Current BATSEL INPUT VBAT 12.6 VBAT 16.8 BATSEL Input Current BOOST REGULATOR OUTPUT Output Voltage Output Current ANALOG REGULATOR OUTPUT Output Voltage Output Current8 PRECISION REFERENCE OUTPUT Output Voltage Output Current8 SHUTDOWN (SD) Input Current POWER SUPPLY Supply Current Supply Current UVLO Threshold Voltage UVLO Hysteresis OUTPUT Output Voltage Output Voltage High OUTPUT REVERSE LEAKAGE PROTECTION Leakage Current OVERCURRENT COMPARATOR Overcurrent Threshold Response Time OVERVOLTAGE COMPARATOR Overvoltage Threshold Response Time
2.53
5.65
COMP
VBAT 120% COMP
limits temperature extremes guaranteed correlation using standard statistical quality control (SQC) methods. Guaranteed design, tested production. SYNC function used, then fSYNC must greater than less than 120% fCT. (VCS+) (VCS-). Accuracy guaranteed ISET input, programming function accuracy specification. System current sense active during shutdown. Load current supplied through SYS+ pin. Guaranteed output current from minimum specified value maintain regulation. VBAT final VBAT final
Rev. Page
ADP3806 ABSOLUTE MAXIMUM RATINGS
Table
Parameter Input Voltage (VCC) BAT, CS+, SYS+, SYS- PGND DRVL PGND ISET, BATSEL, SYNC, LIMIT, ISYS, COMP PGND Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering Sec) Ratings -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +0.3 100°C 115°C/W 125°C -65°C +150°C 300°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION
Rev. Page
ADP3806 CONFIGURATION FUNCTION DESCRIPTIONS
SYS- SYS+ ISYS LIMIT SYNC
DRVH BSTREG DRVL
VIEW PGND (Not Scale)
ADP3806
ISET BATSEL AGND
02611-002
COMP
Figure Configuration
Table Function Descriptions
Mnemonic SYS- SYS+ ISYS LIMIT SYNC COMP AGND BATSEL ISET PGND DRVL BSTREG DRVH Function Supply Voltage. Negative System Current Sense Input. Positive System Current Sense Input. System Current Sense Output. System Current Sense Limit Output. Oscillator Timing Capacitor. Oscillator Synchronization Pin. Analog Regulator Output. Precision Reference Output. Shutdown Control Input. External Compensation Node. Current Output. Analog Ground. Battery Sense Input. ADP3806. 12.525 16.7 ADP3806-12.5. 12.6 16.8 ADP3806-12.6. Battery Voltage Sense Input. High three cells, four cells. Charge Current Program Input. Negative Current Sense Input. Positive Current Sense Input. Power Ground. Drive Output. This switches between PGND. Regulator Output Boost. Floating Bootstrap Supply DRVH. High Drive Output. This switches between BST. Buck Switching Node Reference DRVH.
Rev. Page
ADP3806 TYPICAL PERFORMANCE CHARACTERISTICS
25°C
VREF ACCURACY
02611-003
NUMBER PARTS
-0.1 -0.2 -0.3 -0.4 -0.5
02611-006
-0.5
-0.4
-0.3
-0.2
-0.1
VBAT ACCURACY
TEMPERATURE (°C)
Figure VBAT Accuracy Distribution
VBAT ACCURACY -0.1 -0.2 -0.06
02611-004
Figure VREF Accuracy Temperature
0.10 0.08 0.06
VREF ACCURACY
25°C
0.04 0.02 -0.02 -0.04
-0.08 -0.10
-0.4
TEMPERATURE (°C)
Figure VBAT Accuracy Temperature
0.10
25°C
Figure VREF Accuracy
LOADS
0.05
SUPPLY CURRENT (mA)
VBAT ACCURACY
25°C
100°C
-0.05
02611-005
02611-008
-0.10
Figure VBAT Accuracy
Figure Supply Current
Rev. Page
02611-007
-0.3
ADP3806
SUPPLY CURRENT (mA)
02611-009
25°C fOSC 250kHz 25°C
VLIMIT
2.5V
1000 1500 2000 2500 3000
3500
VISYS
DRIVER LOAD CAPACITANCE (pF)
Figure Supply Current Driver Load Capacitance
Figure VLIMIT VISYS
SUPPPLY CURRENT (µA)
DRIVER RESISTANCE
100°C
DRIVER SOURCING DRIVER SINKING
25°C
02611-010
02611-013
10.0
12.5
15.0
17.5
20.0
TEMPERATURE (°C)
Figure Supply Current
25°C
Figure Driver Resistance Temperature
DRVH 5V/DIV
25°C
FREQUENCY (kHz)
DRVL 5V/DIV
02611-011
02611-014
200ns/DIV
(pF)
Figure Oscillator Frequency
Figure Driver Waveforms
Rev. Page
02611-012
ADP3806
CONVERSION EFFICIENCY
02611-015
VBAT 12.4V 25°C
CONVERSION EFFICIENCY
19VIN 85°C
02611-017
CHARGE CURRENT
VBAT
Figure Conversion Efficiency Charge Current
CONVERSION EFFICIENCY
ICHARGE ICHARGE
Figure Conversion Efficiency Battery Voltage Given Temperatures
VBAT
Figure Conversion Efficiency Battery Voltage
02611-016
25°C
Rev. Page
ADP3806 THEORY OPERATION
ADP3806 combines bootstrapped synchronous switching driver with programmable current control accurate final battery voltage control constant-current, constant-voltage (CCCV) Li-Ion battery charger. High accuracy voltage control needed safely charge Li-Ion batteries, which typically specified cell. typical notebook computer battery pack, three four cells series, giving total voltage 12.6 16.8 ADP3806 available three versions, selectable 12.525 16.7 output, selectable 12.6 16.8 output, adjustable output. adjustable output programmed wide range battery voltages using external precision resistors. Another requirement safely charging Li-Ion batteries accurate control charge current. actual charge current depends number cells parallel within battery pack. Typically, this range ADP3806 provides flexibility programming charge current over wide range. external resistor used sense charge current this voltage compared input voltage. This programmability allows current changed during charging. example, charge current reduced trickle charging. synchronous driver provides high efficiency when charging high currents. Efficiency important mainly reduce
FD56990A 22µF FD56990A 22µH 22µF 22nF 470nF SYS+ SYS- 470nF ISYS SYSTEM DC/DC
amount heat generated charger also stay within power limits adapter. With addition bootstrapped high side driver, ADP3806 drives external power NMOS transistors simple, lower cost power stage. ADP3806 also provides uncommitted current sense amplifier. This amplifier provides analog output monitoring current through external sense resistor. amplifier used anywhere system that high side current sensing needed.
CHARGE CURRENT CONTROL
AMP1 Figure differential input amplify voltage drop across external sense resistor RCS. input common-mode range from ground VCC, allowing current control short-circuit dropout conditions. gain AMP1 internally voltage drop across sense resistor. During constant current (CC) mode, forces voltage output AMP1 equal external voltage ISET pin. choosing VISET appropriately, wide range charge currents programmed.
CHARGE
VREF
BATTERY 12.6V/16.8V
2.2µF
100nF
DRVL
PGND
AMP2 R111 412k 0.1%
VREF VREG UVLO BIAS VREF
DRVLSD
DRVLSD 2.5V LIMIT
BSTREG 7.0V 0.1µF
LOGIC CONTROL
OSCILLATOR 100k
VREF
ADP3806
AGND
6.0V
2.5V
SYNC
COMP 0.22µF
200pF 100nF
180pF
412k 0.1%
ADP3806-12.6,
ADP3806-12.5: SHORT, OPEN; ADP3806, 412k, 102k, OPEN. OPEN FUNCTION USED.
Figure Typical Application
Rev. Page
02611-018
NOTES
BOOTSTRAPPED SYNCHRONOUS DRIVER
AMP1
ISET
SELECT 12.6V/16.8V
BATSEL
R141
6.81k 7.5k
ADP3806
Typical values range from input range ISET from example, charger required, could VISET power dissipation should kept below this example, power maximum Once been chosen, charge current adjusted during operation with VISET. Lowering VISET gives charge current trickle charging. component provide high frequency filtering current sense signal. reference internal resistor divider referenced AGND pin, which should connected close negative terminal battery minimize sensing errors. contrast, ADP3806 requires external, precision resistors. divider ratio should divide desired final voltage down
VBATTERY
FINAL BATTERY VOLTAGE CONTROL
battery approaches final voltage, ADP3806 switches from mode constant voltage (CV) mode. change achieved common output node gm2. Only outputs controls voltage COMP pin. Both amplifiers only pull down COMP, such that when either amplifier positive differential input voltage, output active. example, when battery voltage, VBAT, low, does control COMP. When battery voltage reaches desired final voltage, takes control loop, charge current reduced. Amplifier compares battery voltage internal reference voltage case ADP3806-12.5 ADP3806-12.6, internal resistor divider sets selectable final battery voltage. When BATSEL high, final battery voltage three cells (12.6 12.525 BATSEL tied this state. When BATSEL tied ground, VBAT equals four cells (16.8 16.7 BATSEL pull-up current failsafe select three cells when left open.
These resistors should have parallel impedance approximately minimize bias current errors. When ADP3806 shutdown, internal switch disconnects shown Figure This disconnects resistor (R11) from battery minimizes leakage. resistance internal switch less than
ADP3806
RR11 412k 0.1% BATTERY VREF BATSEL 102k 0.1%
Figure Battery Sense Disconnect Circuit
OSCILLATOR
oscillator generates triangle waveform between This compared voltage COMP pin, setting duty cycle driver stage. When VCOMP below duty cycle zero. Above duty cycle reaches maximum.
BSTREG
ADP3806
BOOTSTRAPPED SYNCHRONOUS DRIVER CMP3 CBST TIME DRVH
CMP2
DELAY
CMP1 DELAY
DRVL PGND
Figure Bootstrapped Synchronous Driver
Rev. Page
02611-020
DRVLSD
02611-019
ADP3806
oscillator frequency external capacitor internal current source according following formula: When charge current low, DRVLSD comparator signals driver turn side MOSFET DRVL held low. shown Figure DRVLSD comparator looks output AMP1. DRVLSD threshold corresponding differential voltage between pins. driver stage monitors voltage across capacitor with CMP3. When this voltage less than CMP3 forces minimum offtime This ensures that capacitor charged even during DRVLSD. However, because minimum time only forced when needed, maximum duty cycle greater than 99%.
fOSC
capacitor sets frequency kHz. frequency also synchronized external oscillator applying square wave input SYNC. SYNC function designed allow increases only oscillator frequency. fSYNC should more than higher than fOSC. duty cycle SYNC input important anywhere between 95%.
PRECISION REFERENCE
voltage compared internal precision, temperature drift reference reference available externally pin. This should bypassed with capacitor analog ground (AGND). reference used precision voltage externally. However, current draw should greater than noisy, switching type loads should connected.
BOOTSTRAP REGULATOR
driver stage powered internal bootstrap regulator available BSTREG pin. Because switching currents supplied this regulator, decoupling must added. capacitor should placed close ADP3806, with ground side connected close power ground (PGND). This supply recommended externally high switching noise.
REGULATOR
regulator supplies power most analog circuitry ADP3806. This regulator should bypassed AGND with capacitor. This reference source capability power external loads needed.
BOOTSTRAPPED SYNCHRONOUS DRIVER
comparator controls state synchronous driver shown Figure high output from comparator forces DRVH DRVL off. drivers have resistance approximately fast rise fall times when driving external MOSFETs. Furthermore, bootstrapped drive allows external NMOS transistor main switch instead PMOS. external boost diode should connected between BSTREG BST, boost capacitor must added externally between voltage between typically DRVL switches between BSTREG PGND. output BSTREG drives external NMOS with high lower resistance. PGND should connected close source external synchronous NMOS. When DRVL high, this turns lower NMOS pulls node ground. this point, boost capacitor charged through boost diode. When switches high, DRVL turned DRVH turns DRVH switches between When DRVH pulled input supply (typically rises above this voltage approximately Overlap protection included driver ensure that both external MOSFETs same time. When DRVH turns upper MOSFET, node goes inductor current. ADP3806 monitors voltage, DRVL goes high turn lower MOSFET when goes below When DRVL turns off, internal timer adds delay before turning DRVH.
ADP3806 provides current (LC) logic output signal when current sense voltage (VCS) below fixed threshold battery voltage greater than 95%. open-drain output that pulled when above threshold. When current threshold condition reached, pulled high external resistor another appropriate pull-up voltage. determine when goes low, internal comparator senses when current falls below 12.5% full scale across pins). comparator hysteresis prevent oscillation around trip point. prevent false triggering (such during soft start), comparator only enabled when battery voltage within final voltage. battery charges comparator does even current falls below 12.5% long battery voltage below full scale. Once battery risen above 95%, comparator enabled. This used indicate charge process.
SYSTEM CURRENT SENSE
uncommitted differential amplifier provided additional high side current sensing. This amplifier, AMP2, fixed gain from SYS+ SYS- pins analog output ISYS. ISYS source capability
Rev. Page
ADP3806
drive external load. common-mode range input pins from VCC. This amplifier only part ADP3806 that remains active during shutdown. power this block derived from bias current SYS+ SYS- pins. separate comparator LIMIT signals when voltage ISYS exceeds typically. internal comparator open-drain output that produces function shown Figure graph VLIMIT VISYS. LIMIT should externally pulled some other voltage needed through resistor. This graph taken with pull-up resistor When ISYS below LIMIT high output impedance. open-drain output capable sinking when threshold exceeded. This comparator turned during shutdown conserve power.
START-UP SEQUENCE
During startup from either going high exceeding UVLO threshold, ADP3806 initiates soft start sequence. soft start timing compensation capacitor COMP internal source. Initially, both DRVH DRVL held until COMP reaches This delay time
DELAY
ccomp
SHUTDOWN
high impedance CMOS logic input provided turn ADP3806. When voltage less than ADP3806 placed power shutdown. With exception system current sense amplifier, AMP2, other circuitry turned off. reference regulators pulled ground during shutdown switching stopped. During this state, supply current less than addition, BAT, CS+, CS-, pins high impedance minimize current drain from battery.
where ccomp capacitor COMP pin. 0.22 COMP capacitor, tDELAY After this initial delay, duty cycle very then ramps final value with same ramp rate given tDELAY. example, battery when charging started, duty cycle approximately 65%, corresponding VCOMP time duty cycle ramp from VCOMP VCOMP approximately Because charge current equal zero first, DRVL does turn However, capacitor discharged, DRVL forced minimum time each clock period until capacitor charged greater than Typically capacitor charged five clock cycles.
LOOP FEED FORWARD
described above, response time COMP slowed large compensation capacitor. speed response, comparators quickly feed forward around normal control loop pull COMP node down limit overshoot either short-circuit overvoltage conditions. overvoltage comparator trip point higher than final battery voltage. overcurrent comparator threshold across pins, which above maximum programmable threshold. When these comparators tripped, normal soft start sequence initiated. overvoltage comparator valuable when battery removed during charging. this case, current inductor causes output voltage spike comparator limits maximum voltage. Neither these comparators affects loop under normal charging conditions.
UVLO
Undervoltage lock-out, UVLO, included ADP3806 ensure proper startup. rises above reference regulators track until they reach their final voltages. However, rest circuitry held UVLO comparator. UVLO comparator monitors both regulators ensure they above before turning main charger circuitry. This occurs when reaches Monitoring regulator outputs ensures that charger circuitry driver stage have sufficient voltage operate normally. UVLO comparator includes hysteresis prevent oscillations near threshold.
Rev. Page
ADP3806 APPLICATION INFORMATION
DESIGN PROCEDURE
Refer Figure typical application circuit, following description. design follows that buck converter. With Li-Ion cells, important have regulator with accurate output voltage control. Where maximum peak-to-peak ripple 30%, that 0.3, maximum battery current, IBAT, MAX, used. example, with VIN, VBAT 12.6 IBAT, value calculated 18.9 Choosing closest standard value gives
BATTERY VOLTAGE SETTINGS
ADP3806 three options voltage selection: 12.525 V/16.7 selectable fixed voltages 12.6 V/16.8 selectable fixed voltages Adjustable
Output Capacitor Selection
output capacitor needed charger circuit absorb switching frequency ripple current smooth output voltage. value output ripple current given
Irms
,MAX
When using fixed versions, should short wire jumper should open circuit. When using adjustable version, following equation gives ratio resistors:
maximum value occurs when duty cycle 0.5. Thus
VBAT
Often 0.1% resistors required maintain overall accuracy budget design.
input voltage inductance, maximum current 0.26 typical ceramic capacitor good choice absorb this current.
Input Capacitor Ripple
case with normal buck converter, pulse current input high component. Therefore, since input capacitor absorb this current ripple, must have appropriate current rating. maximum input current given
Irms PBAT
Inductor Selection
Usually inductor chosen based assumption that inductor ripple current ±15% maximum output current maximum input voltage. long inductor value close this, system should work fine. final choice affects trade-offs between cost, size, efficiency. example, inductance lower, size smaller ripple current higher. This situation, taken far, leads higher losses core windings. Conversely, higher inductance results lower ripple current smaller output filter capacitors, transient response isslower. With these considerations, required inductance found from
(10)
where: estimated converter efficiency (approximately 90%, 0.9). PBAT maximum battery power consumed. This worst-case calculation and, depending total charge time, calculated number could relaxed. Consult capacitor manufacturer further technical information.
VIN, VBAT
Decoupling
good idea filter (R13 C14) from input voltage filter switching noise supply bypass chip. During layout, this capacitor should placed close possible. Values between recommended.
where maximum input voltage VIN, used with minimum duty ratio DMIN. duty ratio defined ratio output voltage input voltage, VBAT/VIN. ripple current found from
Rev. Page
ADP3806
Current-Sense Filtering
During normal circuit operation, current-sense signals have high frequency transients that need filtering ensure proper operation. case inputs, resistors filter capacitor (C13) value system current sense circuits, common-mode filtering from SYS+ SYS- ground needed. ceramic capacitors (C1, with resistors (R1, usually suffice. These time constants adjusted laboratory required represent good starting point. Upper PDISS RDS(ON) (IBAT IBAT Lower PDISS RDS(ON) (IBAT (IBAT f(12) where switching frequency switch transition time, usually first term accounts conduction losses second term estimates switching losses. Using these equations manufacturer's data sheets, proper device selected. Schottky diode (D1) parallel with conducts only during dead time between power MOSFETs. purpose prevent body diode lower N-channel MOSFET from turning which could cost much efficiency. option combined MOSFET with Schottky diode single package; these integrated packages often work better practice. Examples IRF7807D2 Si4832. (11)
MOSFET Selection
features ADP3806 that allows high-side NMOS switch instead more costly PMOS device. converter also uses synchronous rectification optimal efficiency. order high-side NMOS, internal bootstrap regulator automatically generates supply across Maximum output current determines RDS(ON) requirement power MOSFETs. When ADP3806 operating continuous mode, simplifying assumption made that MOSFETs always conducting load current. power dissipation each MOSFET given
Rev. Page
ADP3806 OUTLINE DIMENSIONS
7.90 7.80 7.70
4.50 4.40 4.30
6.40
0.65 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT JEDEC STANDARDS MO-153-AD
Figure 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown millimeters
ORDERING GUIDE
Model ADP3806JRU-REEL ADP3806JRU-REEL7 ADP3806JRUZ-REEL1 ADP3806JRUZ-REEL7 ADP3806JRU-12.5-RL ADP3806JRU-12.5-R7 ADP3806JRUZ-12.5RL1 ADP3806JRUZ-12.5-R71 ADP3806JRU-12.6-RL ADP3806JRU-12.6-R7 ADP3806JRUZ-12.6-RL1 ADP3806JRUZ-12.6-R71 Pb-free. Temperature Range 100°C 100°C 100°C 100°C 100°C 100°C 100°C 100°C 100°C 100°C 100°C 100°C Package Description Adjustable Adjustable Adjustable Adjustable 12.525 V/16.7 12.525 V/16.7 12.525 V/16.7 12.525 V/16.7 12.600 V/16.8 12.600 V/16.8 12.600 V/16.8 12.600 V/16.8 Package Option 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. C02611-0-11/06(C)
Rev. Page

Li-Ion battery charger Three battery voltage options Selectable 12.525

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