16-bit Hybrid Controller Pumps Engine management Compressors Step
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56F803
16-bit Hybrid Controller
Pumps Engine management Compressors Stepper Motors HVAC Conveyors Temperature control Automotive control readers General purpose devices Switched-mode power supplies
BENEFITS
On-board voltage regulator power management designed reduce overall system cost allowing single supply voltage Flash memory engineered provide reliable, non-volatile memory storage, eliminating need external storage devices Easy program with flexible application development tools Simple updating Flash memory through SPI, OnCETM, using on-chip boot loader Program boot directly from Flash Supports multiple processor connections Patented distortion correction reducing design risk better performance control modules tightly coupled reduce processing overhead voltage interrupts protect system during brownout power failure Simple interface with other asynchronous serial communication devices off-chip memory
56F803 member 56800 core-based family Hybrid Controllers. combines, single chip, processing power functionality microcontroller with flexible peripherals create extremely cost-effective solution. Because cost, configuration flexibility, compact program code, 56F803 well-suited many applications. 56800 core based Harvard-style architecture consisting three execution units operating parallel, allowing many operations instruction cycle. microprocessor-style programming model optimized instruction allow straightforward generation efficient, compact code both applications. instruction also highly efficient compilers enable rapid development optimized control applications.
56F803 16-BIT HYBRID CONTROLLER
MIPS 80MHz core frequency functionality unified, C-efficient architecture Hardware loops MCU-friendly instruction supports both controller functions: MAC, manipulation unit, addressing modes On-chip Flash Program Flash Data Flash Boot Flash Program Data 6-channel module 4-channel 12-bit ADCs Quadrature Decoder module Serial Communication Interface (SCI) Serial Peripheral Interface (SPI) general purpose Quad Timers JTAG/OnCE port debugging shared GPIO lines 100-pin LQFP package
COP/Watchdog Memory
Program Memory
ENERGY INFORMATION
Fabricated high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
Flash
On-chip regulators digital analog circuitry lower cost reduce noise Wait Stop modes available
Uses single 3.3V power supply
Boot Flash GPIO 16-Bit Quad Timers
56800 Core
MIPS
Dual 4-Channel ADC, 12-Bit
Power Mgmt
Data Memory
Quad Decoder 6-Channel
JTAG/OnCE
Flash
56800 CORE FEATURES
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture many Million Instructions Second (MIPS) 80MHz core frequency Single-cycle 16-bit parallel Multiplier-Accumulator (MAC) 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction with unique addressing modes Hardware loops Three internal address buses external address Four internal data buses external data Instruction supports both controller functions Controller-style addressing modes instructions compact code Efficient compiler local variable support Software subroutine interrupt stack with depth limited only memory JTAG/OnCE debug programming interface
56F803
PRODUCT DOCUMENTATION
DSP56800 Family Manual Detailed description 56800 family architecture, 16-bit core processor instruction
Order Number: DSP56800FM/D
DSP56F80x User's Manual Detailed description memory, peripherals, interfaces 56F801, 56F802, 56F803, 56F805, 56F807
Order Number: DSP56F801-7UM
DSP56F803 Technical Data Sheet Electrical timing specifications, descriptions, package descriptions Order Number: DSP56F803/D Summary description block diagram core, memory, peripherals interfaces Order Number: DSP56F803PB/D
56F803 MEMORY FEATURES
Harvard architecture permits many three simultaneous accesses program data memory On-chip memory including low-cost, high-volume Flash solution On-chip Flash Program Flash Data Flash Boot Flash Off-chip memory expansion capabilities much data memory much program memory
DSP56F803 Product Brief
AWARD-WINNING DEVELOPMENT ENVIRONMENT
Processor Expert(PE) technology provides rapid application design (RAD) tool that combines easy-to-use component-based software application creation with expert knowledge system. CodeWarriorIntegrated Development Environment (IDE) sophisticated tool code navigation, compiling debugging. comprehensive evaluation modules (EVMs) development system cards will support concurrent engineering. Together, CodeWarrior tool suite EVMs create comprehensive, scalable tools solution easy, fast efficient development.
Program Data
56F803 PERIPHERAL CIRCUIT FEATURES
Pulse Width Modulator module (PWM) with outputs, three Current Sense inputs, three Fault inputs, fault-tolerant design with dead-time insertion, supports both center- edge- aligned modes 12-bit Analog-to-Digital Converters (ADCs), which support simultaneous conversions; modules synchronized Quadrature Decoder general purpose Quad Timers module Serial Communication Interface (SCI) Serial Peripheral Interface (SPI) Computer Operating Properly (COP)/ Watchdog timer dedicated external interrupt pins Sixteen multiplexed General Purpose (GPIO) pins External reset input hardware reset JTAG/OnCEfor unobtrusive, processor speed-independent debugging Software-programmable, Phase Lock Loop-based frequency synthesizer
ORDERING INFORMATION
PART
DSP56F803 DSP56F803
SUPPLY VOLTAGE
3.0-3.6V 3.0-3.6V
PACKAGE TYPE
Low-profile Quad Flat Pack (LQFP) Low-profile Quad Flat Pack (LQFP)
COUNT
FREQUENCY (MHz)
ORDER NUMBER
DSP56F803BU80 SPAK56F803BU80
Motorola stylized Logo registered U.S. Patent Trademark Office. This product incorporates SuperFlash® technology licensed from SST. other product service names property their respective owners. Motorola, Inc. 2003
DSP56F803PB/D
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