SDRAM DIMM JEDEC standard 184-pin, unbuffered dual in-line memory

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SDRAM DIMM JEDEC standard 184-pin, unbuffered dual in-line memory

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64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
SDRAM DIMM
JEDEC standard 184-pin, unbuffered dual in-line memory module (DDR DIMM) Utilizes MT/s 333MT/s SDRAM components Fast data transfer rates: PC2100 PC2700 64MB 64), 128MB 64), 256MB VDD= VDDQ= +2.5V VDDSPD +2.3V +3.6V 2.5V (SSTL_2 compatible) Commands entered each positive edge edge-aligned with data READs; centeraligned with data WRITEs Internal, pipelined double data rate (DDR) architecture; data accesses clock cycle Bidirectional data strobe (DQS) transmitted/ received with data-i.e., source-synchronous data capture Differential clock inputs CK#) Four internal device banks concurrent operation Selectable burst lengths: Auto precharge option Auto Refresh Self Refresh Modes: 15.625µs (64MB); 7.8125µs (128MB, 256MB) maximum average periodic refresh interval. Serial Presence Detect (SPD) with EEPROM Selectable READ latency maximum compatibility Gold edge contacts
latest data sheet, please refer Micron site: www.micron.com/products/modules
MT4VDDT864A 64MB MT4VDDT1664A 128MB MT4VDDT3264A 256MB
Figure 184-Pin DIMM (MO-206)
OPTIONS
MARKING
Operating Temperature Range Commercial (0°C +70°C) None Industrial (-40°C +85°C)1 Package 184-pin DIMM (Standard) 184-Pin DIMM (Lead-free)1 Memory Clock, Speed, Latency2 6ns, MT/s (167 MHz), -335 7.5ns, MT/s (133 MHz), -2621 7.5ns, MT/s (133 MHz), -26A1 7.5ns, MT/s (133 MHz), -265 1.25in. (31.75mm) page note
NOTE: Consult Micron product availability. Device (READ) Latency.
Table
Address Table
64MB 128MB 256MB (A0-A11) (BA0, BA1) 128Mb (A0-A8) (S0#) 8K(A0-A12) 8K(A0-A12) (BA0, BA1) (BA0, BA1) 256Mb 512Mb (A0-A8) (A0-A9) (S0#) (S0#)
Refresh Count Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
©2004 Micron Technology, Inc.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Table Part Numbers Timing Parameters
MODULE DENSITY 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB CONFIGURATION MODULE BANDWITH 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s GB/s GB/s GB/s GB/s GB/s GB/s 2.1GB/s 2.1GB/s GB/s GB/s GB/s GB/s GB/s GB/s 2.1GB/s 2.1GB/s MEMORY CLOCK, DATA RATE 6ns, 333MT/s 6ns, 333MT/s 7.5ns, 266MT/s 7.5ns, 266MT/s 7.5ns, 266MT/s 7.5ns, 266MT/s 7.5ns, MT/s 7.5ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 6ns, MT/s 6ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s 7.5ns, MT/s CLOCK LATENCY tRCD tRP) 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3
PART NUMBER MT4VDDT864A(I)G-335_ MT4VDDT864A(I)Y-335_ MT4VDDT864A(I)G-262_ MT4VDDT864A(I)Y-262_ MT4VDDT864A(I)G-26A_ MT4VDDT864A(I)Y-26A_ MT4VDDT864A(I)G-265_ MT4VDDT864A(I)Y-265_ MT4VDDT1664A(I)G-335_ MT4VDDT1664A(I)Y-335_ MT4VDDT1664A(I)G-262_ MT4VDDT1664A(I)Y-262_ MT4VDDT1664A(I)G-26A_ MT4VDDT1664A(I)Y-26A_ MT4VDDT1664A(I)G-265_ MT4VDDT1664A(I)Y-265_ MT4VDDT3264A(I)G-335_ MT4VDDT3264A(I)Y-335_ MT4VDDT3264A(I)G-262_ MT4VDDT3264A(I)Y-262_ MT4VDDT3264A(I)G-26A_ MT4VDDT3264A(I)Y-26A_ MT4VDDT3264A(I)G-265_ MT4VDDT3264A(I)Y-265_
NOTE:
part numbers with two-place code (not shown), designating component revisions. Consult factory current revision codes. Example: MT4VDDT1664AG-265A1.
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Table Assignment (184-Pin DIMM Front)
DQ17 DQS2 DQ18 VDDQ DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40 VDDQ DQ41 CAS# DQS5 DQ42 DQ43 DQ48 DQ49 CK2# VDDQ DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59
Table
Assignment (184-Pin DIMM Back)
DQ21 DQ22 DQ23 DQ28 DQ29 VDDQ DQ30 DQ31 VDDQ CK0# VDDQ DQ36 DQ37 DQ38 DQ39 DQ44 RAS# DQ45 VDDQ DQ46 DQ47 VDDQ DQ52 DQ53 DQ54 DQ55 VDDQ DQ60 DQ61 DQ62 DQ63 VDDQ VDDSPD
SYMBOL SYMBOL SYMBOL SYMBOL
NOTE:
SYMBOL SYMBOL SYMBOL SYMBOL VDDQ VDDQ DQ12 DQ13 DQ14 DQ15 VDDQ DQ20 NC/A12
VREF DQS0 DQS1 VDDQ CK1# DQ10 DQ11 CKE0 VDDQ DQ16
connect (NC) 64MB, address input 128MB, 256MB.
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
184-Pin DIMM Pinouts
Front View
Back View
Components This Side Module
Indicates VDDQ
Indicates
Table
Descriptions
SYMBOL WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, (along with define command being entered. Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge CK#. Output data (DQs DQS) referenced crossings CK#. Clock Enable: HIGH activates deactivates internal clock, input buffers, output drivers. Taking provides PRECHARGE POWER-DOWN SELF REFRESH operations (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE device bank). synchronous POWER-DOWN entry exit, SELF REFRESH entry. asynchronous SELF REFRESH exit disabling outputs. must maintained HIGH throughout read write accesses. Input buffers (excluding CKE) disabled during POWER-DOWN. Input buffers (excluding CKE) disabled during SELF REFRESH. SSTL_2 input will detect LVCMOS level after applied until first brought HIGH. After brought HIGH, becomes SSTL_2 input only. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied.
numbers correlate with symbols; refer Assignment tables page more information NUMBERS 137,
Input
Input
BA0,
Input
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Table Descriptions
SYMBOL A0-A11 (64MB) A0-A12 (128MB, 256MB) TYPE Input DESCRIPTION Address Inputs: Provide address ACTIVE commands, column address auto precharge (A10) READ/WRITE commands, select location memory array respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). address inputs also provide op-code during MODE REGISTER command. define which mode register (mode register extended mode register) loaded during LOAD MODE REGISTER command. Serial Presence-Detect Data: bidirectional used transfer addresses data into presencedetect portion module. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Presence-Detect Address Inputs: These pins used configure presence-detect device. Data Write Mask: allows WRITE operation. HIGH blocks WRITE operation. lines affect READ operation. Data Strobe: Output with READ data, input with WRITE data. edge-aligned with READ data, centered WRITE data. Used capture data. Data I/Os: Data bus. numbers correlate with symbols; refer Assignment tables page more information NUMBERS (128MB, 256MB), 118, 122, 125, 130,
Input/ Output Input Input Input/ Output Input/ Output Input/ Output
181, 182, 107, 119, 129, 149, 159, 169,
SA0-SA2 DM0-DM7
DQS0-DQS7
105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 104, 112, 128, 136, 143, 156, 164, 172, 108, 120, 148, 100, 116, 124, 132, 139, 145, 152, 160, 101, 102, 103, 113, (64MB), 158, 163, 167, 111, 134, 135, 140, 142,
DQ0-DQ63
VREF VDDQ
Supply Supply
SSTL_2 reference voltage. Power Supply: +2.5V ±0.2V.
Supply Supply
Power Supply: +2.5V ±0.2V. Ground.
VDDSPD
Supply
Serial EEPROM positive power supply: +2.3V +3.6V. Connect: These pins should left unconnected.
Use: These pins connected this module assigned pins other modules this product family.
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Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Figure Functional Block Diagram
DQS0 DM0/DQS9
UDQS LDQS UDQS LDQS
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS5 DM5/DQS14
UDQS LDQS
DQS1 DM1/DQS10
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS7 DM7/DQS16
UDQS LDQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SERIAL
BA0-BA1 A0-A11 (64MB) A0-A12 (128MB, 256MB) RAS# CAS# CKE0
SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS
VDDSPD VDDQ VREF
SPD/EEPROM SDRAMS SDRAMS SDRAMS SDRAMS
CK0#
9.0pF
CK1# SDRAMs CK2# SDRAMs
NOTE:
Standard modules following SDRAM devices: MT46V8M16TG (64MB); MT46V16M16TG (128MB); MT46V32M16TG (256MB) Unless otherwise noted, resistor values wiring differ from that described this drawing; however Lead-free modules following SDRAM devices: relationships maintained shown. MT46V8M16P (64MB); MT46V16M16P (128MB); MT46V32M16P (256MB) industry standard, Micron modules utilize various component speed grades, referenced module part numbering guide Contact factory availability Ind. Temp. DIMMs. www.micron.com/numberguide.
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
General Description
MT4VDDT864A, MT4VDDT1664A, MT4VDDT3264A high-speed CMOS, dynamic random-access, 64MB, 128MB, 256MB memory modules organized configuration. SDRAM modules internally configured quad-bank SDRAM devices. SDRAM modules double data rate architecture achieve high-speed operation. double data rate architecture essentially 2n-prefetch architecture with interface designed transfer data words clock cycle pins. single read write access SDRAM modules effectively consists single 2n-bit wide, one-clock-cycle data transfer internal DRAM core corresponding n-bit wide, one-half-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. intermittent strobe transmitted SDRAM during READs memory controller during WRITEs. edge-aligned with data READs center-aligned with data WRITEs. SDRAM modules operate from differential clocks (CK, CK#); crossing going HIGH going will referred positive edge Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 (64MB) A0-A12 (128MB, 256MB) select device row). address bits registered coincident with READ WRITE command used select device bank starting device column location burst access. SDRAM modules provide programmable read write burst lengths locations. auto precharge function enabled provide self-timed precharge that initiated burst access. pipelined, multibank architecture SDRAM modules allows concurrent operation,
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided, along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2, Class compatible. more information regarding SDRAM operation, refer 128Mb, 256Mb, 512Mb SDRAM component data sheets.
Serial Presence-Detect Operation
SDRAM modules incorporate serial presencedetect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals, together with (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Mode Register Definition
mode register used define specific mode operation SDRAM devices. This definition includes selection burst length, burst type, latency operating mode, shown Figure Mode Register Definition Diagram, page mode register programmed MODE REGISTER command (with will retain stored information until programmed again device loses power (except which self-clearing). Reprogramming mode register will alter contents memory, provided performed correctly. mode register must loaded (reloaded) when device banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Mode register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A11 (64MB), A7-A12 (128MB, 256MB) specify operating mode.
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Burst Length
Read write accesses SDRAM devices burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3Ai when burst length eight (where most significant column address given configuration Note Table Burst Definition Table, page values). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both read write bursts.
Figure Mode Register Definition Diagram
64MB Module
Address
Operating Mode Latency Burst Length
Mode Register (Mx)
(BA1 BA0) must select base mode register (vs. extended mode register).
128MB, 256MB Modules
Address
Operating Mode (BA1 BA0) must select base mode register (vs. extended mode register).
Latency Burst Length
Mode Register (Mx)
Burst Length Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table, page
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Read Latency
READ latency delay, clock cycles, between registration READ command availability first output data. latency clocks, shown Figure Latency Diagram. READ command registered clock edge latency clocks, data will available nominally coincident with clock edge Figure Latency (CL) Table, page indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
M6-M0 Valid Valid
Operating Mode Normal Operation Normal Operation/Reset other states reserved
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64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Table Burst Definition Table
STARTING COLUMN ADDRESS ORDER ACCESSES WITHIN BURST TYPE SEQUENTIAL 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Figure Latency Diagram
COMMAND
READ
BURST LENGTH
COMMAND
READ
Burst Length cases shown Shown with nominal tAC, tDQSCK, tDQSQ TRANSITIONING DATA DON'T CARE
NOTE:
Operating Mode
normal operating mode selected issuing MODE REGISTER command with bits A7-A11 (64MB) A7-A12 (128MB, 256MB) each zero, bits A0-A6 desired values. reset initiated issuing MODE REGISTER command with bits A9-A11 (64MB) A9-A12 (128MB, 256MB) each zero, one, bits desired values. Although required Micron device, JEDEC specifications recommend when LOAD MODE REGISTER command issued reset DLL, should always followed LOAD MODE REGISTER command select normal operating mode. other combinations values A7-A11 (64MB) A7-A12 (128MB, 256MB) reserved future and/or test modes. Test modes reserved states should used because unknown operation incompatibility with future versions result.
burst length two, A1-Ai select two-dataelement block; selects first access within block. burst length four, A2-Ai select four-dataelement block; A0-A1 select first access within block. burst length eight, A3-Ai select eight-dataelement block; A0-A2 select first access within block. Whenever boundary block reached within given sequence above, following access wraps within block. (64MB, 128MB) (256MB).
Table
Latency (CL) Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ)
SPEED -335 -262 -26A -265
Extended Mode Register
extended mode register controls functions beyond those controlled mode register; these additional functions enable/disable output drive strength. These functions controlled bits shown inFigure Extended Mode Register Definition Diagram, page extended mode register programmed LOAD MODE REGIS-
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64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
command mode register (with will retain stored information until programmed again device loses power. enabling should always followed LOAD MODE REGISTER command mode register (BA0/BA1 both low) reset DLL. extended mode register must loaded when device banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements could result unspecified operation.
Figure Extended Mode Register Definition Diagram
64MB Module
Address
Operating Mode
Extended Mode Register (Ex)
128MB, 256MB Modules
Address
Output Drive Strength
normal full drive strength outputs specified SSTL2, Class supports option reduced drive. This option intended support lighter load and/or point-to-point environments. selection reduced drive strength will alter DQSs from SSTL2, Class drive strength reduced drive strength, which approximately percent SSTL2, Class drive strength. detailed information programmable reduced drive strength option, refer 128Mb, 256Mb, 512Mb SDRAM component data sheets.
Operating Mode
Extended Mode Register (Ex)
Valid
Enable Disable Drive Strength Normal Reduced
Operating Mode Normal Operation other states reserved
Enable/Disable
must enabled normal operation. enable required during power-up initialization upon returning normal operation after having disabled purpose debug evaluation. (When device exits self refresh mode, enabled automatically.) time enabled, clock cycles must occur before READ command issued.
NOTE:
(E13 64MB, 128MB 256MB) must select Extended Mode Register (vs. base Mode Register). QFC# option supported.
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Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Commands
Table Commands Truth Table, Table Operation Truth Table, provide general reference available commands. more detailed description commands operations, refer 128Mb, 256Mb, 512Mb SDRAM component data sheet.
Table
Commands Truth Table
RAS# CAS# ADDR Bank/Row Bank/Col Bank/Col Code Op-Code NOTES
HIGH commands shown except SELF REFRESH; states sequences shown illegal reserved NAME (FUNCTION) DESELECT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
NOTE:
DESELECT functionally interchangeable. BA0-BA1 provide device bank address A0-A11 (64MB) A0-A12 (128MB, 256MB) provide address. BA0-BA1 provide device bank address; A0-A9 (64MB, 128MB) A0-A9, (256MB) provide column address; HIGH enables auto precharge feature (nonpersistent), disables auto precharge feature. Applies only read bursts with auto precharge disabled; this command undefined (and should used) READ bursts with auto precharge enabled WRITE bursts. LOW: BA0-BA1 determine which device bank precharged. HIGH: device banks precharged BA0- "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. BA0-BA1 select either mode register extended mode register (BA0 select mode register; select extended mode register; other combinations BA0-BA1 reserved). A0-A11 (64MB) A0-A12 (128MB, 256MB) provide op-code written selected mode register.
Table
Operation Truth Table
Valid
Used mask write data; provided coincident with corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit
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Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVDD Supply Voltage Relative +3.6V VDDQ Supply Voltage Rel. +3.6V VREF Inputs Voltage Relative +3.6V Pins Voltage Relative Vss. -0.5V VDDQ +0.5V tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Operating Temperature, (ambient commercial) +70°C (ambient industrial) -40°C +85°C Storage Temperature (plastic) -55°C +150°C Short Circuit Output Current. 50mA
Table Electrical Characteristics Operating Conditions
Notes: 1-5, notes appear pages 18-21; +70°C PARAMETER/CONDITION Supply Voltage Supply Voltage Reference Voltage Termination Voltage (system) Input High (Logic Voltage Input (Logic Voltage INPUT LEAKAGE CURRENT input, VDD, VREF 1.35V (All other pins under test SYMBOL VDDQ VREF VIH(DC) VIL(DC) IOHR IOLR UNITS 16.8 NOTES
OUTPUT LEAKAGE CURRENT pins disabled; VOUT VDDQ) OUTPUT LEVELS: Full drive option High Current (VOUT VDDQ 0.373V, minimum VREF, minimum VTT) Current (VOUT 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option High Current (VOUT VDDQ 0.763V, minimum VREF, minimum VTT) Current (VOUT 0.763V, maximum VREF,maximum VTT)
Command/ Address,
0.49 VDDQ 0.51 VDDQ VREF 0.04 VREF 0.04 VREF 0.15 -0.3 VREF 0.15 -16.8
Table Input Operating Conditions
Notes: 1-5, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION Input High (Logic Voltage Input (Logic Voltage Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) VREF 0.310 0.49 VDDQ VREF 0.310 0.51 VDDQ UNITS NOTES
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64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Table Specifications Conditions 64MB
SDRAM components only Notes: 1-5, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cycle; Address control inputs changing once every clock cycles. OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle. PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); LOW. IDD0 -335 -262 -26A/ -265 UNITS NOTES
IDD1
IDD2P
IDD2F IDLE STANDBY CURRENT: HIGH; device banks idle; (MIN); HIGH; Address other control inputs changing once clock cycle. VREF DQS, IDD3P ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); LOW. IDD3N ACTIVE STANDBY CURRENT: HIGH; HIGH; device tRAS (MAX); (MIN); bank; Active-Precharge; inputs changing twice clock cycle; Address other control inputs changing once clock cycle. IDD4R OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT 0mA. IDD4W OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle. tREFC tRFC (MIN) IDD5 AUTO REFRESH CURRENT
tREFC
1,060 1,540
1,000 1,500
1,000 1,500
15.625µs
IDD5A IDD6 IDD7
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four device bank interleaving READs with auto precharge, (MIN); (MIN); Address control inputs change only during Active, READ, WRITE commands.
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Table Specifications Conditions 128MB
SDRAM components only Notes: 1-5, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cycle; Address control inputs changing once every clock cycles. OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle. PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); LOW. IDLE STANDBY CURRENT: HIGH; device banks idle; (MIN); HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); LOW. ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; tRAS (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle. OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT 0mA. OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle. tREFC tRFC (MIN) AUTO REFRESH CURRENT
tREFC
IDD0
-335
-262
-26A/ -265
UNITS
NOTES
IDD1
IDD2P IDD2F
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD5A IDD6 IDD7
1,020 1,760
1,520
1,520
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four device bank interleaving READs with auto precharge, (MIN); (MIN); Address control inputs change only during Active, READ, WRITE commands.
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Table Specifications Conditions 256MB
SDRAM components only Notes: 1-5, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V PARAMETER/CONDITION OPERATING CURRENT: device bank; Active-Precharge; (MIN); (MIN); inputs changing once clock cycle; Address control inputs changing once every clock cycles. OPERATING CURRENT: device bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle. PRECHARGE POWER-DOWN STANDBY CURRENT: device banks idle; Power-down mode; (MIN); LOW. IDLE STANDBY CURRENT: HIGH; device banks idle; (MIN); HIGH; Address other control inputs changing once clock cycle. VREF DQS, ACTIVE POWER-DOWN STANDBY CURRENT: device bank active; Power-down mode; (MIN); LOW. ACTIVE STANDBY CURRENT: HIGH; HIGH; device bank; Active-Precharge; tRAS (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle. OPERATING CURRENT: Burst Reads; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); IOUT 0mA. OPERATING CURRENT: Burst Writes; Continuous burst; device bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle. tREFC tRFC (MIN) AUTO REFRESH CURRENT
tREFC
IDD0
-335
-262
-26A/ -265
UNITS
NOTES
IDD1
IDD2P IDD2F
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD5A IDD6 IDD7
1,160 1,620
1,160 1,600
1,120 1,400
7.8125µs
SELF REFRESH CURRENT: 0.2V OPERATING CURRENT: Four device bank interleaving READs with auto precharge, (MIN); (MIN); Address control inputs change only during Active, READ, WRITE commands.
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Table Capacitance
Note: notes appear pages 18-21 PARAMETER Input/Output Capacitance: DQS/DM Input Capacitance: Command Address: Input Capacitance: CK0, CK0# Input Capacitance: CK1, CK1#; CK2, CK2# SYMBOL 10.0 12.0 12.0 UNITS
Table SDRAM Component Electrical Characteristics Recommended Operating Conditions
Notes: 1-5, 13-15, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER Access window from CK/CK# high-level width low-level width Clock cycle time input hold time relative input setup time relative input pulse width (for each input) Access window from CK/CK# input high pulse width input pulse width DQS-DQ skew, last valid, group, access Write command first latching transition falling edge rising setup time falling edge from rising hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address control input hold time (fast slew rate) Address control input setup time (fast slew rate) Address control input hold time (slow slew rate) Address control input setup time (slow slew rate) Address Control input pulse width (for each input)
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
-335 SYMBOL
-262 -0.75 0.45 0.45 7.5/10 1.75 +0.75 0.55 0.55
-26A/-265 -0.75 0.45 0.45 7.5/10 1.75 UNITS NOTES +0.75 0.55 0.55
-0.7 0.45 0.45 0.45 0.45 1.75 -0.60 0.35 0.35
+0.7 0.55 0.55
(2.5)
tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH
+0.60
-0.75 0.35 0.35
+0.75
-0.75 0.35 0.35
+0.75
0.45 0.75
tCH,tCL
0.75
tCH,tCL
0.75
tCH,tCL
1.25
1.25
1.25
-0.70 0.75 0.75 0.80 0.80
+0.70 -0.75 0.90 0.90
+0.75 -0.75
+0.75
tIPW
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Table SDRAM Component Electrical Characteristics Recommended Operating Conditions (Continued)
Notes: 1-5, 13-15, notes appear pages 18-21; +70°C; VDDQ +2.5V ±0.2V CHARACTERISTICS PARAMETER LOAD MODE REGISTER command cycle time DQ-DQS hold, first non-valid, access Data hold skew factor ACTIVE PRECHARGE command ACTIVE READ with Auto precharge command ACTIVE ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE READ WRITE delay PRECHARGE command period read preamble read postamble ACTIVE bank ACTIVE bank command write preamble write preamble setup time write postamble Write recovery time Internal WRITE READ command delay Data valid output window REFRESH REFRESH command interval Average periodic refresh interval 64MB 128MB, 256MB 64MB 128MB, 256MB SYMBOL
-335
-262
-26A/-265
UNITS NOTES 0.75
0.55 70,000
0.75 120,000
tQHS tQHS
tQHS
tQHS
0.25
120,000
tRFC tRCD tRPRE tRPST tRRD tWPRE tWPRES tWPST tWTR
0.25
-tDQSQ
0.25
-tDQSQ
tREFC
-tDQSQ
140.6 70.3 15.6
140.6 70.3 15.6
140.6 70.3 15.6
tREFI tVTD tXSNR
Terminating voltage delay Exit SELF REFRESH non-READ command Exit SELF REFRESH READ command
XSRD
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Notes
voltages referenced VSS. Tests timing, IDD, electrical characteristics conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. Outputs measured with equivalent load:
Reference Point 30pF
Output (VOUT)
timing tests VIL-to-VIH swing 1.5V test environment, input timing still referenced VREF crossing point CK/CK#), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals used test device 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e., receiver will effectively switch result signal crossing input level, will remain that state long signal does ring back above [below] input [HIGH] level). VREF expected equal VDDQ/2 transmitting device track variations level same. Peak-to-peak noise (non-common mode) VREF exceed percent value. Thus, from VDDQ/2, VREF allowed ±25mV error additional ±25mV noise. This measurement taken nearest VREF bypass capacitor. applied directly device. system supply signal termination resistors, expected equal VREF must track variations level VREF. dependent output loading cycle rates. Specified values obtained with minimum cycle time -262, -26A, -335 -265 with outputs open. Enables on-chip refresh address counters. specifications tested after device properly initialized, averaged defined cycle rate. This parameter sampled. +2.5V ±0.2V, VDDQ +2.5V ±0.2V, VREF VSS, MHz,
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
25°C, VOUT (DC) VDDQ/2, VOUT (peak peak) 0.2V. input grouped with pins, reflecting fact that they matched loading. slew rates less than V/ns greater than equal V/ns. slew rate less than V/ns, timing must derated: additional 50ps each 100mV/ns reduction slew rate from 500mV/ns, while unaffected. slew rate exceeds 4.5V/ns, functionality uncertain. CK/CK# input reference level (for timing referenced CK/CK#) point which cross; input reference level signals other than CK/CK# VREF. Inputs recognized valid until VREF stabilizes. Exception: during period before VREF stabilizes, VDDQ recognized LOW. output timing reference level, measured timing reference point indicated Note VTT. transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ) begins driving (LZ). intent Don't Care state after completion postamble DQS-driven signal should either high, low, high-Z that signal transition within input switching region must follow valid input requirements. That transitions high [above VIHDC (MIN)] then must transition (below VIHDC) prior DQSH(MIN). This device limit. device will operate with negative value, system performance could degraded turnaround. recommended that valid (HIGH LOW) before WRITE command. case shown (DQS going from High-Z logic LOW) applies when WRITEs were previously progress bus. previous WRITE progress, could HIGH during this time, depending tDQSS. (tRC tRFC) measurements smallest multiple that meets minimum absolute value respective parameter. tRAS (MAX) measurements largest multiple that meets maximum absolute value tRAS. refresh period 64ms. This equates average refresh rate 15.625µs (64MB) 7.8125µs (128MB, 256MB). However, AUTO REFRESH command must asserted least once every
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140.6µs (64MB) 70.3µs (128MB, 256MB); burst refreshing posting DRAM controller greater than eight refresh cycles allowed. valid data window derived achieving other specifications: (tCK/2), tDQSQ, (tQH tQHS). data valid window derates directly porportional with clock duty cycle practical data valid window derived. clock allowed maximum duty cycle variation 45/55, beyond which functionality uncertain. Figure Derating Data Valid Window (tQH tQHS), shows derating curves duty cycles ranging between 50/50 45/55. Each byte lane corresponding DQS. This limit actually nominal value does result fail value. HIGH during REFRESH command period (tRFC [MIN]) else (i.e., during standby). maintain valid level, transitioning edge input must: Sustain constant slew rate from current level through target level, (AC) (AC). Reach least target level. After target level reached, continue maintain least target level, (DC) (DC). JEDEC specifies input slew rate must 1V/ns (2V/ns differentially). input slew rates must deviate from more than percent. DM/DQS slew rate less than 0.5V/ns, timing must derated: 50ps must added each 100mv/ns reduction slew rate. slew rate exceeds 4V/ns, functionality uncertain. must vary more than percent active while bank active. clock allowed ±150ps jitter. Each timing parameter allowed vary same amount. lesser minimum minimum actually applied device inputs, collectively during bank active. READs WRITEs with auto precharge allowed issued until tRAS (MIN) satisfied prior internal precharge command being issued.
Figure Derating Data Valid Window
(tQH
3.750 3.700
tQHS)
3.650
3.600
3.550 3.500 3.450 3.400 3.350 3.300
-335 -262/-26A/-265 10ns -262/-26A/-265 7.5ns
3.250
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 Clock Duty Cycle
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47/53
46.5/54.5
46/54
45.5/55.5
45/55
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
positive glitch nominal voltage must less than clock more than +400mV 2.9V, whichever less. negative glitch must less than clock cycle exceed either 300mV 2.2V, whichever more positive. However, average cannot below 2.3V minimum. Normal Output Drive Curves: full variation driver pull-down current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Normal Drive Pull-Down Characteristics. variation driver pull-down current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Normal Drive Pull-Down Characteristics. full variation driver pull-up current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Normal Drive Pull-Up Characteristics. variation driver pull-up current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Normal Drive Pull-Up Characteristics. full variation ratio maximum minimum pull-up pull-down current should between 0.71 1.4, device drain-to-source voltages from 0.1V Volt, same voltage temperature. full variation ratio nominal pull-up pull-down current should unity percent, device drain-to-source voltages from 0.1V 1.0V. Reduced Output Drive Curves: a)The full variation driver pull-down current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Reduced Drive PullDown Characteristics, page b)The variation driver pull-down current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Reduced Drive Pull-Down Characteristics, page c)The full variation driver pull-up current from minimum maximum process, temperature voltage will within outer bounding lines curve Figure Reduced Drive Pull-Up Characteristics, page d)The variation driver pull-up current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figure Reduced Drive Pull-Up Characteristics, page e)The full variation ratio maximum minimum pull-up pull-down current should between 0.71 1.4, device drain-to-source voltages from 0.1V 1.0V, same voltage.
Figure Normal Drive Pull-Down Characteristics
Figure Normal Drive Pull-Up Characteristics
Maxim
Nominal high
IOUT (mA)
Maximum
Nominal high
IOUT (mA)
-100 -120 -140 -160
Nominal
inal
Minimum
-180 -200
VOUT
VDDQ VOUT
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Figure Reduced Drive Pull-Down Characteristics
IOUT (mA)
Figure Reduced Drive Pull-Up Characteristics
imum
Minimum
Nominal
Nominal high
IOUT (mA)
VOUT
Nominal
Minimum
VDDQ VOUT
)The full variation ratio nominal pull-up pull-down current should unity percent, device drain-to-source voltages from 0.1V 1.0V. voltage levels used derived from minimum level referenced test load. practice, voltage levels obtained from properly terminated will provide significantly different voltage values. overshoot: (MAX) VDDQ 1.5V pulse width pulse width greater than cycle rate. undershoot: (MIN) -1.5V pulse width pulse width greater than cycle rate. VDDQ must track each other. (MAX) takes precedence over tDQSCK (MAX) tRPST (MAX) condition. (MIN) will prevail over tDQSCK (MIN) tRPRE (MAX) condition. tRPST point tRPRE begin point referenced specific voltage level specify when device output longer driving (tRPST), begins driving (tRPRE). During initialization, VDDQ, VTT, VREF must equal less than 0.3V. Alternatively, 1.35V maximum during power even VDD/VDDQ provided minimum series resistance used between supply input pin. -335, -262, -26A -265 speed grades, IDD3N specified 35mA SDRAM MHz.
current Micron part operates below slowest JEDEC operating frequency MHz. such, future reflect this option. Random addressing changing percent data changing every transfer. Random addressing changing percent data changing every transfer. must active (high) during entire time refresh command executed. That from time AUTO REFRESH command registered, must active each rising clock edge, until tREF later. IDD2N specifies DQS, driven valid high logic level. IDD2Q similar IDD2F except IDD2Q specifies address control inputs remain stable. Although IDD2F, IDD2N, IDD2Q similar, IDD2F "worst case." Whenever operating frequency altered, including jitter, required reset. This followed clock cycles. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes. When input signal HIGH LOW, defined steady state logic HIGH LOW. -335 speed grade will operate with tRAS (MIN) 40ns tRAS (MAX) 120,000ns slower frequency.
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Initialization
ensure device operation DRAM must initialized described below: Simultaneously apply power VDDQ. Apply VREF then power. Assert hold LVCMOS logic low. Provide stable CLOCK signals. Wait least 200µs. Bring high provide least DESELECT command. this point input changes from LVCMOS input SSTL2 input only will remain SSTL_2 input unless power cycle occurs. Perform PRECHARGE command. Wait least time, during this time NOPs DESELECT commands must given. Using command program Extended Mode Register enable normal drive reduced drive, through must where most significant bit). Wait least tMRD time, only NOPs DESELECT commands allowed. Using command program Mode Register operating parameters reset DLL. Note least clock cycles required between reset READ command. Wait least tMRD time, only NOPs DESELECT commands allowed. Issue PRECHARGE command. Wait least time, only NOPs DESELECT commands allowed. Issue AUTO REFRESH command (Note this moved prior step 13). Wait least tRFC time, only NOPs DESELECT commands allowed. Issue AUTO REFRESH command (Note this moved prior step 13). Wait least tRFC time, only NOPs DESELECT commands allowed. Although required Micron device, JEDEC requires command clear (set command issued same operating parameters should utilized step Wait least tMRD time, only NOPs DESELECT commands allowed. this point DRAM ready valid command. Note clock cycles required between step (DLL Reset) READ command.
Figure Initialization Flow Diagram
Step VDDQ Ramp
Apply VREF
must LVCMOS
Apply stable CLOCKs
Wait least 200us
Bring High with command
PRECHARGE
Assert DESELECT time
Configure Extended Mode Register
Assert DESELECT tMRD time
Configure Load Mode Register reset
Assert DESELECT tMRD time
PRECHARGE
Assert DESELECT time
Issue AUTO REFRESH command
Assert DESELECT commands tRFC
Issue AUTO REFRESH command
Assert DESELECT tRFC time
Optional command clear
Assert DESELECT tMRD time
DRAM ready valid command
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Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions shown Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data shown Figure Acknowledge Response from Receiver). device will always respond with acknowledge after recognition start condition slave address. both device write operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response from Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
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Table EEPROM Device Select Code
Most significant (b7) sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER CHIP ENABLE
Table EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE START, Device Select, START, Device Select, "0", Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
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Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced Vss; VDDSPD +2.3V +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +2.3V +3.6V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL
tBUF tHD:DAT tHD:STA tHIGH tLOW fSCL tSU:DAT tSU:STA
UNITS
NOTES
SU:STO tWRC
avoid spurious START STOP conditions, minimum delay placed between falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
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Table Serial Presence- Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"; notes appear page BYTE DESCRIPTION Number Bytes Used Micron Total Number Bytes Device Fundamental Memory Type Number Addresses Assembly Number Column Addresses Assembly Number Physical Ranks DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels ENTRY (VERSION) SDRAM MT4VDDT864A MT4VDDT1664A MT4VDDT3264A
SSTL 2.5V (-335) SDRAM Cycle Time, tCK, (CAS Latency (-262/-26A) 2.5) (See note 7.5ns (-265) 0.70ns (-335) SDRAM Access From Clock, tAC, (CAS 0.75ns (-262/-26A/-265) Latency 2.5) (See note Non-ECC Module Configuration Type 15.6µs 7.8µs/SELF Refresh Rate/Type SDRAM Device Width None Error-checking SDRAM Data Width clock Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency Unbuffered, Diff SDRAM Module Attributes Fast/Concurrent SDRAM Device Attributes: General 7.5ns (-335/-262/-26A) SDRAM Cycle Time, (CAS Latency 10ns (-265) (See note SDRAM Access From (CAS Latency (See note SDRAM Cycle Time, tCK, (CAS Latency 1.5) SDRAM Access from tAC, (CAS Latency 1.5) Minimum Precharge Time, (see note Minimum Active Active, tRRD Minimum RAS# CAS# Delay, tRCD (see note Minimum RAS# Pulse Width, tRAS (See note 0.70ns (-335) 0.75ns (-262/-26A/-265) 18ns (-335) 15ns (-262) 20ns (-26A/-265) 12ns (-335) 15ns (-262/-26A/-265) 18ns (-335) 15ns (-262) 20ns (-26A/-265) 42ns (-335) 45ns (-262/-26A/-265)
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Table Serial Presence- Detect Matrix (Continued)
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"; notes appear page BYTE DESCRIPTION Module Rank Density ENTRY (VERSION) MT4VDDT864A MT4VDDT1664A MT4VDDT3264A Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data Variable Data
64MB, 128MB, 256MB .8ns (-335) Address Command Setup Time, 1.0ns (-262/-26A/-265) (See note
0.8ns (-335) Address Command Hold Time, 1.0ns (-262/-26A/-265) (See note Data/Data Mask Input Setup Time, 0.45ns (-335) 0.5ns (-262/-26A/-265) Data/Data Mask Input Hold Time, 0.45ns (-335) 0.5ns (-262/-26A/-265) 36-40 Reserved 60ns (-335/-262) Minimum Active/Auto Refresh Time, 65ns (-26A/-265) 48-61 Minimum Auto Refresh Active/ Auto Refresh Command Period, tRFC Maximum Cycle Time, (MAX) 72ns (-335) 75ns (-262/-26A/-265)
12ns (-335) 13ns (-262/-26A/-265) 0.45ns (-335) Maximum DQS-DQ Skew Time, tDQSQ 0.5ns (-262/-26A/-265) 0.55ns (-335) Maximum Read Data Hold Skew tQHS 0.75ns (-262/-26A/-265) Factor, Standard Release -335 -262 -26A -265 MICRON
Reserved DIMM Height Reserved Revision Checksum Bytes 0-62
65-71 73-90 95-98 99-127
NOTE:
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Continued) Year Manufacture Week Manufacture Module Serial Number Manufacturer-Specific Data (RSVD)
Value -26A/-265 (0x70) optimum BIOS compatibility. Actual device spec value 7.5ns. value tRAS used -26A/-265 module calculated from tRC- tRP. Actual device spec. value 40ns. JEDEC specification allows fast slow slew rate values these bytes. worst-case (slow slew rate) value represented here. Systems requiring fast slew rate setup hold values supported, provided faster minimum slew rate met. value tRP, tRCD tRAP -335 modules indicated 18ns align with industry specifications; actual SDRAM device specification 15ns.
pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc.
64MB, 128MB, 256MB (x64, 184-PIN SDRAM UDIMM
Figure 184-Pin DIMM Dimensions
FRONT VIEW
5.256 (133.50) 5.244 (133.20) 0.125 (3.18)
0.079 (2.00) (4X)
1.256 (31.90) 1.244 (31.60)
0.098 (2.50) (2X) 0.091 (2.30) TYP. 0.035 (0.90)
0.700 (17.78) TYP.
0.091 (2.30) TYP. 0.050 (1.27) TYP. 0.040 (1.02) TYP.
0.250 (6.35) TYP.
0.054 (1.37) 0.046 (1.17)
4.750 (120.65) TYP.
BACK VIEW
Components This Side Module
1.95 (49.53) TYP. 2.55 (64.77) TYP.
0.150 (3.80) 0.394 (10.00) TYP. TYP.
NOTE:
dimensions inches (millimeters);
typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm Rev. 9/04 Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology,

SDRAM DIMM JEDEC standard 184-pin, unbuffered dual in-line memory

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