PIC18F2410/2510/4410/4510 Rev. Silicon Errata PIC18F2410/2510/441

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PIC18F2410/2510/4410/4510 Rev. Silicon Errata PIC18F2410/2510/441

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PIC18F2410/2510/4410/4510
PIC18F2410/2510/4410/4510 Rev. Silicon Errata
PIC18F2410/2510/4410/4510 Rev. parts have received conform functionally Device Data Sheet (DS39636), except anomalies described below. Data Sheet Clarification issues related PIC18F2410/2510/4410/4510 will reported separate Data Sheet errata. Please check Microchip site existing issues. issues listed here will addressed future revisions PIC18F2410/2510/4410/4510 silicon. following silicon errata apply only PIC18F2410/2510/4410/4510 devices with these Device/Revision IDs: Part Number PIC18F2410 PIC18F2510 PIC18F4410 PIC18F4510 Device 0001 0001 0000 0000 Revision 00001 00001 00001 00001
Module: MSSP
current implementation, I2CMaster mode operates follows: Baud Rate Generator Master mode slower than rates specified Table 16-3 Device Data Sheet. this revision silicon, values shown Table place those shown Table 16-3 Device Data Sheet. differences shown bold text. following formula place shown Register 16-4 (SSPCON1) Device Data Sheet description SSPM3:SSPM0 1000. SSPADD INT((FCY/FSCL) (FCY/1.111 MHz)) Date Codes that pertain this issue: engineering production devices.
Device (DEVID1 DEVID2) located addresses 3FFFFEh:3FFFFFh device's configuration space. They shown hexadecimal format "DEVID2 DEVID1".
TABLE
FOSC Note
I2CCLOCK RATE w/BRG
I2CFCY Value FSCL Rollovers BRG) kHz(1) 312.5 kHz(1) kHz(1) MHz(1)
interface does conform specification (which applies rates greater than kHz) details, used with care where higher rates required application.
2005 Microchip Technology Inc.
DS80208B-page
PIC18F2410/2510/4410/4510
Module: MSSP
When MSSP configured SPIMaster mode, cannot disabled setting TRISC<5> bit. always outputs content SSPBUF regardless state TRIS bit. Slave mode with Slave Select enabled, SSPM3:SSPM0 0010 (SSPCON1<3:0>), disabled placing logic high level (RA5). Work around None. Date Codes that pertain this issue: engineering production devices.
Module: MSSP
10-bit Addressing mode, when Repeated Start issued, followed high address byte write command (R/W issued. Work around There work arounds available: Single-Master Environment: single-master environment, user must issue Stop, then Start, followed write address high, then address followed data. Multi-Master Environment: multi-master environment, user must issue Repeated Start, send dummy write command different address, issue another Repeated Start then send write original address. This procedure will prevent loss bus. Date Codes that pertain this issue: engineering production devices.
Module: MSSP
After transfer initiated, SSPBUF register written before additional writes blocked. data transfer corrupted SSPBUF written during this time. WCOL time SSPBUF write occurs during transfer. Work around Avoid writing SSPBUF until data transfer complete, indicated setting SSPIF (PIR1<3>). Verify WCOL (SSPCON1<7>) clear after writing SSPBUF ensure potential transfer progress corrupted. Date Codes that pertain this issue: engineering production devices.
Module: MSSP
Receive mode should enabled (i.e., RCEN should set) only when system idle (i.e., when ACKEN, RCEN, PEN, RSEN equal zero). should possible RCEN when system idle, however, RCEN under this circumstance. Work around Wait system become idle before setting RCEN bit. This requires check following bits clear: ACKEN, RCEN, PEN, RSEN SEN. Date Codes that pertain this issue: engineering production devices.
DS80208B-page
2005 Microchip Technology Inc.
PIC18F2410/2510/4410/4510
Module: ECCP
When ECCP1 auto-shutdown feature configured automatic restart setting PRSEN (PWM1CON<7>), pulse terminates immediately shutdown event. addition, pulse restart within period shutdown condition expires. This result generation short pulses output(s). Work around Configure auto-shutdown software restart clearing PRSEN (PWM1CON<7>). re-enabled clearing ECCPASE (ECCP1AS<7>) after shutdown condition expires. Date Codes that pertain this issue: engineering production devices.
Module: ECCP
(E)CCP1 CCP2 configured mode, with Timer2 prescaler duty cycle period minus result output(s) remaining logic level. Clearing register select fastest period also result output(s) remaining logic output level. Work around ensure reliable waveform, verify that selected duty cycle does equal 10-bit period minus prior writing these locations, 1:16 Timer2 prescale. Also, verify register written 00h. other duty cycle period settings will function described Device Data Sheet. ECCP modules remain capable 10-bit accuracy. Date Codes that pertain this issue: engineering production devices.
Module: ECCP
When monitoring shutdown condition using test ECCPASE (ECCP1AS<7>), performing operation ECCPASE bit, device produce unexpected results. Work around Before performing test operation ECCPASE bit, copy ECCP1AS register working register perform operation there. avoiding these operations ECCPASE ECCP1AS register, module will operate normally. Example ECCPASE operations performed register.
Module: ECCP
ECCP1 configured auto-shutdown with Comparator corrupts duty cycle pulse. addition, does always synchronize pulse beginning period pulse occur time within period. Work around FLT0 auto-shutdown source. Applications which tolerate shutdown response time several TCYs comparator interrupt flag detect shutdown event disable clearing EECPASE (ECCP1AS<7>). Date Codes that pertain this issue: engineering production devices.
EXAMPLE
MOVF BTFSC ECCP1AS, WREG, ECCPASE SHUTDOWN_ROUTINE
Date Codes that pertain this issue: engineering production devices.
Module: ECCP
When shutdown state pin(s) configured tri-state outputs, device consume higher than expected current during shutdown event. Work around Configure output either high logic state during shutdown PSSAC1:PSSAC0 (ECCP1AS<3:2>) PSSBD1: PSSBD0 (ECCP1AS<1:0>) bits. Clearing autoshutdown event will return device normal current consumption levels. Date Codes that pertain this issue: engineering production devices.
Module: ECCP
auto-shutdown source, FLT0, inverse polarity from description Section 15.4.7 "Enhanced Auto-Shutdown" Device Data Sheet. logic high-voltage level FLT0 will generate shutdown ECCP1. Work around None. Date Codes that pertain this issue: engineering production devices.
2005 Microchip Technology Inc.
DS80208B-page
PIC18F2410/2510/4410/4510
Module: ECCP
pin(s) change state breakpoint encountered during emulation autoshutdown event occurs FLT0. This affects MPLAB® debugger 2000 4000 emulators. Work around During emulation, comparator autoshutdown. Applications which tolerate shutdown response time several TCYs external interrupt flag, INT0IF, detect shutdown event disable clearing ECCPASE (ECCP1AS<7>). Date Codes that pertain this issue: engineering production devices.
Module: ECCP
When shutdown condition occurs, output port made inactive duration event. After event that caused shutdown ends, ECCP module enables output right away instead waiting until beginning next cycle. Work around Disable auto-restart feature software, polling Timer2 Interrupt Flag (TMR2IF) wait until before clearing ECCPASE bit. Date Codes that pertain this issue: engineering production devices.
Module: ECCP
When switching direction Full-Bridge mode, modulated outputs will switch immediately instead waiting next cycle. This generate unexpected short pulses modulated outputs. Work around Disable duty cycle zero prior switching directions. Date Codes that pertain this issue: engineering production devices.
Module: ECCP
When operating either Timer1 Timer3 counter with prescale value other than operating ECCP Compare mode with Special Event Trigger (CCP1CON bits CCP1M3:CCP1M0 1011), Special Event Trigger Reset timer occurs soon there match between TMRxH:TMRxL CCPR1H:CCPR1L. This differs from PIC18F452, where Special Event Trigger Reset timer occurs next prescaler output pulse after match between TMRxH:TMRxL CCPR1H:CCPR1L. Work around achieve same timer Reset period PIC18F4510 family PIC18F452 family given clock source, value CCPR1H:CCPR1L. other words, CCPR1H:CCPR1L PIC18F452, achieve same Reset period PIC18F4510 family, CCPR1H:CCPR1L where prescale depending T1CKPS1:T1CKPS0 values. Date Codes that pertain this issue: engineering production devices.
DS80208B-page
2005 Microchip Technology Inc.
PIC18F2410/2510/4410/4510
Module:
offset greater than specified limit Table 25-24 Device Data Sheet. additional Parameter A06A updated conditions limits shown bold text Table Work around Three work arounds exist. Configure VREF+ VREFpins voltage references. This done setting VCFG<1:0> bits (ADCON1<5:4>). Perform conversion known voltage reference voltage adjust result software. Increase system clock speed adjust settings accordingly. Higher system clock frequencies decrease offset error.
TABLE
CONVERTER CHARACTERISTICS: PIC18F2X1X/4X1X (INDUSTRIAL, EXTENDED) PIC18LF2X1X/4X1X (INDUSTRIAL)
Characteristic Offset Error Offset Error <±1.5 <±3.5 Units Conditions VREF VREF+ VREFVREF
Param Symbol A06A EOFF EOFF
Date Codes that pertain this issue: engineering production devices.
Module:
module reset below minimum operating voltage device when configured BORV1:BORV0 updated Reset voltage specifications shown bold Table
Module: EUSART
When performing back-to-back transmission 9-bit mode (TX9D TXSTA register set), ongoing transmission's timing corrupted TX9D (for next transmission) written immediately following setting TXIF. This because write TXSTA register results reset Baud Rate Generator which will effect ongoing transmission. Work around Load TX9D just after TXIF set, either polling TXIF writing TX9D beginning Interrupt Service Routine, only write TX9D when transmission progress (TRMT Date Codes that pertain this issue: engineering production devices.
TABLE
Param D005
BROWN-OUT RESET VOLTAGE
Characteristic Unit
VBOR Brown-out Reset Voltage PIC18LF2410/2510/4410/4510 BORV1:BORV0 2.05
Work around next higher voltage setting ensure detected above 2.0V. Date Codes that pertain this issue: engineering production devices.
2005 Microchip Technology Inc.
DS80208B-page
PIC18F2410/2510/4410/4510
Module: EUSART
When performing back-to-back transmission 9-bit mode (TX9D TXSTA register set), second byte corrupted written into TXREG immediately after TMRT set. Work around Execute software delay, least one-half transmission's time, after TMRT prior writing subsequent bytes into TXREG. Date Codes that pertain this issue: engineering production devices.
Module: Timer1/Timer3
When Timer1 Timer3 External Clock Synchronized mode external clock period between TCY, interrupts will occasionally skipped. Work around Avoid using external clock with period frequency) between TCY. Date Codes that pertain this issue: engineering production devices.
Module: Timer1/Timer3
When Timer1 Timer3 configured external clock source CCPxCON register configured with 0x0B (Compare mode, trigger special event), timer reset Special Event Trigger. Work around Modify firmware reset Timer1/Timer3 registers upon detection compare match condition TMRxL TMRxH. Date Codes that pertain this issue: engineering production devices.
Module: Timer1/Timer3
When Timer1/Timer3 operating 16-bit mode prescale setting 1:1, write TMR1H/TMR3H Buffer registers lengthen duration period between increments timer period which TMR1H/TMR3H written. Work around work arounds available: Stop Timer1/ Timer3 before writing TMR1H/TMR3H registers; Write TMR1L/TMR3L immediately after writing TMR1H/TMR3H. Date Codes that pertain this issue: engineering production devices.
DS80208B-page
2005 Microchip Technology Inc.
PIC18F2410/2510/4410/4510
Module: Interrupts
interrupt occurs during two-cycle instruction that modifies STATUS, WREG register, unmodified value register will saved corresponding Fast Return (Shadow) register upon fast return from interrupt, unmodified value will restored STATUS, WREG register. example, high priority interrupt occurs during instruction, MOVFF TEMP, WREG, MOVFF instruction will completed WREG will loaded with value TEMP before branching ISR. However, previous value WREG will saved Fast Return register during branching. Upon return from interrupt with fast return, previous value WREG Fast Return register will written WREG. This results WREG containing value before execution MOVFF TEMP, WREG. Affected instructions are: MOVFF where WREG, STATUS; MOVSF where WREG, STATUS; MOVSS [Zs], [Zd] where destination WREG, STATUS. Work around Assembly Language Programming: twocycle instruction used modify WREG, STATUS register, RETFIE FAST instruction return from interrupt. Instead, save/restore WREG, STATUS software Example Device Data Sheet. Alternatively, case MOVFF, MOVF instruction write WREG instead. example, use: MOVF TEMP, MOVWF instead MOVFF TEMP, BSR. Language Programming: exact work around depends compiler use. Please refer your compiler documentation details. using Microchip MPLAB® Compiler, define both high priority interrupt handler functions "low priority" using pragma interruptlow directive. This directive instructs compiler RETFIE FAST instruction. proper high priority interrupt IPRx register, then interrupt treated high priority spite pragma interruptlow directive. following code snippet demonstrates work around using compiler: Date Codes that pertain this issue: engineering production devices. #pragma interruptlow MyLowISR void MyLowISR(void) Handle priority interrupts. Although MyHighISR high priority interrupt, interruptlow pragma that compiler will retfie FAST. #pragma interruptlow MyHighISR void MyHighISR(void) Handle high priority interrupts. #pragma code highVector=0x08 void HighVector (void) _asm goto MyHighISR _endasm #pragma code return default code section #pragma code lowVector=0x18 void LowVector (void) _asm goto MyLowISR _endasm #pragma code return default code section
2005 Microchip Technology Inc.
DS80208B-page
PIC18F2410/2510/4410/4510
REVISION HISTORY
Document (9/2004) First revision this document which includes silicon issues (ECCP), 7-11 (MSSP), (ECCP CCP), (A/D), 14-15 (Timer1/Timer3) (BOD/HLVD). Document (2/2005) Added Date Code information issues, updated text reordered issues clarity. Issues this revision are: (MSSP), 6-8, 10-12, 14-15 (ECCP), (ECCP CCP) (A/D), (BOD), 18-19 (EUSART), 20-22 (Timer1/Timer3) (Interrupts).
DS80208B-page
2005 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance WiperLock trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2005, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2005 Microchip Technology Inc.
DS80208B-page
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10/20/04
DS80208B-page
2005 Microchip Technology Inc.

PIC18F2410/2510/4410/4510 Rev. Silicon Errata PIC18F2410/2510/441

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