KS8995MA Integrated 5-Port 10/100 Managed Switch General Des
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KS8995MA
KS8995MA
Integrated 5-Port 10/100 Managed Switch
General Description
KS8995MA highly integrated Layer managed switch with optimized bill materials (BOM) cost port count, cost-sensitive 10/100Mbps switch systems. also provides extensive feature such tag/port-based VLAN, quality service (QoS) priority, management, counters, dual interfaces control/data interfaces effectively address both current emerging Fast Ethernet applications. KS8995MA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, high-speed non-blocking switch fabric, dedicated address lookup engine, on-chip frame buffer memory. units support 10BASE-T 100BASE-TX. addition, units support 100BASE-FX (ports
Features
Integrated switch with five MACs five Fast Ethernet transceivers fully compliant IEEE 802.3u standard Shared memory based switch fabric with fully nonblocking configuration 1.4Gbps high-performance memory bandwidth 10BASE-T, 100BASE-TX, 100BASE-FX modes ports Dual configuration: MII-Switch (MAC mode MII) MII-P5 (PHY mode MII) IEEE 802.1q tag-based VLAN VLANs, full-range VID) port, WAN/LAN separation inter-VLAN switch links VLAN tag/untag options, per-port basis Programmable rate limiting 0Mbps 100Mbps, ingress egress port, rate options high priority, per-port basis 32Kbps increments Flow control drop packet rate limiting (ingress port) Integrated counters fully compliant statistics gathering, counters port
Functional Diagram
Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X MII-P5 MDC, MDI/O MII-SW Control LED0[5:1] LED1[5:1] LED2[5:1]
10/100 T/Tx 10/100 T/Tx 10/100 T/Tx 10/100 T/Tx/Fx 10/100 T/Tx/Fx
10/100
Look-Up Engine
FIFO, Flow Control, VLAN Tagging, Priority
10/100 10/100 10/100 10/100
Queue Mgmnt
Buffer Mgmnt
Frame Buffers Counters EEPROM
Control Registers
KS8995MA
Micrel, Inc. 1849 Fortune Drive Jose, 95131 (408) 944-0800 (408) 474-1000 http://www.micrel.com
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(continued)
Features
Applications
Broadband gateway/firewall/VPN Integrated cable modem multi-port router Wireless access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Managed Media converter
Enable/Disable option huge frame size 1916 bytes frame IGMP v1/v2 snooping multicast packet filtering Special tagging mode send info ingress packet's port value slave (complete) MDIO (MII only) serial management interface control register configuration MAC-id based security lock option Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN.) read access forwarding table entries 802.1d Spanning Tree Protocol Port mirroring/monitoring/sniffing: ingress and/or egress traffic port Broadcast storm protection with control global per-port basis Optimization fiber-to-copper media conversion Full-chip hardware power-down support (register configuration saved) Per-port based software power-save (idle link detection, register configuration preserved) QoS/CoS packets prioritization supports: port, 802.1p DiffServ based 802.1p/q insertion removal per-port basis (egress) MDI/O interface support access control registers (not control registers) local loopback support On-chip 64Kbyte memory frame buffering (not shared with unicast address table) Wire-speed reception transmission Integrated look-up engine with dedicated addresses Full duplex IEEE 802.3x half-duplex back pressure flow control Comprehensive support 7-wire support legacy interface Automatic MDI/MDI-X crossover plug-and-play Disable automatic MDI/MDI-X option power: Core: 1.8V I/O: 2.5V 3.3V 0.18µm CMOS technology Commercial temperature range: +70°C Industrial temperature range: -40°C +85°C Available 128-pin PQFP package
Ordering Information
Part Number KS8995MA KSZ8995MA KS8995MAI Temp. Range +70°C +70°C -40°C +85°C Package 128-Pin PQFP 128-Pin PQFP 128-Pin PQFP Lead Finish Standard Lead-Free Standard
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Revision History
Revision Date 10/10/03 10/30/03 4/1/04 Summary Changes Created. Editorial changes electrical characteristics. Editorial changes input output electrical characteristics.
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Table Contents
System Level Applications Description Number Description Name Configuration Introduction Functional Overview: Physical Layer Transceiver 100BASE-TX Transmit 100BASE-TX Receive Clock Synthesizer Scrambler/De-scrambler (100BASE-TX only) 100BASE-FX Operation 100BASE-FX Signal Detection 100BASE-FX Fault 10BASE-T Transmit 10BASE-T Receive Power Management MDI/MDI-X Auto Crossover Auto-Negotiation Functional Overview: Switch Core Address Look-Up Learning Migration Aging Forwarding Switching Engine Operation Inter-Packet (IPG) Backoff Algorithm Late Collision Illegal Frames Flow Control Half-Duplex Back Pressure Broadcast Storm Protection Interface Operation Interface Operation Advanced Functionality Spanning Tree Support Special Tagging Mode IGMP Support Port Mirroring Support VLAN Support Rate Limit Support Configuration Interface Master Serial Configuration Slave Serial Configuration Management Interface (MIIM)
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Register Description Global Registers Register (0x00): Chip Register (0x01): Chip ID1/Start Switch Register (0x02): Global Control Register (0x03): Global Control Register (0x04): Global Control Register (0x05): Global Control Register (0x06): Global Control Register (0x07): Global Control Register (0x08): Global Control Register (0x09): Global Control Register (0x0A): Global Control Register (0x0B): Global Control Port Registers Register (0x10): Port Control Register (0x11): Port Control Register (0x12): Port Control Register (0x13): Port Control Register (0x14): Port Control Register (0x15): Port Control Register (0x16): Port Control Register (0x17): Port Control Register (0x18): Port Control Register (0x19): Port Control Register (0x1A): Port Control Register (0x1B): Port Control Register (0x1C): Port Control Register (0x1D): Port Control Register (0x1E): Port Status Register (0x1F): Port Control Advanced Control Registers Register (0x60): Priority Control Register Register (0x61): Priority Control Register Register (0x62): Priority Control Register Register (0x63): Priority Control Register Register (0x64): Priority Control Register Register (0x65): Priority Control Register Register (0x66): Priority Control Register Register (0x67): Priority Control Register Register (0x68): Address Register Register (0x69): Address Register Register (0x6A): Address Register Register (0x6B): Address Register Register (0x6C): Address Register Register (0X6D): Address Register Register (0x6E): Indirect Access Control Register (0x6F): Indirect Access Control June 2004
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Register (0x70): Indirect Data Register Register (0x71): Indirect Data Register Register (0x72): Indirect Data Register Register (0x73): Indirect Data Register Register (0x74): Indirect Data Register Register (0x75): Indirect Data Register Register (0x76): Indirect Data Register Register (0x77): Indirect Data Register Register (0x78): Indirect Data Register Register (0x79): Digital Testing Status Register (0x7A): Digital Testing Status Register (0x7B): Digital Testing Control Register (0x7C): Digital Testing Control Register (0x7D): Analog Testing Control Register (0x7E): Analog Testing Control Register (0x7F): Analog Testing Status Static Address VLAN Address Dynamic Address Counters MIIM Registers Register Control Register Status Register PHYID HIGH Register PHYID Register Advertisement Ability Register Link Partner Ability Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams Selection Isolation Transformers Qualified Magnetic Lists Package Information
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System Level Applications
10/100
Switch Controller On-Chip Frame Buffers
10/100 10/100 10/100 10/100 10/100
1-port 4-port
10/100 10/100 10/100 10/100
SPI/GPIO Ethernet Ethernet MII-SW
MII-P5
External port required.
Figure Broadband Gateway
10/100
Switch Controller On-Chip Frame Buffers
10/100 10/100 10/100 10/100 10/100
4-port
10/100 10/100 10/100 10/100
(xDSL, CM.)
SPI/GPIO
MII-SW MII-P5
Ethernet
Figure Integrated Broadband Router
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10/100
Switch Controller On-Chip Frame Buffers
10/100 10/100 10/100 10/100 10/100
5-port
10/100 10/100 10/100 10/100
Figure Standalone Switch
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Type(1) Function(2) Disable auto MDI/MDI-X. (default) normal operation. disable auto MDI/MDI-X ports. Analog ground. 1.8V analog VDD. Physical receive signal (differential). Physical receive signal (differential). Analog ground. Physical transmit signal (differential). Physical transmit signal (differential). 2.5V 3.3V analog VDD. Physical receive signal (differential). Physical receive signal (differential). Analog ground. Physical transmit signal (differential). Physical transmit signal (differential). 1.8V analog VDD. Analog ground. physical transmit output current. Pull-down with 3.01k resistor. 2.5V 3.3V analog VDD. Physical receive signal (differential). Physical receive signal (differential). Analog ground. Physical transmit signal (differential). Physical transmit signal (differential). 2.5V 3.3V analog VDD. Physical receive signal (differential). Physical receive signal (differential). Analog ground. Physical transmit signal (differential). Physical transmit signal (differential). Analog ground.
Description Number)
Number Name MDI-XDIS Port
GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect. Strap pull-up. Strap pull-down.
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Number Name VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5 FXSD4 GNDA VDDAR GNDA VDDAR GNDA MUX1 MUX2 Type(1) Port Function 1.8V analog VDD. Physical receive signal (differential). Physical receive signal (differential). Analog ground. Physical transmit signal (differential). Physical transmit signal (differential). 2.5V 3.3V analog VDD. Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. 1.8V analog VDD. Analog ground. 1.8V analog VDD. Analog ground. Factory test pins. MUX1 MUX2 should left unconnected normal operation. Mode Normal Operation PWRDN_N RESERVE GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD VDDIO PMRXC Full-chip power down. Active low. Reserved pin. connect. Digital ground. 1.8V digital core VDD. PHY[5] transmit enable. PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit error. PHY[5] transmit clock. mode MII. Digital ground. 3.3/2.5V digital digital circuitry. PHY[5] receive clock. mode MII. MUX1
MUX2
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect.
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Number Name PMRXDV PMRXD3 PMRXD2 PMRXD1 PMRXD0 Type(1) Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Port Function(2) PHY[5] receive data valid. PHY[5] receive Strap option: (default) enable flow control; disable flow control. PHY[5] receive Strap option: (default) disable back pressure; enable back pressure.
PHY[5] receive Strap option: (default) drop excessive collision packets; does drop excessive collision packets. PHY[5] receive Strap option: (default) disable aggressive back-off algorithm half-duplex mode; enable performance enhancement. PHY[5] receive error. Strap option: (default) 1522/1518 bytes; packet size 1536 bytes. PHY[5] carrier sense/force duplex mode. "Register port only. (default) force half-duplex auto-negotiation disabled fails. force full-duplex auto-negotiation disabled fails. PHY[5] collision detect/force flow control. "Register port only. (default) force flow control. normal operation. force flow control. Switch transmit enable. Switch transmit Switch transmit Switch transmit Switch transmit Switch transmit error. Switch transmit clock. Input mode, output mode MII. Digital ground. 3.3/2.5V digital digital circuitry Switch receive clock. Input mode, output mode MII. Switch receive data valid Switch receive Strap option: (default) Disable Switch full-duplex flow control; enable switch full-duplex flow control. Switch receive Strap option: (default) switch full duplex mode; switch half-duplex mode.
PMRXER PCRS
Ipd/O Ipd/O
PCOL
Ipd/O
SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2
Ipd/O Ipd/O Ipd/O
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect. Strap pull-up. Strap pull-down.
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Number Name SMRXD1 SMRXD0 Type(1) Ipd/O Ipd/O Port Function(2) Switch receive Strap option: (default) switch 100Mbps mode; switch 10Mbps mode. Switch receive Strap option: mode (default) mode mode "Register 11." Mode LEDX_2 LEDX_1 LEDX_0 SCOL SCRS SCONF1 Ipd/O Ipd/O Switch collision detect. Switch carrier sense. Dual configuration pin. (91, 87): SCONF0 GNDD VDDC LED5-2 LED5-1 LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Switch Disable, Otri Mode Mode Mode Disable Mode Mode Mode Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable Mode Mode Mode Lnk/Act Fulld/Col Speed
Mode 100Lnk/Act 10Lnk/Act Full duplex
Dual configuration pin. Digital ground. 1.8V digital core VDD. indicator Strap option: aging setup. "Aging" section. (default) aging enable; aging disable. indicator Strap option: (default) enable I/F. tristate output. "Pin SCONF1." indicator indicator indicator indicator indicator indicator
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect. Strap pull-up. Otri Output tristated. Strap pull-down. Fulld Full duplex.
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Number Name LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Otri Port Function indicator Digital ground. 3.3/2.5V digital digital I/O. indicator indicator indicator indicator indicator indicator Switch PHY[5] management data clock. Switch PHY[5] management data I/O. Features internal pull down define state when driven.
serial data output slave mode; used master mode. "Pin 113." Input clock 5MHz slave mode; output clock 81kHz master mode. "Pin 113." Serial data input slave mode; serial data input/output master mode. "Pin 113." Active low. data transfer start slave mode. When SPIS_N high, KS8995MA deselected SPIQ held high impedance state, high-to-low transition initiate data transfer; used master mode. Serial configuration pin. this case, EEPROM present, KS8995MA will start itself with PS[1:0] default register values Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Configuration Master Mode EEPROM Reserved Slave Mode Interface Factory Test Mode (BIST)
RST_N GNDD VDDC TESTEN
Serial configuration pin. "Pin 113." Reset KS8995MA. Active low. Digital ground. 1.8V digital core VDD. normal operation. Factory test pin.
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect.
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Number Name SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 Type(1) Port Function normal operation. Factory test pin. connect. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should ±100ppm. 25MHz crystal clock connection. 1.8V analog PLL. Analog ground. 1.8V analog VDD. Analog ground. Analog ground. normal operation. Factory test pin.
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect.
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Type(1)
Description Name)
Number Name FXSD4 FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0 Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Port Function Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. Analog ground. connect. Analog ground. Analog ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. Digital ground. physical transmit output current. Pull-down with 3.01k resistor. indicator indicator indicator indicator indicator indicator indicator
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect.
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Number Name LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDIO MDI-XDIS MUX1 MUX2 Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Port Function(2) indicator indicator indicator indicator indicator indicator indicator Strap option: (default) enable tristate output. "Pin SCONF1." indicator Strap option: aging setup. "Aging" section. (default) aging enable; aging disable. Switch PHY[5] management data clock. Switch PHY[5] management data I/O. Disable auto MDI/MDI-X. Factory test pins. MUX1 MUX2 should left unconnected normal operation. Mode Normal Operation PCOL Ipd/O MUX1
MUX2
PHY[5] collision detect/force flow control. "Register 18." port only. (default) force flow control. force flow control. PHY[5] carrier sense/force duplex mode. "Register 28." port only. (default) force half-duplex auto-negotiation disabled fails. force full-duplex auto-negotiation disabled fails. PHY[5] receive clock. mode MII. PHY[5] receive Strap option: (default) disable aggressive back-off algorithm half-duplex mode; enable performance enhancement. PHY[5] receive Strap option: (default) drop excessive collision packets; does drop excessive collision packets. PHY[5] receive Strap option: (default) disable back pressure; enable back pressure. PHY[5] receive Strap option: (default) enable flow control; disable flow control. PHY[5] receive data valid. PHY[5] receive error. Strap option: (default) 1522/1518 bytes; packet size 1536 bytes.
PCRS
Ipd/O
PMRXC PMRXD0
Ipd/O
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXER
Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect. Strap pull-up. Strap pull-down.
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Number Name PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER Type(1) Port Function PHY[5] transmit clock. mode MII. PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit enable. PHY[5] transmit error. Serial configuration pin. "Pin 113." Serial configuration pin. EEPROM present, KS8995MA will start itself with chip default (00). Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 PWRDN_N RESERVE RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCOL SCONF0 Ipd/O Serial Configuration Master Mode EEPROM Reserved Slave Mode Interface Factory Test Mode (BIST)
Full-chip power down. Active low. Reserved pin. connect. Reset KS8995MA. Active low. Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). Physical receive signal (differential). normal operation. Factory test pin. Switch collision detect. Dual configuration pin.
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. connect.
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Number Name SCONF1 Type(1) Port Function(2) Dual configuration pin. (91, 87): SCRS SMRXC SMRXD0 Ipd/O Ipd/O Switch carrier sense. Switch Disable, Otri Mode Mode Mode Disable Mode Mode Mode Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable Mode Mode Mode
Switch receive clock. Input mode, output mode MII. Switch receive strap option: mode (default) mode mode "Register 11." Mode LEDX_2 LEDX_1 LEDX_0 Lnk/Act Fulld/Col Speed Mode 100Lnk/Act 10Lnk/Act Full duplex
SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER
Ipd/O Ipd/O Ipd/O Ipd/O
Switch receive Strap option: (default) switch 100Mbps mode; switch 10Mbps mode. Switch receive Strap option: (default) switch full-duplex mode; switch half-duplex mode. Switch receive Strap option: (default) disable switch full-duplex flow control; enable switch full-duplex flow control. Switch receive data valid. Switch transmit clock. Input mode, output mode MII. Switch transmit Switch transmit Switch transmit Switch transmit Switch transmit enable. Switch transmit error.
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. Otri Output tristated. connect. Strap pull-up. Strap pull-down. Fulld Full duplex.
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Number Name SPIC/SCL SPID/SDA SPIQ SPIS_N Type(1) Otri Port Function
Input clock 5MHz slave mode; Output clock 81kHz master mode. "Pin 113." Serial data input slave mode; Serial data input/output master mode. "Pin 113." serial data output slave mode; used master mode. "Pin 113." Active low. data transfer start slave mode. When SPIS_N high, KS8995MA deselected SPIQ held high impedance state, high-to-low transition initiate data transfer; used master mode. connect normal operation. Factory test pin. connect normal operation. Factory test pin.
TEST2 TESTEN TXM1 TXM2 TXM3 TXM4 TXM5 TXP1 TXP2 TXP3 TXP4 TXP5 VDDAP VDDAR VDDAR VDDAR VDDAR VDDAR VDDAR VDDAT VDDAT VDDAT VDDAT VDDC
Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). Physical transmit signal (differential). 1.8V analog PLL. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 1.8V analog VDD. 2.5V 3.3V analog VDD. 2.5V 3.3V analog VDD. 2.5V 3.3V analog VDD. 2.5V 3.3V analog VDD. 1.8V digital core VDD.
Note: Power supply. Input. Output. Bidirectional. Ground. Input internal pull-up. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Ipu/O Input internal pull-up during reset, output otherwise. Otri Output tristated. connect.
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Number
Note: Power supply. Input. Output.
Name VDDC VDDC VDDIO VDDIO VDDIO Type(1) Port Function 1.8V digital core VDD. 1.8V digital core VDD. 3.3/2.5V digital digital circuitry. 3.3/2.5V digital digital circuitry. 3.3/2.5V digital digital circuitry. 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should ±100ppm. 25MHz crystal clock connection.
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LED2-0 LED1-2 LED1-1 LED1-0 MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2
KS8995MA
Configuration
128-Pin PQFP (PQ)
MDIXDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD5
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4
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Introduction
KS8995MA contains five 10/100 physical layer transceivers five media access control (MAC) units with integrated Layer managed switch. device runs three modes. first mode five-port integrated switch. second five-port switch with fifth port decoupled from physical port. this mode, access fifth provided through media independent interface (MII) This useful implementing integrated broadband router. third mode uses dual feature recover fifth PHY. This allows additional broadband gateway configuration, where fifth accessed through MII-P5 port. KS8995MA flexibility reside managed unmanaged design. managed design, host processor complete control KS8995MA bus, partial control MDC/MDIO interface. unmanaged design achieved through strapping EEPROM programming system reset time. media side, KS8995MA supports IEEE 802.3 10BASE-T, 100BASE-TX ports, 100BASE-FX ports KS8995MA used separate media converters. Physical signal transmission reception enhanced through patented analog circuitry that makes design more efficient allows lower power consumption smaller chip size. major enhancements from KS8995E KS8995MA support host processor management, dual interface, well port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support rate limiting functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding transmission. circuit starts with parallel-to-serial conversion, which converts data from into 125MHz serial stream. data control stream then converted into 4B/5B coding followed scrambler. serialized data further converted from NRZ-to-NRZI format, then transmitted MLT3 current output. output current external 3.01k resistor transformer ratio. typical rise/fall time complies with ANSI TP-PMD standard regarding amplitude balance, overshoot, timing jitter. wave-shaped 10BASE-T output also incorporated into 100BASE-TX transmitter.
100BASE-TX Receive
100BASE-TX receiver function performs adaptive equalization, restoration, MLT3-to-NRZI conversion, data clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, serial-to-parallel conversion. receiving side starts with equalization filter compensate inter-symbol interference (ISI) over twisted pair cable. Since amplitude loss phase distortion function length cable, equalizer adjust characteristics optimize performance. this design, variable equalizer will make initial estimation based comparisons incoming signal strength against some known cable characteristics, then tunes itself optimization. This ongoing process self-adjust against environmental changes such temperature variations. equalized signal then goes through restoration data conversion block. restoration circuit used compensate effect baseline wander improve dynamic range. differential data conversion circuit converts MLT3 format back NRZI. slicing threshold also adaptive. clock recovery circuit extracts 125MHz clock from edges NRZI signal. This recovered clock then used convert NRZI signal into format. signal then sent through de-scrambler followed 4B/5B decoder. Finally, serial data converted format provided input data MAC.
Clock Synthesizer
KS8995MA generates 125MHz, 42MHz, 25MHz, 10MHz clocks system timing. Internal clocks generated from external 25MHz crystal oscillator.
Scrambler/De-scrambler (100BASE-TX only)
purpose scrambler spread power spectrum signal order reduce baseline wander. data scrambled through 11-bit wide linear feedback shift register (LFSR). This generate 2047-bit nonrepetitive sequence. receiver will then de-scramble incoming data stream with same sequence transmitter.
100BASE-FX Operation
100BASE-FX operation very similar 100BASE-TX operation except that scrambler/de-scrambler MLT3 encoder/ decoder bypassed transmission reception. this mode auto-negotiation feature bypassed since there standard that supports fiber auto-negotiation.
100BASE-FX Signal Detection
physical port runs 100BASE-FX mode FXSDx >0.6V ports only. This signal internally referenced 1.25V. fiber module interface should voltage divider such that FXSDx above this 1.25V reference, indicating signal
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detect, FXSDx below 1.25V reference indicate signal. When FXSDx below 0.6V then 100BASE-FX mode disabled. Since there auto-negotiation 100BASE-FX mode, ports must forced either full half-duplex. Note that strap-in options exist duplex mode port port
100BASE-FX Fault
fault occurs when signal detection logically false from receive fiber module. When this occurs, transmission side signals other link sending followed zero idle period between frames. fault disabled through register settings.
10BASE-T Transmit
output 10BASE-T driver incorporated into 100BASE-T driver allow transmission with same magnetics. They internally wave-shaped pre-emphasized into outputs with typical 2.3V amplitude. harmonic contents least 27dB below fundamental when driven all-ones Manchester-encoded signal.
10BASE-T Receive
receive side, input buffer level detecting squelch circuits employed. differential input receiver circuit perform decoding function. Manchester-encoded data stream separated into clock signal data. squelch circuit rejects signals with levels less than 400mV with short pulsewidths order prevent noises input from falsely triggering decoder. When input exceeds squelch limit, locks onto incoming signal KS8995MA decodes data frame. receiver clock maintained active during idle periods between data reception.
Power Management
KS8995MA features port power down mode. save power user power down ports that setting port control registers control registers. addition, also supports full chip power down mode. When activated, entire chip will shutdown.
MDI/MDI-X Auto Crossover
KS8995MA supports MDI/MDI-X auto crossover. This facilitates either straight connection CAT-5 cable crossover CAT-5 cable. auto-sense function will detect remote transmit receive pairs, correctly assign transmit receive pairs from Micrel device. This highly useful when users unaware cable types also save additional uplink configuration connection. auto crossover feature disabled through port control registers.
Auto-Negotiation
KS8995MA conforms auto-negotiation protocol described 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners select best common mode operation. auto-negotiation link partners advertise capabilities across link each other. auto-negotiation supported link partner KS8995MA forced bypass auto-negotiation, then mode observing signal receiver. This known parallel mode because while transmitter sending auto-negotiation advertisements, receiver listening advertisements fixed signal protocol. flow link setup shown Figure
Start Auto Negotiation
Force Link Setting
Parallel Operation
Bypass Auto-Negotiation Link Mode
Attempt Auto-Negotiation
Listen 100BASE-TX Idles
Listen 10BASE-T Link Pulses
Join Flow
Link Mode
Link Mode
Figure Auto-Negotiation June 2004
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Functional Overview: Switch Core
Address Look-Up
internal look-up table stores addresses their associated information. contains unicast address table plus switching information. KS8995MA guaranteed learn addresses distinguishes itself from hash-based lookup table, which depending operating environment probabilities, guarantee absolute number addresses learn.
Learning
internal look-up engine updates table with entry following conditions met: received packet's source address (SA) does exist look-up table. received packet good; packet receiving errors legal length. look-up engine inserts qualified into table, along with port number time stamp. table full, last entry table deleted first make room entry.
Migration
internal look-up engine also monitors whether station moved. this occurs, updates table accordingly. Migration happens when following conditions met: received packet's table associated source port information different. received packet good; packet receiving errors legal length. look-up engine will update existing record table with source port information.
Aging
look-up engine will update time stamp information record whenever corresponding appears. time stamp used aging process. record updated period time, look-up engine will remove record from table. look-up engine constantly performs aging process will continuously remove aging records. aging period seconds. This feature enabled disabled through Register external pull-up pull-down resistors LED[5][2]. "Register section.
Forwarding
KS8995MA will forward packets using algorithm that depicted following flowcharts. Figure shows stage forwarding algorithm where search engine looks VLAN static table, dynamic table destination address, comes with "port forward (PTF1). PTF1 then further modified spanning tree, IGMP snooping, port mirroring, port VLAN processes come with "port forward (PTF2), shown Figure This where packet will sent. KS8995MA will forward following packets: Error packets. These include framing errors, errors, alignment errors, illegal size packet errors. 802.3x pause frames. KS8995MA will intercept these packets perform appropriate actions. "Local" packets. Based destination address (DA) look-up. destination port from look-up table matches port where packet from, packet defined "local".
Switching Engine
KS8995MA features high-performance switching engine move data from MAC's, packet buffers. operates store forward mode, while efficient switching mechanism reduces overall latency. KS8995MA 64kB internal frame buffer. This resource shared between five ports. buffer sharing mode programmed through Register "Register mode, ports allowed free buffers buffer pool. second mode, each port only allowed total buffer pool. There total buffers available. Each buffer sized 128B.
Media Access Controller (MAC) Operation
KS8995MA strictly abides IEEE 802.3 standards maximize compatibility. Inter Packet (IPG) frame successfully transmitted, 96-bit time measured between consecutive MTXEN. current packet experiencing collision, 96-bit time measured from MCRS next MTXEN. Backoff Algorithm KS8995MA implements IEEE 802.3 binary exponential back-off algorithm, optional "aggressive mode" back off. After collisions, packet will optionally dropped depending chip configuration Register "Register
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Start
PTF1=NULL
VLAN VALID?
-Search VLAN table. -Ingress VLAN filtering -Discard NPVID check
Search complete. PTF1 from static table.
FOUND
Search Static Table
Search based DA+FID
FOUND
Search complete. PTF1 from dynamic table.
FOUND
Dynamic Table Search
This search based DA+FID
FOUND
Search complete. PTF1 from VLAN table.
PTF1
Figure Look-Up Flowchart-Stage
PTF1
Spanning Tree Process
-Check receiving port's receive enable -Check destination port's transmit enable -Check whether packets special (BPDU specified)
IGMP Process
-Applied -MAC#5 reserved microprocessor -IGMP will forwarded port
Port Mirror Process
Mirror Mirror Mirror Mirror
Port VLAN Membership Check
PTF2
Figure Resolution Flowchart-Stage
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Late Collision transmit packet experiences collisions after 512-bit times transmission, packet dropped. Illegal Frames KS8995MA discards frames less than bytes programmed accept frames 1536 bytes Register special applications, KS8995MA also programmed accept frames 1916 bytes Register Since KS8995MA supports VLAN tags, maximum size adjusted when these tags present. Flow Control KS8995MA supports standard 802.3x flow control frames both transmit receive sides. receive side, KS8995MA receives pause control frame, KS8995MA will transmit next normal frame until timer, specified pause control frame, expires. another pause frame received before current timer expires, timer will updated with value given second pause frame. During this period flow control, only flow controlled packets from KS8995MA transmitted. transmit side, KS8995MA intelligent efficient ways determine when invoke flow control. flow control based availability system resources, including available buffers, available transmit queues, available receive queues. KS8995MA flow controls port that just received packet destination port resource busy. KS8995MA issues flow control frame (XOFF), containing maximum pause time defined IEEE standard 802.3x. Once resource freed KS8995MA sends other flow control frame (XON) with zero pause time turn flow control (turn transmission port). hysteresis feature also provided prevent over-activation deactivation flow control mechanism. KS8995MA flow controls ports receive queue becomes full. Half-Duplex Back Pressure KS8995MA also provides half-duplex back pressure option (note: this IEEE 802.3 standards). activation deactivation conditions same ones given full-duplex mode. back pressure required, KS8995MA sends preambles defer other station's transmission (carrier sense deference). avoid jabber excessive deference defined IEEE 802.3 standard, after certain period time, KS8995MA discontinues carrier sense raises quickly after drops packets inhibit other transmissions. This short silent time carrier sense) prevent other stations from sending packets keeps other stations carrier sense deferred state. port packets send during back pressure situation, carrier-sense-type back pressure interrupted those packets transmitted instead. there more packets send, carrier-sense-type back pressure becomes active again until switch resources free. collision occurs, binary exponential backoff algorithm skipped carrier sense generated immediately, reducing chance further colliding maintaining carrier sense prevent reception packets. ensure packet loss 10BASE-T 100BASE-TX half-duplex modes, user must enable following: Aggressive backoff (Register excessive collision drop (Register Back pressure (Register These bits default because this IEEE standard. Broadcast Storm Protection KS8995MA intelligent option protect switch system from receiving many broadcast packets. Broadcast packets normally forwarded ports except source port thus many switch resources (bandwidth available space transmit queues). KS8995MA option include "multicast packets" storm control. broadcast storm rate parameters programmed globally enabled disabled port basis. rate based 50ms interval 100BT 500ms interval 10BT. beginning each interval, counter cleared zero rate limit mechanism starts count number bytes during interval. rate definition described Registers default setting Registers 0x4A decimal). This equal rate calculated follows: 148,800 frames/sec 50ms/interval frames/interval (approx.) 0x4A
Interface Operation
media independent interface (MII) specified IEEE 802.3 committee provides common interface between physical layer layer devices. KS8995MA provides such interfaces. MII-P5 interface used connect fifth PHY, whereas MII-SW interface used connect fifth MAC. Each these interfaces contains distinct groups signals, transmission other receiving. Table describes signals used MII-P5 interface.
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Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDIO Description Transmit enable Transmit error Transmit data Transmit data Transmit data Transmit data Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data Receive data Receive data Receive data Receive clock Management data clock Management data KS8995MA Signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDIO
Table Signals (PHY Mode)
Mode Connection External MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995MA Signal SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Description Transmit enable Transmit error Transmit data Transmit data Transmit data Transmit data Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data Receive data Receive data Receive data Receive clock
Mode Connection External MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995MA Signal SMRXDV used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC
Table Signals
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MII-P5 interface operates mode only, while MII-SW interface operates either mode mode. These interfaces nibble-wide data interfaces therefore network rate (not encoded). Additional signals transmit side indicate when data valid when error occurs during transmission. Likewise, receive side indicators that convey when data valid without physical layer errors. half-duplex operation there signal that indicates collision occurred during transmission. Note that signal MRXER provided MII-SW interface mode operation signal MTXER provided MII-SW interface mode operation. Normally MRXER would indicate receive error coming from physical layer device. MTXER would indicate transmit error from device. These signals appropriate this configuration. mode operation, device interfacing with KS8995MA MRXER pin, should tied low. mode operation, device interfacing with KS8995MA MTXER pin, should tied low.
Interface Operation
serial network interface (SNI) compatible with some controllers used network layer protocol processing. This interface directly connected these types devices. signals divided into groups, transmission other reception. signals involved described Table
Signal TXEN Description Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock KS8995MA Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC
Table Signals This interface bit-wide data interface therefore runs network rate (not encoded). additional signal transmit side indicates when data valid. Likewise, receive side also indicator that shows data receiving valid. half-duplex operation, there signal that indicates collision occurred during transmission.
Advanced Functionality
Spanning Tree Support
Port designated port spanning tree support. other ports (port port configured five spanning tree states "transmit enable," "receive enable," "learning disable" register settings Registers ports respectively. following description shows port setting software actions taken each five spanning tree states. Disable state: port should forward receive packets. Learning disabled. Port setting: "transmit enable receive enable learning disable Software action: processor should send packets port. switch still send specific packets processor (packets that match some entries static table with "overriding bit" set) processor should discard those packets. Note: processor connected port interface. Address learning disabled port this state. Blocking state: only packets processor forwarded. Learning disabled. Port setting: "transmit enable receive enable learning disable Software action: processor should send packets port(s) this state. processor should program "Static table" with entries that needs receive (e.g., BPDU packets). "overriding" should also that switch will forward those specific packets processor. Address learning disabled port this state. Listening state: only packets from processor forwarded. Learning disabled. Port setting: "transmit enable receive enable learning disable Software action: processor should program static table with entries that needs receive (e.g. BPDU packets). "overriding" should that switch will forward those specific packets processor. processor send packets port(s) this state, "Special Tagging Mode" section details. Address learning disabled port this state.
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Learning state: only packets from processor forwarded. Learning enabled. Port setting: "transmit enable receive enable learning disable Software action: processor should program static table with entries that needs receive (e.g., BPDU packets). "overriding" should that switch will forward those specific packets processor. processor send packets port(s) this state, "Special Tagging Mode" section details. Address learning enabled port this state. Forwarding state: packets forwarded received normally. Learning enabled. Port setting: "transmit enable receive enable learning disable Software action: processor should program static table with entries that needs receive (e.g., BPDU packets). "overriding" should that switch will forward those specific packets processor. processor send packets port(s) this state, "Special Tagging Mode" section details. Address learning enabled port this state.
Special Tagging Mode
special tagging mode designed spanning tree protocol IGMP snooping flexible other applications. special tagging mode, similar 802.1q, requires software change network drivers insert/modify/strip/interpret special tag. This mode enabled setting both Register Register
802.1q Format TPID (tag protocol identifier, 0x8100) Special Format STPID (special identifier, 0x8100) 0x810 "port mask")
Table Special Tagging Mode Format STPID will only seen used port interface, which should connected processor. Packets from processor switch should tagged with STPID port mask defined below: "0001" packet port only "0010" packet port only "0100" packet port only "1000" packet port only "0011" packet broadcast port port "1111" packet broadcast port "0000" normal tag, will KS8995MA internal look-up result. Normal packets should this setting. packets from processors have tag, KS8995MA will treat them normal packets internal look-up will performed. KS8995MA uses non-zero "port mask" bypass look-up result override port setting, regardless port states (blocking, disable, listening, learning). Table shows egress rules when dealing with STPID.
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Port "Tag Insertion" Port "Tag Removal"
Ingress Field (0x810+ port mask)
Egress Action Field Modify field 0x8100. Recalculate CRC. change null VID. Replace with ingress (port port null VID.
(0x810+ port mask)
(STPID TCI) will removed. Padding bytes necessary. Recalculate CRC. Modify field 0x8100. Recalculate CRC. change null VID. Replace with ingress (port port null VID. Modify field 0x8100. Recalculate CRC. change null VID. Replace with ingress (port port null VID.
(0x810+ port mask)
(0x810+ port mask)
tagged
Don't care
Don't care
Determined dynamic address table.
Table STPID Egress Rules (Processor Switch Port packets from regular ports (port port port port mask used tell processor which port packet received defined "0001" from port "0010" from port "0100" from port "1000" from port values other than previous four defined should received this direction special mode. Table shows egress rule this direction.
Ingress Packets Tagged with 0x8100 Egress Action Field Modify TPID 0x810 "port mask," which indicates source port. change TCI, null. Replace null with ingress port VID. Recalculate CRC.
tagged
Insert TPID 0x810 "port mask," which indicates source port. Insert with ingress port VID. Recalculate CRC.
Table STPID Egress Rules (Switch Processor)
IGMP Support
There parts involved support IGMP Layer first part "IGMP" snooping. switch will trap IGMP packets forward them only processor port. IGMP packets identified packets (either Ethernet packets IEEE 802.3 SNAP packets) version protocol number 0x2. second part "multicast address insertion" static table. Once multicast address programmed static table, multicast session will trimmed subscribed ports, instead broadcasting ports. enable this feature, Register Also "special mode" needs enabled, that processor knows which port IGMP packet received Enable "special mode" setting both Register Register
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Port Mirroring Support
KS8995MA supports "port mirror" comprehensively "Receive Only" mirror port. packets received port will mirrored sniffer port. example, port programmed sniff," port programmed "sniffer port." packet, received port destined port after internal look-up. KS8995MA will forward packet both port port KS8995MA optionally forward even "bad" received packets port "Transmit Only" mirror port. packets transmitted port will mirrored sniffer port. example, port programmed sniff," port programmed "sniffer port." packet, received ports, destined port after internal look-up. KS8995MA will forward packet both ports "Receive Transmit" mirror ports. packets received port transmitted port will mirrored sniffer port. turn "AND" feature, Register example, port programmed sniff," port programmed "transmit sniff," port programmed "sniffer port." packet, received port destined port after internal look-up. KS8995MA will forward packet port only, since does meet "AND" condition. packet, received port destined port after internal look-up. KS8995MA will forward packet both port port Multiple ports selected sniffed" sniffed." port selected "sniffer port." these port features selected through Register
VLAN Support
KS8995MA supports active VLANs 4096 possible VLANs specified IEEE 802.1q. KS8995MA provides 16-entry VLAN table, which converts bits) bits) address look-up. non-tagged null-VID-tagged packet received, ingress port used look-up. VLAN mode, look-up process starts with VLAN table look-up determine whether valid. valid, packet will dropped address will learned. valid, retrieved further look-up. FID+DA used determine destination port. FID+SA used learning purposes.
found Static table DA+FID found Dynamic table Don't care Don't care
Flag? Don't care Don't care
Match? Don't care Don't care Don't care
Action Broadcast membership ports defined VLAN table [20:16]. Send destination port defined dynamic table [54:52]. Send destination port(s) defined static table [52:48]. Broadcast membership ports defined VLAN table [20:16]. Send destination port defined dynamic table [54:52]. Send destination port(s) defined static table [52:48].
Table FID+DA Look-Up VLAN Mode
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SA+FID found Dynamic table
Action SA+FID will learned into dynamic table. Time stamp will updated.
Table FID+SA Look-Up VLAN Mode Advanced VLAN features also supported KS8995MA, such "VLAN ingress filtering" "discard PVID" defined Register These features controlled port basis.
Rate Limit Support
KS8995MA supports hardware rate limiting "receive" "transmit" independently port basis. also supports rate limiting priority non-priority environment. rate limit starts from 0Kbps goes line rate steps 32Kbps. KS8995MA uses second interval. beginning each interval, counter cleared zero, rate limit mechanism starts count number bytes during this interval. receive, number bytes exceeds programmed limit, switch will stop receiving packets port until "one second" interval expires. There option provided flow control prevent packet loss. rate limit programmed greater than equal 128Kbps byte counter bytes below limit, flow control will triggered. rate limit programmed lower than 128Kbps byte counter bytes below limit, flow control will triggered. transmit, number bytes exceeds programmed limit, switch will stop transmitting packets port until "one second" interval expires. priority enabled, KS8995MA support different rate controls both high priority priority packets. This programmed through Registers 21-27.
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Configuration Interface
KS8995MA function managed switch unmanaged switch. EEPROM micro-controller exists, KS8995MA will operate from default setting. Some default settings configured strap options indicated table below.
Name MDI-XDIS PU/PD(1) Description(1) Disable auto MDI/MDI-X. (default) normal operation. disable auto MDI/MDI-X ports. Factory test pins. MUX1 MUX2 should left unconnected normal operation. Mode Normal Operation PMRXD3 PMRXD2 PMRXD1 PMRXD0 PMRXER PCRS Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O MUX1 MUX2
MUX1 MUX2
PHY[5] receive Strap option: (default) enable flow control; disable flow control. PHY[5] receive Strap option: (default) disable back pressure; enable back pressure. PHY[5] receive Strap option: (default) drop excessive collision packets; does drop excessive collision packets. PHY[5] receive Strap option: (default) disable aggressive back-off algorithm half-duplex mode; enable performance enhancement. PHY[5] receive error. Strap option: (default) 1522/1518 bytes; packet size 1536 bytes. PHY[5] carrier sense/force duplex mode. "Register port only. (default) force half-duplex auto-negotiation disabled fails. force full-duplex auto-negotiation disabled fails. PHY[5] collision detect/force flow control. "Register port only. (default) force flow control. force flow control. Switch receive Strap option: (default) disable switch full-duplex flow control; enable switch full-duplex flow control. Switch receive Strap option: (default) switch full-duplex mode; switch half-duplex mode. Switch receive Strap option: (default) switch 100Mbps mode; switch 10Mbps mode. Switch receive Strap option: mode (default) mode mode "Register 11." Mode LEDX_2 LEDX_1 LEDX_0 Lnk/Act Fulld/Col Speed Mode 100Lnk/Act 10Lnk/Act Fulld
PCOL SMRXD3 SMRXD2 SMRXD1 SMRXD0
Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O
Note: connect. Input internal pull-down. Ipd/O Input internal pull-down during reset, output otherwise. Fulld Full duplex.
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Name SCONF1 PU/PD(1) Description1) Dual configuration pin. Pins SCONF0 LED5-2 LED5-1 Ipu/O Ipu/O Switch Disable, Otri Mode Mode Mode Disable Mode Mode Mode Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable Mode Mode Mode
Dual configuration pin. indicator Strap option: Aging setup. "Aging" section (default) aging enable; aging disable. indicator Strap option: (default): enable I/F. tristate output. "Pin SCONF1." Serial configuration pin. this case, EEPROM present, KS8995MA will start itself with PS[1:0] default register values Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Serial Configuration Master Mode EEPROM Reserved Slave Mode Interface Factory Test Mode (BIST)
TEST2
Serial configuration pin. "Pin 113." normal operation. Factory test pin.
Note: connect. Input internal pull-down. Ipu/O Input internal pull-up during reset, output otherwise. Otri Output tristated.
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Master Serial Configuration 2-wire EEPROM exists, KS8995MA perform more advanced features like broadcast storm protection rate control. EEPROM should have entire valid configuration data from Register Register defined "Memory Map," except status registers. After reset, KS8995MA will start read registers sequentially from EEPROM. configuration access time (tprgm) less than 15ms shown Figure
RST_N
tprgm<15
Figure KS8995MA EEPROM Configuration Timing Diagram
configure KS8995MA with pre-configured EEPROM following steps: board level, connect KS8995MA EEPROM. Connect KS8995MA EEPROM. input signals PS[1:0] (pins 114, respectively) "00." This puts KS8995MA serial configuration into master mode. sure board-level reset signal connected KS8995MA reset signal (RST_N). Program contents EEPROM before placing board with desired configuration data. Note that first byte EEPROM must "95" loading occur properly. this value correct, other data will ignored. Place EEPROM board power board. Assert active-low board level reset RST_N KS8995MA. After reset de-asserted, KS8995MA will begin reading configuration data from EEPROM. configuration access time (tprgm) less than 15ms. Note: proper operation, make sure that (PWRDN_N) asserted during reset operation.
Slave Serial Configuration KS8995MA also slave device. Through SPI, entire feature enabled, including "VLAN," "IGMP snooping," "MIB counters," etc. external master device access register from Register Register randomly. system should configure desired settings before enabling switch KS8995MA. enable switch, write Register standard commands supported (00000011 "READ DATA," 00000010 "WRITE DATA"). speed configuration time, KS8995MA also supports multiple reads writes. After byte written read from KS8995MA, internal address counter automatically increments Slave Select Signal (SPIS_N) continues driven low. SPIS_N kept after first byte read, next byte next address will shifted SPIQ. SPIS_N kept after first byte written, bits Master Slave Input (SPID) line will written next address. Asserting SPIS_N high terminates read write operation. This means that SPIS_N signal must asserted high then again before issuing another command address. address counter wraps back zero once reaches highest address. Therefore entire register written read from issuing single command address. KS8995MA able support 5MHz bus. high performance master recommended prevent internal counter overflow.
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KS8995MA SPI: board level, connect KS8995MA pins follows:
KS8995MA Number KS8995MA Signal Name SPIS_N SPIC SPID SPIQ Microprocessor Signal Description Slave Select Clock Master Slave Input Master Slave Output
Table Connections input signals PS[1:0] (pins 114, respectively) "10" serial configuration slave mode. Power board assert reset signal. After reset, start switch Register will `0'. Configure desired settings KS8995MA before setting start register `1.' Write configuration registers using typical write data cycle shown Figure multiple write shown Figure Note that data input SPID registered rising edge SPIC. Registers read configuration verified with typical read data cycle shown Figure multiple read shown Figure Note that read data registered SPIQ falling edge SPIC. After configuration written verified, write Register begin KS8995MA operation.
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SPIS_N SPIC SPID SPIQ
WRITE COMMAND
WRITE ADDRESS
WRITE DATA
Figure Write Data Cycle
SPIS_N SPIC SPID SPIQ
READ COMMAND
READ ADDRESS
READ DATA
Figure Read Data Cycle
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SPIS_N SPIC SPID SPIQ
WRITE COMMAND SPIS_N SPIC SPID SPIQ
WRITE ADDRESS
Byte
Byte
Byte
Byte
Figure Multiple Write
SPIS_N SPIC SPID SPIQ
READ COMMAND SPIS_N SPIC SPID SPIQ
READ ADDRESS
Byte
Byte
Byte
Byte
Figure Multiple Read
Management Interface (MIIM)
standard MIIM interface provided five devices KS8995MA. external device with MDC/MDIO capability able read status configure settings. details MIIM interface standard please reference IEEE 802.3 specification (section 22.2.4.5). MIIM interface does have access configuration registers KS8995MA. only access standard registers. "MIIM Registers." interface, other hand, used access entire KS8995MA feature set.
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Register Description
Offset Decimal 2-11 12-15 16-29 30-31 32-45 46-47 48-61 62-63 64-77 78-79 80-93 94-95 96-103 104-109 110-111 112-120 121-122 123-124 125-126 0x00-0x01 0x02-0x0B 0x0C-0x0F 0x10-0x1D 0x1E-0x2F 0x20-0x2D 0x2E-0x2F 0x30-0x3D 0x3E-0x3F 0x40-0x4D 0x4E-0x4F 0x50-0x5D 0x5E-0x5F 0x60-0x67 0x68-0x6D 0x6E-0x6F 0x70-0x78 0x79-0x7A 0x7B-0x7C 0x7D-0x7E 0x7F Description Chip Registers Global Control Registers Reserved Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Priority Control Registers Address Registers Indirect Access Control Registers Indirect Data Registers Digital Testing Status Registers Digital Testing Control Registers Analog Testing Control Registers Analog Testing Status Register
Global Registers
Address Name Description Mode Default Register (0x00): Chip Family Chip family. 0x95
Register (0x01): Chip Start Switch Chip Revision Start Switch assigned series. (95MA) Revision start chip when external pins (PS1, PS0) (1,0) (0,1). Note: (PS1,PS0) (0,0) mode, chip will start automatically, after trying read external EEPROM. EEPROM does exist, chip will default values internal registers. EEPROM present, contents EEPROM will checked. switch will check: Register 0x95, Register [7:4] 0x0. this check contents EEPROM will override chip register default values chip will start when external pins (PS1, PS0) (1,0) (0,1).
Note: (PS1, PS0) (1,1) factory test only.
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Address Name Description Mode Default
Register (0x02): Global Control Reserved 802.1p Base Priority Reserved. Used classify priority incoming 802.1q packets "User priority" compared against this value classified high priority. classified priority. enable interface.
Enable
Note: enabled, switch will tri-state outputs.
LED[5][1] strap option. Pull-down (0): isolate. Pull-up (1): Enable.
Note: LED[5][1] internal pull-up.
Buffer Share Mode buffer pool shared ports. port more buffer when other ports busy. port only allowed buffer pool. switch will drop packets with 0x8808 filed, DA=01-80-C2-00-00-01. switch will drop packets qualified "flow control" packets. link change from "link" link" will cause fast aging (<800µs) address table faster. After cycle complete, logic will return normal (300 seconds Note: port
Mode
Link Change
unplugged, addresses will automatically aged out.
Register (0x03): Global Control Pass Frames switch packets including ones. Used solely debugging purpose. Works conjunction with sniffer mode. Reserved. will enable transmit flow control based result. will enable transmit flow control regardless result.
Reserved IEEE 802.3x Transmit Flow Control Disable
PMRXD3 strap option. Pull-down(0): Enable flow control. Pull-up(1): Disable Tx/Rx flow control.
Note: PMRXD3 internal pulldown.
IEEE 802.3x Receive Flow Control Disable will enable receive flow control based result. will enable receive flow control regardless result. PMRXD3 strap option. Pull-down (0): Enable flow control. Pull-up (1): Disable Tx/Rx flow control.
Note: default values controlled same pin, they programmed independently.
Note: PMRXD3 internal pulldown.
Frame Length Field Check
will check frame length field IEEE packets actual length does match, packet will dropped (for <1500)
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Address Name Aging Enable Description Enable function chip. Disable aging function. Mode Default
LED[5][2] strap option. Pull-down (0): Aging disable Pull-up (1): Aging enable.
Note: LED[5][2] internal pull
Fast Enable Aggressive Back Enable Turn fast (800µs). Enable more aggressive back-off algorithm half duplex mode enhance performance. This IEEE standard. PMRXD0 strap option. Pull-down (0): Disable aggressive back off. Pull-up (1): Aggressive back off.
Note: PMRXD0 internal pull down.
Register (0x04): Global Control Unicast Port-VLAN Mismatch Discard This feature used port VLAN (described Register Register 33.). packets cross VLAN boundary. unicast packets (excluding unknown/ multicast/broadcast) cross VLAN boundary. "Broadcast Storm Protection" does include multicast packets. Only DA=FFFFFFFFFFFF packets will regulated. "Broadcast Storm Protection" includes FFFFFFFFFFFF DA[40] packets. carrier sense based backpressure selected. collision based backpressure selected. fair mode selected. this mode, flow control port non-flow control port talk same destination port, packets from non-flow control port dropped. This prevent flow control port from being flow controlled extended period time. this mode, flow control port non-flow control port talk same destination port, flow control port will flow controlled. This "fair" flow control port.
Multicast Storm Protection Disable
Back Pressure Mode Flow Control Back Pressure Fair Mode
Excessive Collision Drop switch will drop packets when more collisions occur. switch will drop packets when more collisions occur.
PMRXD1 strap option. Pull-down (0): Drop excessive collision packets. Pull-up (1): Don't drop excessive collision packets.
Note: PMRXD1 internal pull down.
Huge Packet Support will accept packet sizes 1916 bytes (inclusive). This setting will override setting from same register. packet size will determined this register.
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Address Name Legal Maximum Packet Size Check Disable Description will accept packet sizes 1536 bytes (inclusive). 1522 bytes tagged packets (not including packets with STPID from ports 1-4), 1518 bytes untagged packets. packets larger than specified value will dropped. Mode Default
PMRXER strap option. Pull-down (0): 1518/1522 byte packets. Pull-up (1): 1536 byte packets.
Note: PMRXER internal pulldown.
Priority Buffer Reserve each output queue pre-allocated buffers, used exclusively high priority packets. recommended enable this when priority queue feature turned reserved buffers high priority packets.
Register (0x05): Global Control 802.1q VLAN Enable 802.1q VLAN mode turned VLAN table needs before operation. 802.1q VLAN disabled. IGMP snoop enabled. IGMP packets will forwarded Switch port. IGMP snoop disabled. direct mode port This special mode Switch interface. Using preamble before MRXDV direct switch forward packets, bypassing internal look-up. normal operation. packets forwarded Switch interface will pre-tagged with source port number (preamble before MRXDV). normal operation. always deliver high priority packets first. deliver high/low packets ratio 10/1. deliver high/low packets ratio 5/1. deliver high/low packets ratio 2/1. last digits field used mask determine which port(s) packet should forwarded masks. will sniff (both source port destination port need match). will sniff (Either source port destination port needs match). This mode used implement only sniff.
IGMP Snoop Enable Switch Interface Enable Direct Mode Switch Interface
Enable Pre-Tag Switch Interface
Priority Scheme Select
Enable "Tag" Mask
Sniff Mode Select
Register (0x06): Global Control Switch Back Pressure Enable Switch Half-Duplex Mode enable half-duplex back pressure switch interface. disable back pressure switch interface. enable interface half-duplex mode. enable interface full-duplex mode.
SMRXD2 strap option. Pull-down (0): Full-duplex mode. Pull-up (1): Half-duplex mode. Note:
SMRXD2 internal pull-down.
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Address Name Switch Flow Control Enable Description enable full-duplex flow control switch interface. disable full-duplex flow control switch interface. Mode Default(1)
SMRXD3 strap option. Pull-down (0): disable flow control. Pull-up(1): enable flow control.
Note: SMRXD3 internal pulldown.
Switch 10BT switch interface 10Mbps mode. switch interface 100Mbps mode. SMRXD1 strap option. Pull-down (0): Enable 100Mbps. Pull-up (1): Enable 10Mpbs.
Note: SMRXD1 internal pulldown.
Null Replacement Broadcast Storm Protection Rate [10:8] will replace null with port bits). replacement null VID. This along with next register determines many byte blocks" packet data allowed input port preset period. period 50ms 100BT 500ms 10BT. default
Register (0x07): Global Control Broadcast Storm Protection Rate [7:0] This along with previous register determines many byte blocks" packet data allowed input port preset period. period 50ms 100BT 500ms 10BT. default 0x4A(1)
Note: 148,800 frames/sec 50ms/interval frames/interval (approximately) 0x4A.
Register (0x08): Global Control Factory Testing Reserved. 0x24
Register (0x09): Global Control Factory Testing Reserved. 0x28
Register (0x0A): Global Control Factory Testing Reserved. 0x24
Register (0x0B): Global Control Reserved Power Save Factory Setting Mode disable power save mode. enable power save mode. Reserved. mode mode SMRXD0 strap option. Pull-down(0): Enabled mode Pull-up(1): Enabled mode
Note: SMRXD0 internal pull-down
Mode LEDX_2 LEDX_1 LEDX_0 Special TPID Mode Lnk/Act Fulld/Col Speed Mode 100Lnk/Act 10Lnk/Act Fulld
Used direct mode forwarding from port "Spanning Tree" functional description.
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Port Registers
following registers used enable features that assigned port basis. register assignments same ports, address each port different, indicated.
Register (0x10): Port Control Register (0x20): Port Control Register (0x30): Port Control Register (0x40): Port Control Register (0x50): Port Control Address Name Broadcast Storm Protection Enable DiffServ Priority Classification Enable 802.1p Priority Classification Enable Port-Based Priority Classification Enable Description enable broadcast storm protection ingress packets port. disable broadcast storm protection. enable DiffServ priority classification ingress packets port. disable DiffServ function. enable 802.1p priority classification ingress packets port. disable 802.1p. ingress packets port will classified high priority "DiffServ" "802.1p" classification enabled fails classify. ingress packets port will classified priority "DiffServ" "802.1p" classification enabled fails classify. Mode Default
Note: "DiffServ", "802.1p" port priority enabled same time. OR'ed result 802.1p DSCP overwrites port priority.
Reserved Insertion Reserved. when packets output port, switch will 802.1q tags packets without 802.1q tags when received. switch will tags packets already tagged. inserted ingress port's "port VID." disable insertion. when packets output port, switch will remove 802.1q tags from packets with 802.1q tags when received. switch will modify packets received without tags. disable removal. port output queue split into high priority queues. single output queue port. There priority differentiation even though packets classified into high priority.
Removal
Priority Enable
Register (0x11): Port Control Register (0x21): Port Control Register (0x31): Port Control Register (0x41): Port Control Register (0x51): Port Control Address Name Sniffer Port Description port designated sniffer port will transmit packets that monitored. Port normal port. packets received port will marked "monitored packets" forwarded designated "sniffer port." receive monitoring. Mode Default
Receive Sniff
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Address Name Transmit Sniff Description packets transmitted port will marked "monitored packets" forwarded designated "sniffer port." transmit monitoring. Define port's "Port VLAN membership." stands port port 4.bit port port only communicate within membership. includes port membership, excludes port from membership. Mode Default
Port VLAN Membership
0x1f
Register (0x12): Port Control Register (0x22): Port Control Register (0x32): Port Control Register (0x42): Port Control Register (0x52): Port Control Address Name Reserved Ingress VLAN Filtering. Description Reserved. switch will discard packets whose port membership VLAN table bit[20:16] does include ingress port. ingress VLAN filtering. Mode Default
Discard Non-PVID Packets. switch will discard packets whose does match ingress port default VID. packets will discarded. Force Flow Control will always enable flow control port, regardless result. flow control enabled based result.
Note: Setting port both half-duplex forced flow control illegal configuration. half-duplex enable back pressure.
port only, there special configuration default, PCOL strap option. Pull-down (0): Force flow control. Pull-up (1): Force flow control.
Note: PCOL internal pull-down.
Back Pressure Enable enable port's half-duplex back pressure. disable port's half-duplex back pressure. PMRXD2 strap option. Pull-down (0): disable back pressure. Pull-up (1): enable back pressure.
Note: PMRXD2 internal pull-down.
Transmit Enable Receive Enable Learning Disable enable packet transmission port. disable packet transmission port. enable packet reception port. disable packet reception port. disable switch address learning capability. enable switch address learning.
Note: Bits used spanning tree support. "Spanning Tree Support" section.
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Register (0x13): Port Control Register (0x23): Port Control Register (0x33): Port Control Register (0x43): Port Control Register (0x53): Port Control Address Name Default [15:8] Description Port's default tag, containing: 7-5: user priority bits VID[11:8] Mode Default
Register (0x14): Port Control Register (0x24): Port Control Register (0x34): Port Control Register (0x44): Port Control Register (0x54): Port Control Address Name Default [7:0] Description Default port tag, containing: 7-0: VID[7:0] Mode Default
Note: Registers (and those corresponding other ports) serve purposes: associated with ingress untagged packets, used egress tagging; default ingress untagged null-VID-tagged packets, used address look-up.
Register (0x15): Port Control Register (0x25): Port Control Register (0x35): Port Control Register (0x45): Port Control Register (0x55): Port Control Address Name Transmit High Priority Rate Control [7:0] Description This along with port control bits [3:0] form 12-bit field determine many "32Kbps" high priority blocks transmitted unit bytes second period). Mode Default
Register (0x16): Port Control Register (0x26): Port Control Register (0x36): Port Control Register (0x46): Port Control Register (0x56): Port Control Address Name Transmit Priority Rate Control [7:0] Description This along with port control bits [7:4] form 12-bit field determine many "32Kbps" priority blocks transmitted unit bytes second period). Mode Default
Register (0x17): Port Control Register (0x27): Port Control Register (0x37): Port Control Register (0x47): Port Control Register (0x57): Port Control Address Name Transmit Priority Rate Control [11:8] Description This along with port control bits [7:0] form 12-bit field determine many "32Kbps" priority blocks transmitted unit bytes second period). This along with port control bits [7:0] form 12-bit field determine many "32Kbps" high priority blocks transmitted unit bytes second period). Mode Default
Transmit High Priority Rate Control [11:8]
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Register (0x18): Port Control Register (0x28): Port Control Register (0x38): Port Control Register (0x48): Port Control Register (0x58): Port Control Address Name Receive High Priority Rate Control [7:0] Description This along with port control bits [3:0] form 12-bit field determine many "32Kbps" high priority blocks received unit bytes second period). Mode Default
Register (0x19): Port Control Register (0x29): Port Control Register (0x39): Port Control Register (0x49): Port Control Register (0x59): Port Control Address Name Receive Priority Rate Control [7:0] Description This along with port control bits [7:4] form 12-bit field determine many "32Kbps" priority blocks received unit bytes second period). Mode Default
Register (0x1A): Port Control Register (0x2A): Port Control Register (0x3A): Port Control Register (0x4A): Port Control Register (0x5A): Port Control Address Name Receive Priority Rate Control [11:8] Description This along with port control bits [7:0] form 12-bit field determine many "32Kbps" priority blocks received unit bytes second period). This along with port control bits [7:0] form 12-bit field determine many "32Kbps" high priority blocks received unit bytes second period). Mode Default
Receive High Priority Rate Control [11:8]
Register (0x1B): Port Control Register (0x2B): Port Control Register (0x3B): Port Control Register (0x4B): Port Control Register (0x5B): Port Control Address Name Receive Differential Priority Rate Control Description also this will enable receive rate control this port priority packets priority rate. also `1', this will enable receive rate control high priority packets high priority rate. receive rate control will based priority rate packets this port. enable port's priority receive rate control feature. disable port's priority receive rate control. also this will enable port's high priority receive rate control feature. `1', receive packets this port will rate controlled priority rate. disable port's high priority receive rate control feature. flow control asserted port's priority receive rate exceeded. flow control asserted port's priority receive rate exceeded. Mode Default
Priority Receive Rate Control Enable High Priority Receive Rate Control Enable
Priority Receive Rate Flow Control Enable
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Address Name High Priority Receive Rate Flow Control Enable Description flow control asserted port's high priority receive rate exceeded this, differential receive rate control must on). flow control asserted port's high priority receive rate exceeded. will transmit rate control both high priority packets based rate counters defined high priority packets respectively. will transmit rate control packets. rate counters defined priority will used. enable port's priority transmit rate control feature. disable port's priority transmit rate control feature. enable port's high priority transmit rate control feature disable port's high priority transmit rate control feature. Mode Default
Transmit Differential Priority Rate Control
Priority Transmit Rate Control Enable
High Priority Transmit Rate Control Enable
Register (0x1C): Port Control Register (0x2C): Port Control Register (0x3C): Port Control Register (0x4C): Port Control Register (0x5C): Port Control Address Name Disable Auto-Negotiation Description disable auto-negotiation, speed duplex decided same register. auto-negotiation forced 100BT disabled (bit forced 10BT disabled (bit forced full-duplex disabled enabled failed. forced half-duplex disabled enabled failed. Mode Default
Forced Speed Forced Duplex
port only, there special configure default, PCRS strap option. Pull-down (0): Force half-duplex. Pull-up (1): Force full-duplex.
Note: PCRS internal pull down.
Advertised Flow Control Capability Advertised 100BT Full-Duplex Capability Advertised 100BT Half-Duplex Capability Advertised 10BT Full-Duplex Capability advertise flow control capability. suppress flow control capability from transmission link partner. advertise 100BT full-duplex capability. suppress 100BT full-duplex capability from transmission link partner. advertise 100BT half-duplex capability. suppress 100BT half-duplex capability from transmission link partner. advertise 10BT full-duplex capability. suppress 10BT full-duplex capability from transmission link partner.
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Address Name Advertised 10BT Half-Duplex Capability Description advertise 10BT half-duplex capability. suppress 10BT half-duplex capability from transmission link partner. Mode Default
Note: Port Control Port Status contents accessed MIIM (MDC/MDIO) interface standard MIIM register definition.
Register (0x1D): Port Control Register (0x2D): Port Control Register (0x3D): Port Control Register (0x4D): Port Control Register (0x5D): Port Control Address Name Description Turn port's LEDs (LEDx_2, LEDx_1, LEDx_0, where port number). These pins will driven high this one. normal operation. disable port's transmitter. normal operation. restart auto-negotiation. normal operation. disable fault detection pattern transmission. enable fault detection pattern transmission. power down. normal operation. disable auto MDI/MDI-X function. enable auto MDI/MDI-X function. auto MDI/MDI-X disabled, force into mode. force into mode. Perform loopback. normal operation. Mode Default
Txids Restart Disable Fault Power Down Disable Auto MDI/MDI-X Forced
Loopback
Register (0x1E): Port Status Register (0x2E): Port Status Register (0x3E): Port Status Register (0x4E): Port Status Register (0x5E): Port Status Address Name MDI-X Status Done Link Good Partner Flow Control Capability Partner 100BT Full-Duplex Capability Partner 100BT Half-Duplex Capability Partner 10BT Full-Duplex Capability Partner 10BT Half-Duplex Capability Description MDI. MDI-X. done. done. link good. link good. link partner flow control capable. link partner flow control capable. link partner 100BT full-duplex capable. link partner 100BT full-duplex capable. link partner 100BT half-duplex capable. link partner 100BT half-duplex capable. link partner 10BT full-duplex capable. link partner 10BT full-duplex capable. link partner 10BT half-duplex capable. link partner 10BT half-duplex capable. Mode Default
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Register (0x1F): Port Control Register (0x2F): Port Control Register (0x3F): Port Control Register (0x4F): Port Control Register (0x5F): Port Control Address Name Loopback Description perform loopback, i.e. loopback MAC's back normal operation. perform remote loopback, i.e. loopback PHY's back normal operation. electrical isolation from Tx+/Tx-. normal operation. soft reset. normal operation. Force link PHY. normal operation. fault status detected. fault status detected. Mode Default
Remote Loopback
Isolate Soft Reset Force Link Reserved Fault
Advanced Control Registers
IPv4 priority control registers implement fully decoded differentiated services code point (DSCP) register used determine priority from field header. most significant bits field fully decoded into possibilities, singular code that results compared against corresponding DSCP register. register priority high; register priority low.
Address Name Description Mode Default
Register (0x60): Priority Control Register DSCP[63:56] 00000000
Register (0x61): Priority Control Register DSCP[55:48] 00000000
Register (0x62): Priority Control Register DSCP[47:40] 00000000
Register (0x63): Priority Control Register DSCP[39:32] 00000000
Register (0x64): Priority Control Register DSCP[31:24] 00000000
Register (0x65): Priority Control Register DSCP[23:16] 00000000
Register (0x66): Priority Control Register DSCP[15:8] 00000000
Register (0x67): Priority Control Register DSCP[7:0] 00000000
Registers define switching engine's address. This 48-bit address used source address pause control frames.
Register (0x68): Address Register MACA[47:40] 0x00
Register (0x69): Address Register M9999-060704 MACA[39:32] 0x10
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Address Name Description Mode Default
Register (0x6A): Address Register MACA[31:24] 0xA1
Register (0x6B): Address Register MACA[23:16] 0xff
Register (0x6C): Address Register MACA[15:8] 0xff
Register (0X6D): Address Register MACA[7:0] 0xff
registers read write data static address table, VLAN table, dynamic address table, counters.
Address
Name
Description
Mode
Default
Register (0x6E): Indirect Access Control Reserved Read High Write Table Select Reserved. read cycle. write cycle. static address table selected. VLAN table selected. dynamic address table selected. counter selected. indirect address.
Indirect Address High
Register (0x6F): Indirect Access Control Indirect Address indirect address. 00000000
Note: Write Register will actually trigger command. Read write access will decided Register 110.
Address
Name
Description
Mode
Default
Register (0x70): Indirect Data Register 68-64 Indirect Data 68-64 indirect data. 00000
Register (0x71): Indirect Data Register 63-56 Indirect Data 63-56 indirect data. 00000000
Register (0x72): Indirect Data Register 55-48 Indirect Data 55-48 indirect data. 00000000
Register (0x73): Indirect Data Register 47-40 Indirect Data 47-40 indirect data. 00000000
Register (0x74): Indirect Data Register 39-32 Indirect Data 39-32 indirect data. 00000000
Register (0x75): Indirect Data Register 31-24 Indirect Data 31-24 indirect data 00000000
Register (0x76): Indirect Data Register 23-16 Indirect Data 23-16 indirect data. 00000000
Register (0x77): Indirect Data Register 15-8 Indirect Data 15-8 indirect data. 00000000
Register (0x78): Indirect Data Register Indirect Data indirect data. 00000000
write read to/from Register isters 127. Doing prevent proper operation. Micrel internal testing only.
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Address Name Description Mode Default
Register (0x79): Digital Testing Status Factory Testing Reserved. Qm_split status
Register (0x7A): Digital Testing Status Factory Testing Reserved. Dbg[7:0]
Register (0x7B): Digital Testing Control Factory Testing Reserved. Dbg[12:8]
Register (0x7C): Digital Testing Control Factory Testing Reserved.
Register (0x7D): Analog Testing Control Factory Testing Reserved.
Register (0x7E): Analog Testing Control Factory Testing Reserved.
Register (0x7F): Analog Testing Status Factory Testing Reserved.
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Static Address
KS8995MA static dynamic address table. When look-up requested, both tables will searched make packet forwarding decision. When look-up requested, only dynamic table searched aging, migration, learning purposes. static look-up result will have precedence over dynamic look-up result. there matches both tables, result from static table will used. static table only accessed controlled external master (usually processor). entries static table will aged KS8995MA. external device does addition, modification deletion.
Note: Register assignments different static table reads static table write, shown tables below.
Address
Name
Description
Mode
Default
Format Static Table Reads entries) 60-57 Reserved Override Filter VLAN representing active VLANs. (FID+MAC) look-up static table. only look-up static table. Reserved. override spanning tree "transmit enable "receive enable setting. This used spanning tree implementation. override. this entry valid, look-up result will used. this entry valid. bits control forward ports, example: 00001, forward port 00010, forward port 10000, forward port 00110, forward port port 11111, broadcasting (excluding ingress port) address. 0000
52-48
Valid Forwarding Ports
00000
47-0
Address
Format Static Table Writes entries) 59-56 Override Filter VLAN representing active VLANs. (FID+MAC) look-up static table. only look-up static table. override spanning tree "transmit enable "receive enable setting. This used spanning tree implementation. override. this entry valid, look-up result will used. this entry valid. bits control forward ports, example: 00001, forward port 00010, forward port 10000, forward port 00110, forward port port 11111, broadcasting (excluding ingress port) 48-bit address. 0000
52-48
Valid Forwarding Ports
00000
47-0
Address
Table Static Address Table
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Examples: Static Address Table Read (read entry) Write Register with 0x10 (read static table selected) Write Register with (trigger read operation) Then Read Register (60-56) Read Register (55-48) Read Register (47-40) Read Register (39-32) Read Register (31-24) Read Register (23-16) Read Register (15-8) Read Register (7-0) Static Address Table Write (write entry) Write Register (59-56) Write Register (55-48) Write Register (47-40) Write Register (39-32) Write Register (31-24) Write Register (23-16) Write Register (15-8) Write Register (7-0) Write Register with 0x00 (write static table selected) Write Register with (trigger write operation)
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VLAN Address
VLAN table used VLAN table look-up. 802.1q VLAN mode enabled (Register =1), this table used retrieve VLAN information that associated with ingress packet. information includes (filter ID), (VLAN ID), VLAN membership described below:
Address Name Description Mode Default
Format Static VLAN Table entries) 20-16 Valid Membership entry valid. entry invalid. Specify which ports members VLAN. look-up fails match both static dynamic tables), packet associated with this VLAN will forwarded ports specified this field. E.g., 11001 means port this VLAN. Filter KS8995MA supports active VLANs represented these four fields. mapped 802.1q VLAN enabled, look-up will based FID+DA FID+SA. IEEE 802.1q VLAN 11111
15-12
11-0
Table VLAN Table 802.1q VLAN mode enabled, KS8995MA assigns every ingress packet. packet untagged tagged with null VID, packet assigned with default port ingress port. packet tagged with non-null VID, used. look-up process starts from VLAN table look-up. valid, packet dropped address learning occurs. valid, retrieved. FID+DA FID+SA lookups performed. FID+DA look-up determines forwarding ports. FID+DA fails, packet broadcast members (excluding ingress port) VLAN. FID+SA fails, FID+SA learned. Examples: VLAN Table Read (read entry) Write Register with 0x14 (read VLAN table selected) Write Register with (trigger read operation) Then Read Register (VLAN table bits 21-16) Read Register (VLAN table bits 15-8) Read Register (VLAN table bits 7-0) VLAN Table Write (write entry) Write Register (VLAN table bits 21-16) Write Register (VLAN table bits 15-8) Write Register (VLAN table bits 7-0) Write Register with 0x04 (write static table selected) Write Register with (trigger write operation)
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Dynamic Address
This table read only. contents maintained KS8995MA only.
Address Name Description Mode Default
Format Dynamic Address Table entries) 67-58 Empty Valid Entries there valid entry table. there valid entries table. Indicates many valid entries table. 0x3ff means entries means entries means entry means entry 2-bit counters internal aging entry ready, retry until this entry ready. source port where FID+MAC learned. port port port port port Filter 48-bit address.
57-56 54-52
Time Stamp Data Ready Source Port
51-48 47-0
Address
Table Dynamic Address Table Examples: Dynamic Address Table Read (read entry), retrieve table size Write Register with 0x18 (read dynamic table selected) Write Register with (trigger read operation Then Read Register (68-64) Read Register (63-56); above registers show entries Read Register (55-48) restart (reread) from this register Read Register (47-40) Read Register (39-32) Read Register (31-24) Read Register (23-16) Read Register (15-8) Read Register (7-0) Dynamic Address Table Read (read 257th entry), without retrieving entries information Write Register with 0x19 (read dynamic table selected) Write Register with (trigger read operation) Then Read Register (55-48) restart (reread) from this register ister Read Register (47-40) Read Register (39-32) Read Register (31-24) Read Register (23-16) Read Register (15-8) Read Register (7-0)
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Counters
counters provided port basis. indirect memory below: port
Offset 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Counter Name RxLoPriorityByte RxHiPriorityByte RxUndersizePkt RxFragments RxOversize RxJabbers RxSymbolError RxCRCerror RxAlignmentError RxControl8808Pkts RxPausePkts RxBroadcast RxMulticast RxUnicast Rx64Octets Rx65to127Octets Rx128to255Octets Rx256to511Octets Rx512to1023Octets Rx1024to1522Octets TxLoPriorityByte TxHiPriorityByte TxLateCollision TxPausePkts TxBroadcastPkts TxMulticastPkts TxUnicastPkts TxDeferred TxTotalCollision TxExcessiveCollision TxSingleCollision TxMultipleCollision Description lo-priority (default) octet count including packets. hi-priority octet count including packets. undersize packets w/good CRC. fragment packets w/bad CRC, symbol errors alignment errors. oversize packets w/good (max: 1536 1522 bytes). packets longer than 1522B w/either errors, alignment errors, symbol errors (depends packet size setting). packets invalid data symbol legal packet size. packets within (64,1522) bytes w/an integral number bytes (upper limit depends packet size setting). packets within (64,1522) bytes non-integral number bytes (upper limit depends packet size setting). number control frames received port with 88-08h EtherType field. number PAUSE frames received port. PAUSE frame qualified with EtherType (88-08h), control opcode (00-01), data length (64B min), valid CRC. good broadcast packets (not including errored broadcast packets valid multicast packets). good multicast packets (not including control frames, errored multicast packets valid broadcast packets). good unicast packets. Total packets (bad packets included) that were octets length. Total packets (bad packets included) that between octets length. Total packets (bad packets included) that between octets length. Total packets (bad packets included) that between octets length. Total packets (bad packets included) that between 1023 octets length. Total packets (bad packets included) that between 1024 1522 octets length (upper limit depends packet size setting). lo-priority good octet count, including PAUSE packets. hi-priority good octet count, including PAUSE packets. number times collision detected later than bit-times into packet. number PAUSE frames transmitted port. good broadcast packets (not including errored broadcast valid multicast packets). good multicast packets (not including errored multicast packets valid broadcast packets). good unicast packets. packets port which attempt delayed busy medium. total collision, half-duplex only. count frames which fails excessive collisions. Successfully frames port which inhibited exactly collision. Successfully frames port which inhibited more than collision.
Table Port-1 Counter Indirect Memory Offsets
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port port port port base base base base 0x20, 0x40, 0x60, 0x80, same same same same offset offset offset offset definition definition definition definition (0x20-0x3f) (0x40-0x5f) (0x60-0x7f) (0x80-0x9f)
Mode Default
Address
Name
Description
Format Port Counters entries) 29-0 Overflow Count Valid Counter Values Counter overflow. Counter overflow. Counter value valid. Counter value valid. Counter value.
Offset 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109
Counter Name Port1 Drop Packets Port2 Drop Packets Port3 Drop Packets Port4 Drop Packets Port5 Drop Packets Port1 Drop Packets Port2 Drop Packets Port3 Drop Packets Port4 Drop Packets Port5 Drop Packets
Description packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources. packets dropped lack resources.
Table Port Dropped Packet Counters
Address Name Description Mode Default
Format Port Dropped Packet Counters 30-16 15-0 Reserved Counter Values Reserved. Counter value.
Note: port dropped packet counters indicate overflow validity; therefore application must keep track overflow valid conditions.
Examples: counter read (read port counter) Write Register with 0x1c (read counters selected) Write Register with (trigger read operation) Then Read Register (counter value 31-24) there counter overflow restart (reread) from this register Read Register (counter value 23-16) Read Register (counter value 15-8) Read Register (counter value 7-0)
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counter read (read port counter) Write Register with 0x1c (read counter selected) Write Register with 0x2e (trigger read operation Then Read Register (counter value 31-24) there counter overflow restart (reread) from this register Read Register (counter value 23-16) Read Register (counter value 15-8) Read Register (counter value 7-0) counter read (read port drop packets) Write Register with 0x1d Write Register with 0x00 Then Read Register (counter value 15-8) Read Register (counter value 7-0)
Note: read counters, best performance over (160+3) 260ms, where there registers, overhead, clocks access, 5MHz. heaviest condition, byte counter will overflow minutes. recommended that software read counters least every seconds. port counters designed "read clear." port counter will cleared after accessed. port dropped packet counters cleared after they accessed. application needs keep track overflow valid conditions these counters.
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MIIM Registers
registers defined this section also accessed interface. Note: different mapping mechanisms used MIIM SPI. "PHYAD" defined IEEE assigned "0x1" port "0x2" port "0x3" port "0x4" port "0x5" port "REGAD" supported 0,1,2,3,4,5.
Address Name Description Mode Default
Register Control Soft Reset Loop Back Force Enable Power Down Isolate Restart Force Full Duplex Collision Test Reserved Reserved Force Disable Auto MDI/MDI-X Disable Fault Disable Transmit Disable Force MDI. Normal operation. Disable auto MDI/MDI-X. Normal operation. Disable fault detection. Normal operation. Disable transmit. Normal operation. Disable LED. Normal operation. soft reset. Normal operation. Loop back mode (loopback MAC). Normal operation. 100Mbps. 10Mbps. Auto-negotiation enabled. Auto-negotiation disabled. Power down. Normal operation. Electrical isolation from Tx+/Tx-. Normal operation. Restart Auto-negotiation. Normal operation. Full duplex. Half duplex. supported.
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Address Name Description Mode Default
Register Status 10-7 Capable Full Capable Half Capable Full Capable Half Capable Reserved Preamble Suppressed Complete Fault Capable Link Status Jabber Test Extended Capable supported. Auto-negotiation complete. Auto-negotiation completed. fault detected. fault detected. Auto-negotiation capable. auto-negotiation capable. Link Link down. supported. extended register capable. BASET4 capable. 100BASE-TX full-duplex capable. capable 100BASE-TX full-duplex. 100BASE-TX half-duplex capable. 100BASE-TX half-duplex capable. 10BASE-T full-duplex capable. 10BASE-T full-duplex capable. 10BASE-T half-duplex capable. 10BASE-T half-duplex capable.
Register PHYID HIGH 15-0 Phyid High High order PHYID bits. 0x0022
Register PHYID 15-0 Phyid order PHYID bits. 0x1450
Register Advertisement Ability 12-11 Next Page Reserved Remote Fault Reserved Pause Reserved Full Half Full Half Selector Field Advertise full-duplex ability. advertise full-duplex ability. Advertise half-duplex ability. advertise half-duplex ability. Advertise full-duplex ability. advertise full-duplex ability. Advertise half-duplex ability. advertise half-duplex ability. 802.3 Advertise pause ability. advertise pause ability. supported. supported. 00001
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Address Name Description Mode Default
Register Link Partner Ability 12-11 Next Page Remote Fault Reserved Pause Reserved Full Half Full Half Reserved Link partner full capability. Link partner half capability. Link partner full capability. Link partner half capability. Link partner pause capability. supported. supported. supported. 00001
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Absolute Maximum Ratings(1)
Supply Voltage (VDDAR, VDDAP, VDDC) -0.5V +2.4V (VDDAT, VDDIO) -0.5V +4.0V Input Voltage -0.5V +4.0V Output Voltage -0.5V +4.0V Lead Temperature (soldering, sec.) 270°C Storage Temperature (TS) -55°C +150°C
Operating Ratings(2)
Supply Voltage (VDDAR, VDDAP, VDDC) +1.7V +1.9V (VDDAT, VDDIO) +2.4V +2.6V +3.0 +3.6 Ambient Temperature (TA) Commercial -0°C +70°C Industrial -40°C +85°C Package Thermal Resistance(3) PQFP (JA) Flow 59.47°C/W
Electrical Characteristics(4,
Symbol Parameter Condition Units 100BASE-TX Operation Ports 100% Utilization IDDC IDDIO IDDC IDDIO IDDC IDDIO Inputs Outputs |IOZ| VIMB Output High Voltage Output Voltage Output Tri-State Leakage -8mA VDDIO termination differential output termination differential output 0.95 +2.4 +0.4 Input High Voltage Input Voltage Input Current (Excluding Pull-up/Pull-down) VDDIO +2.0 +0.8 100BASE-TX (Transmitter) 100BASE-TX (Digital Core/PLL Analog 100BASE-TX (Digital VDDAT VDDC, VDDAP, VDDAR VDDIO VDDAT VDDIO VDDAT VDDC, VDDAP VDDIO
10BASE-TX Operation Ports 100% Utilization 10BASE-TX (Transmitter)
10BASE-TX (Digital Core Analog VDDC, VDDAP 10BASE-TX (Digital
Auto-Negotiation Mode 10BASE-TX (Transmitter) 10BASE-TX (Digital Core Analog 10BASE-TX (Digital
100BASE-TX Transmit (measured differentially after transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance
Notes: Exceeding absolute maximum rating damage device. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (ground VDD). heat spreader package. Specification packaged product only. Measurements were taken within operating ratings.
1.05
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Symbol Parameter Condition ±0.5 Peak-to-peak
Units
100BASE-TX Transmit (measured differentially after transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Output Jitters 10BASE-TX Receive Squelch Threshold 5MHz square wave
10BASE-T Transmit (measured differentially after transformer) VDDAT 2.5V Peak Differential Output Voltage Jitters Added Rise/Fall Times termination differential output termination differential output ±3.5
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Timing Diagrams
Receive Timing tcyc1
Figure EEPROM Interface Input Receive Timing Diagram
tcyc1 Transmit Timing
tov1
Figure EEPROM Interface Output Transmit Timing Diagram
Symbol tCYC1 tOV1
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
16384
Units
4096 4112 4128
Table EEPROM Timing Parameters
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Receive Timing
tcyc2
MTXC MTXEN
MTXD[0]
Figure Input Timing
tcyc2 Transmit Timing
MRXC MRXDV MCOL MRXD[0]
tov2
Figure Output Timing
Symbol tCYC2
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
Units
Table Timing Parameters
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Receive Timing
tcyc3
MRXCLK MTXEN MTXER MTXD[3:0]
Figure Mode Timing Data Received from
tcyc3 Transmit Timing
MTXCLK MRXDV MRXD[3:0]
tov3
Figure Mode Timing Data Transmitted from
Symbol tCYC3 tCYC3 tOV3
Parameter Clock Cycle (100BASE-T) Clock Cycle (10BASE-T) Set-Up Time Hold Time Output Valid
Units
Table Mode Timing Parameters
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Receive Timing
tcyc4
MTXCLK MTXEN MTXER MTXD[3:0]
Figure Mode Timing Data Received from
tcyc4 Transmit Timing
MRXCLK MRXDV MRXD[3:0]
tov4
Figure Mode Timing Data Transmitted from
Symbol tCYC4 tCYC4 tOV4
Parameter Clock Cycle (100BASE-T) Clock Cycle (10BASE-T) Set-Up Time Hold Time Output Valid
Units
Table Mode Timing Parameters
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tSHSL
SPIS_N tCHSL SPIC tDVCH tCHDX SPID tDLDH tDHDL SPIQ High Impedance tCLCH tCHCL tSLCH tCHSH tSHCH
Figure Input Timing
Symbol tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL
Parameter Clock Frequency SPIS_N Inactive Hold Time SPIS_N Active Set-Up Time SPIS_N Active Hold Time SPIS_N Inactive Set-Up Time SPIS_N Deselect Time Data Input Set-Up Time Data Input Hold Time Clock Rise Time Clock Fall Time Data Input Rise Time Data Input Fall Time
Units
Table Input Timing Parameters
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SPIS_N SPIC tCLQV tCLQX SPIQ tQLQH tQHQL SPID tSHQZ
Figure Output Timing
Symbol tCLQX tCLQV tQLQH tQHQL tSHQZ
Parameter Clock Frequency SPIQ Hold Time Clock SPIQ Valid Clock High Time Clock Time SPIQ Rise Time SPIQ Fall Time SPIQ Disable Time
Units
Table Output Timing Parameters
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Supply Voltage
RST_N
Strap-In Value Strap-In Output
Figure Reset Timing
Symbol
Parameter Stable Supply Voltages Reset High Configuration Set-Up Time Configuration Hold Time Reset Strap-In Output
Units
Table Reset Timing Parameters
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Selection Isolation Transformer(1)
simple isolation transformer needed line interface. isolation transformer with integrated common-mode choke recommended exceeding requirements. following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) Hipot (min.)
Note: IEEE 802.3u standard 100BASE-TX assumes transformer loss 0.5dB. transmit line transformer, insertion loss 1.3dB compensated increasing line drive current means reducing ISET resistor value.
Value 350µH 0.4µH 12pF 1.0dB 1500Vrms
Test Condition
100mV, 100kHz, 1MHz (min.)
0MHz 65MHz
following transformer vendors provide compatible magnetic parts Micrel's device:
4-Port IntegratedAuto Vendor Pulse Fuse Transpower Delta LanKom Part H1164 558-5999-Q9 PH406466 HB826-2 LF8731 SQ-H48W Number MDI-X Single Port Port Vendor Pulse Fuse Transpower Delta LanKom AutoNumber Part H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S MDI-X Port
Table Qualified Magnetics Vendors
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Package Information
128-Pin PQFP (PQ) MICREL, INC. 1849 FORTUNE DRIVE
JOSE, 95131
(408) 944-0800 (408) 474-1000 http://www.micrel.com
information furnished Micrel this data sheet believed accurate reliable. However, responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer. Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2004 Micrel, Incorporated.
June 2004
M9999-060704
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