KS8695PX Integrated Multi-Port Gateway Solution Rev. Ge

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KS8695PX Integrated Multi-Port Gateway Solution Rev. Ge

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KS8695PX
KS8695PX
Integrated Multi-Port Gateway Solution
Rev.
General Description
CENTAUR KS8695PX, Multi-Port Gateway Solution, delivers level networking integration, performance, overall cost savings, enabling original equipment manufacturers (OEMs) provide customers with feature-rich, low-cost solutions residential gateway small office environment. Integration bridge allowing incorporation variety productivity enhancing system interfaces, including expanding 802.11 a/g/b wireless LAN. High-performance ARMCPU (ARM992T) with I-cache, D-cache, memory management unit (MMU) Linux WinCE® support. XceleRoutertechnology interfaces. Proven wire-speed switching technology that includes 802.1Q tag-based VLAN quality service (QoS) support. Five patented mixed-signal, low-powered Fast Ethernet transceivers with corresponding media access control (MAC) units. Advanced memory interface with programmable 8/16/ 32-bit data 22-bit address with 64MB total memory space Flash, ROM, SRAM, SDRAM, external peripherals. Protocol engine accelerate packet processing.
Functional Diagram
CENTAUR KS8695PX
Advanced Memory Controller External Controller FLASH/ROM/ SRAM Controller SDRAM Controller
ARM922T
I-Cache
High Speed AMBA
D-Cache
XceleRouter
Bridge Switch Registers
Advanced Peripheral (APB)
Interrupt Controller
Host Bridge
High-Performance Non-Blocking 5-Port Switch
GPIOs
UART 10/100 TX/FX 10/100 TX/FX 10/100 TX/RX 10/100 TX/RX 10/100 TX/RX
Timer/ Watchdog
XceleRouter trademark Micrel, Inc.; registered trademark Advanced Micro Devices, Inc.; trademark Advanced RISC Machines Ltd.; Intel registered trademark Intel Corporation; WinCE registered trademark Microsoft Corporation.
Micrel, Inc. 2180 Fortune Drive Jose, 95131 (408) 944-0800 (408) 474-1000 http://www.micrel.com
July 2004
M9999-070604
KS8695PX
Peripheral Support 8/16/32-bit external interface supporting PCMCIA generic CPU/DSP host Sixteen general purpose input/output (GPIO) 32-bit timer counters (one watchdog) Interrupt controller System Design 166MHz 125MHz speed PBGA package (19mm 19mm) saves board real estate power supplies: 1.8V core Ethernet supply, 3.3V Ethernet supply Built-in controls Debugging ARM922T JTAG debug interface UART console port modem back-up Power Management system clock speed step-down options Low-power Ethernet transceivers port power-down Ethernet transmit disable Reference Hardware Software Evaluation Hardware evaluation board (passes class EMI) Board support package including firmware source codes, linux kernel, software stacks Documentation design programming Complete hardware software reference designs available Commercial Temperature Range: +70°C Available 289-Pin PBGA
Features
CENTAUR KS8695PX featuring XceleRouter technology single-chip multi-port gateway solution with components integrated high-performance, low-cost broadband gateway ARM922T High-Performance Core 185MIPS ARM922T core 166MHz I-cache D-cache Memory management unit (MMU) Linux WinCE® 32-bit 16-bit thumb instruction sets smaller memory footprints 33MHz 32-bit Interface version Supports mastership guest-mode Supports normal memory-mapped Support miniPCI cardbus peripherals Integrated Ethernet Transceivers Switch Engine Five 10/100 Ethernet transceivers five MACs interface, switching) 100BASE-FX mode option port port Automatic MDI/MDI-X crossover ports Wire-speed, non-blocking switch 802.1Q tag-based VLAN VLANs, full range VID) Port-based VLAN QoS/CoS packet prioritization support: port 802.1P DiffServ-based 64KB on-chip frame buffer SRAM VLAN 802.1P tag/untag option port 802.1D Spanning Tree Protocol support Programmable rate-limiting port: 0Mbps 100Mbps, ingress egress, rate options high priority Extensive counter management support IGMP snooping multicast packet filtering Dedicated entry look-up engine Port mirroring/monitoring/sniffing Broadcast storm protection with control global port basis Full- half-duplex flow control XceleRouter Technology TCP/UDP/IP packet header checksum generation offload tasks IPv4 packet filtering checksum errors Automatic error packet discard engine with burst-mode support efficient WAN/LAN data transfers FIFOs back-to-back packet transfers Memory External Interfaces 8/16/32-bit wide shared data path Flash, ROM, SRAM, SDRAM, external Total memory space 64MB Intel®/AMD®-type Flash support
Applications
combo 802.11a/b/g access point Multi-port broadband gateway Multi-port firewall appliances Combination wireless wireline gateway Multi-port VoIP gateway Fiber-to-the-home managed
Ordering Information
Part Number KS8695PX Temperature Range +70°C Package 289-Pin PBGA
M9999-070604
July 2004
KS8695PX
Revision History
Revision Date 05/13/03 07/06/04 Summary Changes Created. Copied Micrel format updated System Clock.
July 2004
M9999-070604
KS8695PX
Contents
System Level Applications Description Configuration Functional Description Introduction Features Bridge Features Switch Engine Advanced Memory Controller Features Direct Memory Access (DMA) Engines Protocol Engine XceleRouterTechnology Network Interface Peripherals Other Features Signal Description System Level Hardware Interface Configuration Pins Reset System Clock Memory Interface Signal Descriptions Group Address Register Description Memory Memory Example Register Description Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams Package Information
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System Level Applications
HomePlug Cable Fiber Satellite Wireless Flash/ROM/ SRAM Memory External 10/100 TX/FX Auto MDI-X Console Port KS8695PX
PCMCIA SDRAM 8/16/32
Integrated Multi-Port Gateway Solution
33MHz
802.11a/g/b
4-Port 10/100 TX/FX Auto MDI-X
Figure KS8695PX Gateway System Options
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Description
Signal List Alphabetized Name
Number
Note: Ground. Output. Bidirectional.
Name ADDR0 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR20/BA0 ADDR2/BA1 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AGND AGND AGND AGND AGND CBEN0 CBEN1 CBEN2 CBEN3 CLKRUNN DATA0 DATA1 DATA10 DATA11
Type(1)
Function Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Address Bit/Bank Address SDRAM Interface. Address Bit/Bank Address SDRAM Interface. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Address Bit. Analog Signal Ground. Analog Signal Ground. Analog Signal Ground. Analog Signal Ground. Analog Signal Ground. Commands Byte Enable Active Low. Commands Byte Enable Active Low. Commands Byte Enable Active Low. Commands Byte Enable Active Low. Cardbus Clock Request Signal. Active Low. External Data Bit. External Data Bit. External Data Bit. External Data Bit.
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Number
Note: Output. Bidirectional. Output normal mode; input during reset.
Name DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA2 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA3 DATA30 DATA31 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DEVSELN ECSN0 ECSN1 ECSN2 EROEN/ WRSTPLS ERWEN0/ TESTACK ERWEN1/ TESTREQB ERWEN2/ TESTREQA Type(1) Function External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. External Data Bit. Device Select Signal. Active Low. External Device Chip Select. Active Low. External Device Chip Select. Active Low. External Device Chip Select. Active Low. ROM/SRAM/FLASH External Output Enable. Active Low. WRSTO Polarity Select. External ROM/SRAM/FLASH Write Byte Enable. Active Low. External ROM/SRAM/FLASH Write Byte Enable. Active Low. External ROM/SRAM/FLASH Write Byte Enable. Active Low.
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Number
Note: Ground. Input. Output. Bidirectional.
Name ERWEN3/ TICTESTENN EWAITN FRAMEN GNT1N GPIO0/EINT0 GPIO1/EINT1 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 Type(1) Function External ROM/SRAM/FLASH Write Byte Enable. Active Low. External Wait. Active Low. Frame Signal. Active Low. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Signal Ground. Grant Active Low. Output Host Bridge Mode Guest Bridge Mode. This must left connect. This must left connect. General Purpose Pin. External Interrupt Request Pin. General Purpose Pin. External Interrupt Request Pin. General Purpose Pin. General Purpose Pin. General Purpose Pin. General Purpose Pin. General Purpose Pin.
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KS8695PX
Number
Note: Input. Output. Bidirectional.
Name GPIO15 GPIO2/EINT2 GPIO3/EINT3 GPIO4/TOUT0 GPIO5/TOUT1 GPIO6 GPIO7 GPIO8 GPIO9 IDSEL IRDYN ISET L1LED0 L1LED1 L2LED0 L2LED1 L3LED0 L3LED1 L4LED0 L4LED1 LANRXM1 LANRXM2 LANRXM3 LANRXM4 LANRXP1 LANRXP2 LANRXP3 LANRXP4 LANTXM1 LANTXM2 LANTXM3 LANTXM4 LANTXP1 LANTXP2 LANTXP3 LANTXP4 M66EN MPCIACTN PAD0 Type(1) Function General Purpose Pin. General Purpose Pin. External Interrupt Request Pin. General Purpose Pin. External Interrupt Request Pin. General Purpose Pin. Timer Output Pin. General Purpose Pin. Timer Output Pin. General Purpose Pin. General Purpose Pin. General Purpose Pin. General Purpose Pin. Initialization Device Select. Active High. Initiator Ready Signal. Active Low. Transmit Output Current. Connect Ground with 3.01k Resistor. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Programmable Indicator Active Low. Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Receive Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Port Transmit Signal (differential). Enable. MiniPCI Active Signal. Active Low. Address Data
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Number
Note: Input. Output. Bidirectional.
Name PAD1 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD2 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD3 PAD30 PAD31 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PBMS PCLK PCLKOUT0 PCLKOUT1 PERRN PRSTN Type(1) Function Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Address Data Parity. Bridge Mode Select. Host Bridge Mode. Guest Bridge Mode. Clock. Clock Output Clock Output This must left connect. This must left connect. Parity Error Signal. Active Low. Reset. Active Low.
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Number Name RCSN0 RCSN1 REQ1N RESETN SDCASN SDCSN0 SDCSN1 SDICLK SDOCLK SDQM0 SDQM1 SDQM2 SDQM3 SDRASN SDWEN SERRN STOPN TEST1 TEST2 TESTEN TRDYN TRSTN UCTSN/ BISTEN UDCDN/ SCANEN UDSRN UDTRN/ DBGENN URIN/TSTRST URTSN/ CPUCLKSEL Type(1) Function ROM/SRAM/FLASH Chip Select. Active Low. ROM/SRAM/FLASH Chip Select. Active Low. Request Active Low. Input Host Bridge Mode Guest Bridge Mode. This must left connect. This must left connect. KS8695PX Chip Reset. Active Low. SDRAM Column Address Strobe, Active Low. SDRAM Chip Select. Active Chip Select Pins SDRAM. SDRAM Chip Select. Active Chip Select Pins SDRAM. SDRAM Clock System/SDRAM Clock Out. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. SDRAM Data Input/Output Mask. SDRAM Address Strobe, Active Low. SDRAM Write Enable. Active Low. System Error Signal. Active Low. Stop Signal. Active Low. JTAG Test Clock. JTAG Test Data JTAG Test Data Out. Test (factory test signal). Test (factory test signal). Chip Test Enable (factory test signal). JTAG Test Mode Select Target Ready Signal. Active Low. JTAG Test Reset. Active Low. UART Data Ready. Active Low. BIST Enable (factory test signal). UART Data Carrier Detect. Scan Enable (factory test signal). UART Data Ready. Active Low. UART Data Terminal Ready. Active Low. Debug Enable (factory test signal). UART Ring Indicator/Chip Test Reset (factory test signal). UART Request Send/CPU Clock Select.
Note: Input. Output. Bidirectional. Output normal mode; input during reset.
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Number
Note: Power. Input. Output.
Name URXD UTXD VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD1.8 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 Type(1) Function UART Receive Data. UART Transmit Data. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 1.8V Digital Core VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V Digital Circuitry VDD. 3.3V digital Circuitry VDD.
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KS8695PX
Number Name VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA1.8 VDDA3.3 VDDA3.3 VDDA3.3 VDDA3.3 VDDA3.3 VDDA3.3 VDDA3.3 VDDA3.3 WANFXSD WANRXM WANRXP WANTXM WANTXP WLED0/ B0SIZE0 WLED1/ B0SIZE1 WRSTO XCLK1 XCLK2 Type(1) Function 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 1.8V Analog VDD. 3.3V Analog VDD. 3.3V Analog VDD. 3.3V analog VDD. 3.3V analog VDD. 3.3V analog VDD. 3.3V analog VDD. 3.3V analog VDD. 3.3V analog VDD. Fiber Signal Detect. Receive Signal (differential). Receive Signal (differential). Transmit Signal (differential). Transmit Signal (differential). Programmable Indicator Bank Size Programmable Indicator Bank Size Watchdog Timer Reset Output. External Clock External Clock (negative polarity).
Note: Power. Input. Output. Output normal mode; input during reset.
July 2004
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Description
PAD31
PAD27
CBEN3
PAD21
PAD17
IRDYN
SERRN
CBEN1
PAD12
PAD8
PAD5
PAD1
PAD0
RESETN
PCLKOUT0 PRSTN
PCLKOUT1
REQ1N
PAD29
PAD25
PAD23
PAD19
CBEN2
CLKRUNN PERRN
PAD14
PAD10
PAD7
PAD3
L1LED1
L1LED0
GNT1N
PAD28
PAD24
PAD22
PAD16
TRDYN
DEVSELN PAD13
PAD9
PAD6
PAD2
L2LED1
L2LED0
MPCIACTN PMBS
PCLK
PAD30
PAD26
IDSEL
PAD20
PAD18
FRAMEN
STOPN
PAD15
PAD11
CBEN0
PAD4 WLED0/ B0SIZE
L3LED1
L3LED0
XCLK1
XCLK2
AGND FXSD1
M66EN
VPLL1.8
VDDA1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD3.3
VDD3.3
VDD3.3
WLED1
L4LED1
L4LED0
ISET
WANFXSD
TEST2
VDDA1.8
VDDA1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD3.3
VDD3.3
VDD3.3
TRSTN GPIO1/ EINT1 GPIO3/ EINT3
TESTEN GPIO0/ EINT0 GPIO2/ EINT2
WANTXP
WANTXM
WANRXP
WANRXM VDDA1.8
VDDA1.8
VDD3.3
VDD3.3
GPIO5/ TOUT1
GPIO4/ TOUT0
LANTXP1
LANTXM1
LANRXP1
LANRXM1 VDDA1.8
VDDA1.8
AGND
VDD1.8
VDD1.8
LANTXP2
LANTXM2
LANRXP2
LANRXM2 VDDA1.8
VDDA1.8
AGND
VDD1.8
VDD1.8
GPIO9
GPIO8
GPIO7
GPIO6
LANTXP3
LANTXM3
LANRXP3
LANRXM3 VDDA3.3
VDDA3.3
AGND
VDD1.8
VDD1.8
GPIO13
GPIO12
GPIO11
GPIO10
LANTXP4
LANTXM4
LANRXP4
LANRXM4 VDDA3.3
VDDA3.3
AGND
VDD3.3
VDD3.3
URIN/ UDCDN/ TSTRST SCANEN UCTSN/ URTSN/ BISTEN CPUCLKSEL
GPIO15
GPIO14
ADDR17
ADDR18
ADDR19
TEST1
VDDA3.3
VDDA3.3
VDD1.8
VDD1.8
VDD1.8
VDD3.3
VDD3.3
VDD3.3
VDD3.3
UDSRN
ERWEN0
ADDR13
ADDR14
ADDR15 ADDR20/
ADDR16 ADDR21/
VDDA3.3
VDDA3.3
VDD1.8
VDD1.8
VDD1.8
VDD3.3
VDD3.3
VDD3.3
VDD3.3
UTXD
UDTRN
URXD
ERWEN1
ADDR11
ADDR12
SDCSN0
SDQM3
DATA31 DATA29 DATA25
DATA21
DATA17
DATA13
DATA9
DATA5
RCSN0
EWAITN ERWEN2
ADDR8
ADDR9
ADDR10
SDCSN1
SDRASN
SDQM2
DATA30 DATA28 DATA24
DATA20
DATA16
DATA12
DATA8
DATA4
RSCN1
ECSN0
ERWEN3 EROEN/ WRSTPLS
ADDR6
ADDR7
ADDR3
ADDR1
SDCASN
SDQM1
SDICLK
DATA27 DATA23
DATA19
DATA15
DATA11
DATA7
DATA3
DATA1
ECSN1
ADDR5
ADDR4
ADDR2
ADDR0
SDWEN
SDQM0
SDOCLK DATA26 DATA22
DATA18
DATA14
DATA10
DATA6
DATA2
DATA0
ECSN2
WRSTO
Signals UART Signals JTAG Signals Miscellaneous
Drivers Memory Interface GPIO Analog
VDD3.3 VDDA1.8 VDD1.8
VDDA3.3 AGND
Figure KS8695PX Mapping (Top View)
M9999-070604
July 2004
KS8695PX
Functional Description
Introduction
Micrel's KS8695PX, member CENTAUR line integrated processors, high-performance router-on-a-chip solution Ethernet 802.11 a/g/b based embedded systems. Designed communication's routers, integrates bridge solution interfacing with 32-bit PCI, miniPCI, cardbus devices. KS8695PX combines proven third generation 5-port managed switch, ARM9 RISC processor with MMU, five physical transceiver units (PHYs) including their corresponding units with Micrel's XceleRouter technology. KS8695PX built around 16/32-bit ARM922T RISC processor, which scalable, high-performance, microprocessor developed highly integrated system-on-a-chip applications. also offers configurable I-cache D-cache that reduces memory access latency high-performance applications. simple, elegant, fully static design KS8695PX especially suitable cost-effective, power-sensitive applications. KS8695PX contains five 10/100 PHYs: four local area network (LAN) wide area network (WAN). Connected PHYs five corresponding units with integrated Layer managed switch. combining switch analog PHYs make KS8695PX extremely prudent solution SOHO router applications, saving both board space costs. Layer switch contains 16Kx32 SRAM on-chip memory frame buffering. embedded frame buffer memory designed with 1.4Gbps on-chip memory bus. This allows KS8695PX perform full non-blocking frame switching and/or routing many applications media interface, KS8695PX supports 10BASE-T 100BASE-TX, specified IEEE 802.3 standard, BASE-FX port port KS8695PX supports modes operation environment: host bridge mode guest bridge mode. host bridge mode, ARM9 processor acts host entire system. configures other devices coordinates their transactions, including initiating transactions between devices subsystem. host bridge mode, registers, including those embedded switch, configured ARM922T processor through on-chip AMBA interface. guest bridge mode, registers programmed either external host local ARM922T host processor through AMBA bus. guest bridge mode, KS8695PX also functions slave bus. KS8695PX configured either ARM9 host CPU. both cases, KS8695PX memory subsystem accessible from either host ARM9 CPU. Communications between external host ARM922T accomplished through message passing through shared memory.
Features
166MHz ARM922T RISC processor core On-chip AMBA interfaces 16-bit thumb programming relax memory requirement I-cache D-cache Little-endian mode supported Configurable memory management unit Supports reduced system clock speed power savings
Bridge Features
Support 33MHz, 32-bit data Integrated bridge support interfacing with 32-bit miniPCI cardbus devices Independent clock speed Supports 125MHz speed Supports revision protocols Supports interfaces Supports both regular memory-mapped interface Integrated arbiter with power-on option enable disable Support Round Robin arbitration with three external devices internal device Supports burst transfers data words Configurable registers host ARM922T Supports mastership from 5-Port 10/100 integrated switch with four physical layer transceivers 16Kx32 on-chip SRAM frame buffering 1.4Gbps on-chip memory bandwidth wire-speed frame switching 10Mbps 100Mbps modes operation both full half duplex M9999-070604
Switch Engine
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KS8695PX
Switch Engine (continued)
Supports 802.1Q tag-based VLAN port-based VLAN Supports 8.2,1p-based priority, DiffServ priority, post-based priority Integrated address look-up engine, supports absolute addresses Automatic address learning, address aging, address migration Broadcast storm protection Full-duplex IEEE 802.3x flow control Half-duplex back pressure flow control Supports IGMP snooping Spanning Tree Protocol support
Advanced Memory Controller Features
Supports glueless connection banks ROM/SRAM/FLASH memory with programmable 8/16/32 data programmable access timing Supports glueless connection SDRAM banks with programmable 8/16/32-bit data programmable RAS/CAS latency Supports three external banks with programmable 8/16/32-bit data programmable access timing Programmable system clock speed power management Automatic address line mapping 8/16/32-bit accesses Flash, ROM, SRAM, SDRAM interfaces
Direct Memory Access (DMA) Engines
Independent engine with programmable burst mode port Independent engine with programmable burst mode ports Supports little-endian byte ordering memory buffers descriptors Contains large independent receive transmit FIFOs (3KB receive/3KB transmit) back-to-back packet receive, guaranteed under-run packet transmit Data alignment logic scatter gather capability
Protocol Engine/XceleRouter Technology
Supports IPv4 header/TCP/UDP packet checksum generation host offloading Supports IPv4 packet filtering based checksum errors
Network Interface
Features five units five units Supports 10BASE-T 100BASE-TX ports port. Also supports 100BASE-FX port port Supports automatic generation checking Supports automatic error packet discard Supports IEEE 802.3 auto-negotiation algorithm full-duplex half-duplex operation 10Mbps 100Mbps Supports full-/half-duplex operation interfaces Fully compliant with IEEE 802.3 Ethernet standards IEEE 802.3 full-duplex flow control half-duplex backpressure collision flow control Supports MDI/MDI-X auto-crossover
Peripherals
Twenty-eight interrupt sources, including four external interrupt sources Normal fast interrupt mode (IRQ, FIQ) supported Prioritized interrupt handling Sixteen programmable general purpose I/O. Pins individually configurable input, output, mode dedicated signals. programmable 32-bit timers with watchdog timer capability High-speed UART interface 115kbps
Other Features
Integrated generate system clocks JTAG development interface connection 19mm 19mm 289-pin PBGA 1.8V CMOS core 3.3V
M9999-070604
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KS8695PX
Signal Description
System Level Hardware Interfaces
KS8695PX
Clock Reset JTAG Ethernet GPIO UART
Ethernet Advanced Memory Interface
Drivers Factory Test
Power Ground
Figure System Level Interfaces system level KS8695PX features following interfaces: Clock interface crystal external oscillator JTAG development interface Ethernet physical interface Four Ethernet physical interfaces drivers high-speed UART interface Sixteen GPIO pins 33MHz, 32-bit interface supporting three external masters Advanced memory interface Programmable synchronous rate Programmable asynchronous interface timing Independently programmable data width static synchronous memory Glueless connection SDRAM Glueless connection flash memory Factory test Power ground
Configuration Pins
Configuration Bank0 Flash Data Width Name B0SIZE[1:0] E14, Settings `00'= reserved `01' byte wide `10' half word wide bits) `11' word wide bits) active high active normal mode (PLL) bypass internal guest bridge mode host bridge mode
WRSTO Polarity Clock Select Bridge Mode
EROEN/WRSTPLS URTSN/CPUCLKSEL PBMS
Table Configuration Pins
Reset
KS8695PX single reset input that driven system reset circuit simple power reset circuit. KS8695PX also features reset output (WRSTO) that used reset other devices system. WRSTO configured either active high reset active reset through strap-in option U17, shown Table KS8695PX also built watchdog timer. When watchdog timer programmed timer setting expires, KS8695PX resets itself also asserts WRSTO reset other devices system. Figure shows typical system using KS8695PX WRSTO system reset. July 2004 M9999-070604
KS8695PX
Power Reset Circuit
KS8695PX
WRSTO System Reset System
RESETN EROEN/ WRSTPLS
Memory WRSTO Active
Figure Example Reset Circuit
System Clock
clock KS8695PX supplied either 25MHz ±50ppm crystal oscillator. oscillator used, must connected input (pin KS8695PX. crystal used, must connected with circuit similar shown below. 25MHz input clock used internal generate programmable SDOCLK. SDOCLK system clock programmed from 25MHz 125MHz using system clock control register offset 0x0004. CPUCLKSEL strap-in option needs pulled normal operation. SDCLK used register data read from SDRAM back into KS8695PX. system designer must ensure that SDRAM timing when routing SDOCLK back SDICLK. KS8695PX
URTSN/ CPUCLKSEL XCLK1
SDOCLK System 25MHz 125MHz XCLK2
25MHz Xtal
22pF
22pF
Figure Typical Clock Circuit
M9999-070604
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KS8695PX
KS8695PX Half Word Wide
SDICLK SDOCLK SDCKE DATA[15.0] ADDR[12.0] ADDR[21.20] BA[1.0] DQ[15.0] A[12.0] SDRAM
Memory Interface
KS8695PX glueless interface SDRAM static memory, i.e. ROM, SRAM, Flash. supports banks static memory (Figure banks SDRAM (Figure three banks external (Figure total address space KS8695PX 64MB. This includes SDRAM, static memory, external I/O, KS8695PX's 64KB register space. memory interface SDRAM static memory special automatic address mapping feature. This allows designer connect address memory ADDR[0] KS8695PX address memory ADDR[1] memory, regardless whether designer trying achieve word, half word, byte addressing. KS8695PX memory controller performs address mapping internally. This permits designer maximum amount address bits, instead losing bits because address mapping. external I/O, however, designer still needs take care address mapping (see Figure
KS8695PX
ADDR0 ADDR1 ADDR[21:2] DATA[7:0] RCSN0 EROEN ERWEN0
SDCSN0 SDRASN SDCASN SDQM0 SDQM1 SDWEN
RAS# CAS# LDQM UDQM
KS8695PX Word Wide
SDICLK SDOCLK SDCKE DATA[31.0] ADDR[11.0] ADDR[21.20] BA[1.0] DQ[31.0] A[11.0] SDRAM
Byte Wide Static Memory
A[21:2] D[7:0]
SDCSN0
RAS# CAS# DQM[3.0]
KS8695PX
ADDR0 ADDR1 ADDR[21:2] DATA[15:0] RCSN0 EROEN ERWEN0
Half Word Wide Static Memory
A[21:2] D[15:0] BYTE
SDRASN SDCASN SDQM[3.0] SDWEN
Figure SDRAM Interface Examples
Figure Static Memory Interface Examples
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Byte Wide External
ADDR[21:0] DATA[7:0] ECSN0 EROEN ERWEN0 A[21:0] D[7:0]
KS8695PX
ADDR0 ADDR[21:1] DATA[15:0] ECSN0 EROEN ERWEN0
Half Word Wide External
A[20:0] D[15:0]
KS8695PX
ADDR0 ADDR1 ADDR[21:2] DATA[31:0] ECSN0 EROEN ERWEN0
Word Wide External
A[19:0] D[31:0]
Figure External Interface Examples
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Signal Descriptions Group
Clock Reset Pins
Name XCLK1/ CPUCLK Type(1) Description External Clock This signal used source clock transmit clock internal PHY. clock frequency 25MHz ±50ppm. XCLK1 signal also used reference clock signal internal generate 125MHz internal system clock. CPUCLK: factory clock test input when internal disabled (factory test signal). External Clock Used with XCLK1 when another polarity crystal needed. This unused normal clock input. Normal Mode: UART request send. Active output. During reset: clock select. Select clock source. CPUCLKSEL=0 (normal mode), internal clock output used clock source. CPUCLKSEL=1 (factory test signal): external clock CPUCLK used internal clock source. KS8695PX chip reset. Active input asserted least system clock (40ns) cycles reset KS8695PX. When reset state, output pins tristated open drain signals floating. Watchdog timer reset output. This signal asserted least 200ms RESETN asserted when internal watchdog timer expires. Normal Mode: ROM/SRAM/FLASH External output enable. Active low. When asserted, this signal controls output enable port specified device. During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high; WRSTPLS=1, Active low. default.
XCLK2 URTSN/ CPUCLKSEL
RESETN
WRSTO EROEN/ WRSTPLS
JTAG Interface Pins
Name TRSTN Type(1) Description JTAG test clock. JTAG test mode select. JTAG test data JTAG test data out. JTAG test reset. Active low.
Ethernet Physical Interface Pins
Name WANTXP WANTXM WANRXP WANRXM WANFXSD Type(1) Description transmit signal (differential). transmit signal (differential). receive signal (differential). receive signal (differential). fiber signal detect. Signal detect input when port operated 100BASE-FX 100Mb fiber mode.
Note: Input. Output. Output normal mode; input during reset.
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Type(1)
Ethernet Physical Interface Pins
Name LANTXP1 LANTXP2 LANTXP3 LANTXP4 LANTXM1 LANTXM2 LANTXM3 LANTXM4 LANRXP1 LANRXP2 LANRXP3 LANRXP4 LANTXM1 LANTXM2 LANTXM3 LANTXM4 ISET LANFXSD1 Description Port[4:1] transmit signal (differential).
Port[4:1] transmit signal (differential).
Port[4:1] receive signal (differential).
Port[4:1] receive signal (differential).
transmit output current. Connect ground through 3.01k resistor. fiber signal detect. Signal detect input when LAN1 port operated 100BASE-FX 100Mb fiber mode.
Drivers
Name WLED0/ B0SIZE0 Type(1) Description Normal Mode: indicator Programmable misc. Control register bits [2:0]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. During reset: Bank Data Access Size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved. WLED1/ B0SIZE1 Normal Mode: indicator Programmable Misc. Control register bits [6:4]. `000' Speed; `001'= Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. During reset: Bank data access size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved.
Note: Input. Output. Output normal mode; input during reset.
L1LED0 L2LED0 L3LED0 L4LED0 L1LED1 L2LED1 L3LED1 L4LED1
Port[4:1] indicator Programmable switch control register bits [27:25]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; '100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity. Port[4:1] indicator Programmable switch control register bits [24:22]. `000' Speed; `001' Link; `010' Full/half duplex; `011' Collision; `100' TX/RX activity; `101' Full-duplex collision; `110' Link/Activity.
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Type(1)
UART Pins
Name URXD UTXD UDTRN/ DBGENN UDSRN URTSN/ CPUCLKSEL Description UART receive data. UART transmit data. UART data terminal ready. Active low. Debug enable (factory test signal). UART data ready. Active low. Normal mode: UART request send. Active output. During reset: clock select. Select clock source. CPUCLKSEL=0 (normal mode), internal clock output used clock source. CPUCLKSEL=1 (factory test signal), external clock CPUCLK used internal clock source. UART clear send. BIST enable (factory test signal). UART data carrier detect. Scan enable (factory test signal). UART ring indicator. Chip test reset (factory test signal).
UCTSN/ BISTEN UDCDN/ SCANEN URIN/ TSTRST
General Purpose Pins
Name GPIO0/ EINT0 GPIO1/ EINT1 GPIO2/ EINT2 GPIO3/ EINT3 GPIO4/ TOUT0 GPIO5/ TOUT1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 PRSTN Type(1) Description General purpose pin. External interrupt request pin. General purpose pin. External interrupt request pin. General purpose pin. External interrupt request pin. General purpose pin. External interrupt request pin. General purpose pin. Timer output pin. General purpose pin. Timer output pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. General purpose pin. Reset. Active low. This signal input used reset KS8695PX logic. KS8695PX host, RESETN signal drive this input. KS8695PX guest, system reset drive this signal.
Note: Input. Output. Bidirectional. Output normal mode; input during reset.
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Type(1)
General Purpose Pins (continued)
Name PCLK Description clock.This signal provides timing transactions. This signal used drive interface internal logic. signals sampled rising edges PCLK. PCLK operate from 20MHz 33MHz. host mode, PCLKOUT signal drive this input. guest mode, system clock drive this input. connect. connect. grant Active low. host bridge mode, this output signal from internal arbiter grant access device connected REQ1N. guest bridge mode, this signal output indicate that KS8695PX requesting access master. guest bridge mode, this basically KS8695PX's request output. connect. connect. request Active low. host bridge mode, this input signal from external device request access. guest bridge mode, this input signal from external arbiter granting access bus. guest bridge, this basically KS8695PX's grant input. 32-Bit address data. transactions consist address phase followed more data phases. Address data signals multiplexed same pins. write transaction, source data KS8695PX. read transaction, data source target. KS8695PX supports both read write burst transactions. case read transaction, special data turn around cycle needed between address phase data phase(s).
GNT1N
REQ1N
PAD31 PAD30 PAD29 PAD28 PAD27 PAD26 PAD25 PAD24 PAD23 PAD22 PAD21 PAD20 PAD19 PAD18 PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0
Note: Input. Output. Bidirectional.
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Type(1)
General Purpose Pins (continued)
Name CBEN3 CBEN2 CBEN1 CBEN0 Description commands byte enable. Active low. command byte enable signals multiplexed same pins. During first clock cycle transaction, CBEN contains command transaction. transaction consists address phases more data phases. During data phases transaction, carries byte enable current data phases. Parity. parity even across PAD[31:0] CBEN[3:0]. KS8695PX generates during address phase write data phases master during read data phases target. checks correct during read data phase master, during every address phase slave, during write data phases target. frame signal. Active low. FRAMEN indication active cycle. asserted beginning transaction, i.e. address phase, deasserted before final transfer data phase transaction. initiator ready signal. Active low. This signal asserted master indicate valid data phase during data phases write transaction. During read transaction, indicates that master ready accept data from target. target monitors IRDYN signal when data phase completed rising edge clock when both IRDYN TRDYN asserted. Wait cycles inserted until both IRDYN TRDYN asserted together. target ready signal. Active low. This signal asserted slave indicate valid data phase during read transaction. During write transaction, indicates that slave ready accept data from target. initiator monitors TRDYN signal when data phase completed rising edge clock when both IRDYN TRDYN asserted. Wait cycles inserted until both IRDYN TRDYN asserted together. device select signal. Active low. This signal asserted when KS8695PX selected target during transaction. When KS8695PX initiator current access, expects target assert DEVSELN within five cycles, confirming access. target does assert DEVSELN within required cycles, KS8695PX aborts cycle. meet timing requirement, KS8695PX asserts this signal medium speed decode timing. cycles). Initialization device select. Active high. used chip select during configuration read write transactions. stop signal. Active low. This signal asserted target indicate master that terminating current transaction. KS8695PX responds assertion STOPN when master, either disconnect, retry, abort transaction. parity error signal. Active low. KS8695PX asserts PERRN when checks detects parity error. When generates output, KS8695PX monitors reported parity error PERRN. When KS8695PX master parity error detected, KS8695PX sets error bits control status registers. completes current data burst transaction, then stops operation. After host clears system error, KS8695PX continues opera tion. system error signal. Active low. address parity error detected, KS8695PX asserts SERRN signal clocks after failing address. 66MHz enable. When asserted, this signal indicates segment operating 66MHz. This mainly used guest bridge mode when PCLK driven external host bridge.
FRAMEN
IRDYN
TRDYN
DEVSELN
IDSEL STOPN
PERRN
SERRN M66EN
Note: Input. Output. Bidirectional.
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Type(1)
General Purpose Pins (continued)
Name PCLKOUT1 PCLKOUT0 CLKRUNN Description connect. connect. clock output clock output This cardbus only signal. CLKRUNN signal used portable cardbus devices request that system turn clock. Output always active cardbus miniPCI modes. MiniPCI active. This signal asserted device indicate that current function requires full system performance. MPCIACTN open drain output signal. miniPCI mode, this signal always low. bridge mode select. This selects operating mode bridge. When PBMS high, host bridge mode selected on-chip arbiter enabled. When PBMS low, guest bridge mode selected on-chip arbiter disabled.
MPCIACTN
PBMS
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Name SDICLK SDOCLK ADDR21/BA1 ADDR20/BA0 ADDR[19] ADDR[18] ADDR[17] ADDR[16] ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0] Type(1) Description SDRAM Clock SDRAM clock input SDRAM memory controller interface. System/SDRAM Clock Out: Output internal system clock, also used clock signal SDRAM interface. Address 21/Bank Address Input Address asynchronous accesses. Bank Address Input SDRAM accesses. Address 20/Bank Address Input Address asynchronous accesses. Bank Address Input SDRAM accesses. Address Bus: 22-bit address (including ADDR[21:20] above) covers word memory space shared ROM/SRAM/FLASH, SDRAM, external banks. During SDRAM cycles, internal address used generate addresses SDRAM. number column address bits SDRAM banks programmed from bits SDRAM control registers. ADDR[12:0] SDRAM address ADDR[21:20] SDRAM bank address. During other cycles, ADDR[21:0] byte address data transfer. SDRAM FLASH/ROM/SRAM, connect address lines, i.e. etc. memory controller automatically handles address line adjustments 8/16/32 accesses. external devices, user needs connect address lines 8/16/32 accesses.
Note: Input. Output. Bidirectional.
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Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Name DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] DATA[23] DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] SDCSN[1] SDCSN[0] SDRASN SDCASN SDWEN SDQM[3] SDQM[2] SDQM[1] SDQM[0] ECSN[2] ECSN[1] ECSN[0] EWAITN Type(1) Description External Data Bus. 32-Bit bi-directional data data transfer. KS8695PX also supports 8-bit 16-bit data widths.
SDRAM Chip Select: Active chip select pins SDRAM. KS8695PX supports SDRAM banks. SDCSN output provided each bank. SDRAM Address Strobe: Active low. address strobe SDRAM. SDRAM Column Address Strobe: Active low. column address strobe SDRAM. SDRAM Write Enable: Active low. write enable signal SDRAM. SDRAM Data Input/Output Mask: Data input/output mask signals SDRAM. SDQM sampled high output mask signal write accesses output enable signal read accesses. Input data masked during write cycle. SDQM0/1/2/3 correspond DATA[7:0], DATA[15:8], DATA[23:16] DATA[31:24], respectively. External Device Chip Select: Active low. Three external banks provided external memory mapped operations. Each bank stores 16KB. ECSNx signals indicate which three banks selected. External Wait: Active low. This signal asserted when external device ROM/SRAM/FLASH bank needs more access cycles than those defined corresponding control register. ROM/SRAM/FLASH Chip Select: Active low. KS8695PX access external ROM/SRAM/FLASH memory banks. RCSN pins controlled addresses into physical memory banks.
RCSN[1] RCSN[0]
Note: Input. Output. Bidirectional.
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Name EROEN/ WRSTPLS Type(1) Description
Normal mode: External ROM/SRAM/FLASH output enable: Active low. When asserted, this signal controls output enable port specified memory device. During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low; WRSTPLS active high. default. External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable: Active low. When asserted, ERWENx controls byte write enable memory device except SDRAM). test signal (factory test signal). External ROM/SRAM/FLASH write byte enable. Active low. When asserted, ERWENx controls byte write enable memory device (except SDRAM). test signal (factory test signal). Normal mode: indicator Programmable misc. Control register bits [2:0]. Speed; Link; Full/half duplex; Collision; TX/RX activity; Full-duplex collision; Link/Activity. During reset: Bank data access size. Bank used boot program. B0SiZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved. Normal mode: indicator Programmable Misc. Control register bits [6:4]. Speed; Link; Full/half duplex; Collision; TX/RX activity; Full-duplex collision; Link/Activity. During reset: Bank data access size. Bank used boot program. B0SIZE[1:0] used specify size bank data width follows: `01' byte, `10' half-word, `11' word, `00' reserved.
ERWEN0/ TESTACK ERWEN1/ TESTREQB ERWEN2/ TESTREQA ERWEN3/ TICTESTENN WLED0/ B0SIZE0
WLED1/ B0SIZE1
Factory Test Pins
Note: Input. Output. Output normal mode; input during reset.
Name TESTEN TEST1 TEST2
Type(1)
Description Chip test enable: (factory test signal), pull down used. test pin: (factory test signal). test pin: (factory test signal).
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Type(1)
Power Ground Pins
Note: Power.
Name VDDA1.8
Description 1.8V analog VDD.
VDD1.8
1.8V digital core VDD.
VDDA3.3
3.3V analog VDD.
VDDA3.3
3.3V digital VDD.
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Note: Power.
Name AGND Type(1) Description Analog Ground.
Ground.
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Address Register Description
Memory
Upon power KS8695PX memory configured shown below.
Address Range 0x03FF0000 0x03FFFFFF 0x02000000 0x03FEFFFF 0x00000000 0x01FFFFFF Region 64KB 32MB 32MB Description KS8695PX System Configuration Register Space Configured Flash Bank
Memory Example
default base address KS8695PX system configuration registers 0x03ff0000. After power user free remap memory their specific application. following example memory space remapped operation.
Address Range 0x03FF0000 0x03FFFFFF 0x03E00000 0x03FEFFFF 0x03200000 0x036FFFFF 0x02C00000 0x031FFFFF 0x02800000 0x02BFFFFF 0x02000000 0x027FFFFF 0x00000000 0x01FFFFFF Region 64KB 32MB Description KS8695PX System Configuration Register Space Disabled, Used Space (External I/O) Reserved FLASH Space, Used FLASH Disabled, Used SDRAM
Register Description
KS8695PX system configuration registers (SCRs) located block 64KB host memory address space. After power initialization, user remap SCRs desired offset. SCRs bits wide. They wordaligned must accessed using word instructions. AHB-PCI bridge configuration registers also included SCRs. subset AHB-PCI bridge configuration registers also accessible external host when KS8695PX configured guest mode. Refer detailed Register Description document additional information, including definitions. don't have this document, contact your local Micrel Field Application Engineer salesperson.
Register Type System Configuration External Bank External Bank External Bank Used Flash Bank Used SDRAM 16MB
Address Range 0x03FFFFFF 0x03FEFFFF 0x03FEFFFF 0x039FFFFF 0x039FFFFF 0x035FFFFF 0x035FFFFF 0x031FFFFF 0x031FFFFF 0x02FFFFFF 0x02FFFFFF 0x027FFFFF 0x027FFFFF 0x00FFFFFF 0x00FFFFFF 0x00000000
Address Range 0x0000 0x0004 0x2000 0x2224 0x4000 0x4040 0x6000 0x60FC 0x8000 0x80FC 0xA000 0xA0FC 0xE000 0xA0FC 0xE200 0xE234 0xE400 0xE410 0xE600 0xE608 0xE800 0xE850 0xEA00 0xEA18
Register Type System Configuration PCI-AHB Bridge Configuration Memory Controller Interface Reserved UART Registers Interrupt Controller Timer Registers General Purpose Switch Engine Configuration Miscellaneous
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Absolute Maximum Ratings(1)
Supply Voltage (VDDA1.8, VDD1.8, -0.5V +2.4V (VADD3.3, VDD3.3). -0.5V +4.0V Input Voltage (all inputs) -0.5V +4.0V Output Voltage (all outputs) -0.5V +4.0V Lead Temperature (soldering, 10sec.) 270°C Storage Temperature (TS) -55°C +150°C
Operating Ratings(2)
Supply Voltage (VDDA1.8, VDD1.8 +1.7V +1.9V (VDDA3.3, VDD3.3)(3) +3.0V +3.6V Ambient Temperature (TA) -0°C +70°C Junction Temperature (TJ) 150°C Package Thermal Resistance(4) PBGA (JA) Flow 29.86°C/W 1m/s 21.86°C/W 2m/s 21.54°C/W (JC)No Flow 8.34°C/W
Stresses greater than those give above cause permanent damage device. Operation device stated other conditions above those specified operating sections this specification implied. Maximum conditions extended periods affect reliability. Unused inputs must always tied appropriate logic voltage level.
Electrical Characteristics(5)
Symbol Parameter Condition Units Total Supply Current (including output driver current) 100BASE-TX Operation: ports 100% Utilization, SDOCLK 125MHz IDDIO IDDC IDDIO IDDC IDDIO IDDC 100BASE-TX (Analog 100BASE-TX (Analog 100BASE-T (Digital I/O) 100BASE-T (Digital Core) VDDA3.3 +3.3V VDDA1.8 +1.8V VDD3.3 +3.3V VDD1.8 +1.8V VDDA3.3 +3.3V VDDA1.8 VDD3.3 +3.3V VDD1.8 +1.8V VDDA3.3 +3.3V VDDA1.8 VDD3.3 +3.3V VDD1.8 +1.8V 1/2VDDA3.3 1/2VDDA3.3 VDD3.3 -8mA; VDD3.3 +0.4 -0.4 0.243 0.124 0.033 0.235
10BASE-TX Operation: ports 100% Utilization, SDOCLK 125MHz 10BASE-T (Analog 10BASE-T (Analog 10BASE-T (Digital I/O) 100BASE-T (Digital Core) 0.328 0.072 0.025 0.234
Auto-Negotiation Mode: SDOCLK 125MHz 10BASE-T (Transmitter) 10BASE-T (Analog 10BASE-T (Digital I/O) 10BASE-T (Digital Core) 0.046 0.07 0.021 0.0233
Inputs (PCI, LED, Memory Interface, UART) Input High Voltage Input Voltage Input Current (Excluding pull-up/pull-down)
Outputs (PCI, LED, Memory Interface, UART)
Notes: Exceeding absolute maximum rating damage device. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). VDDA operate from either 2.5V 3.3V supply. heat spreader package. Specification packaged product only.
Output High Voltage Output Voltage Output Tri-state Leakage
+0.4 +0.4
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Symbol Parameter Condition
Units
Outputs (PCI, LED, Memory Interface, UART) VIMB Output High Voltage Output Voltage Output Tri-state Leakage -8mA; VDD3.3 +0.4 +0.4
100BASE-TX Transmit (measured differentially after transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Output Jitters 10BASE-T Receive Squelch Threshold 5MHz square wave Peak-to-peak termination differential output termination differential output 0.95 1.05 ±0.5
10BASE-T Transmit (measured differentially after transformer) VDDAT 2.5V Peak Differential Output Voltage Jitters Added Rise/Fall Time termination differential output termination differential output ±3.5
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Timing Diagrams
timing, please refer specification, version 2.1.
Supply Voltages RESETN Strap-In Strap-In Output
Figure Reset Timing
Symbol
Parameter Stable supply voltages reset high Configuration set-up time Configuration hold time Reset strap-in output
Units
Table Reset Timing Parameters
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SDOCLK RBiTACC RCSNi RBiTPA RBiTACC ADDR[21:0] EROEN ERWENi DATA[31:0]
ADDR0 ADDR0 ADDR1
RBiTPA RBiTP
ADDR2 ADDR3
Figure Static Memory Read Cycle
SDOCLK RBiTACC RCSNi ADDR[21:0] EROEN ERWEN[3:0] DATA[31:0]
DATA ADDR
Figure Static Memory Write Cycle
Symbol
RBiTACC RBiTPA
Parameter(1) Programmable bank access time
Programmable bank page access time
Registers 0x4010 0x4014
Table Static Memory Timing Parameters
Note: Refers chip select parameters
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SDOCLK ECSN[i] EBiTACS ADDR[21:0]
Read Address
EBiTACS
Write Address
EBiTACT EBiTCOS EROEN
EBiTCOH
EBiTACT EBiTCOS ERWEN[3:0] EWAITN DATA[31:0]
RDATA WDATA
EBiTCOH
Figure External Read Write Cycles
Symbol
EBiTACS EBiTACT EBiTCOS EBiTCOH
Parameter(1) Programmable bank address setup time before chip select Programmable bank write enable/output enable access time Programmable bank chip select setup time before Programmable bank chip select hold time
Registers 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008 0x4000, 0x4004, 0x4008
Table External Timing Parameters
Note: Refers chip select parameters
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SDOCLK SDCSNi ADDR[21:0] SDRASN SDCASN SDWEN SDQM[3:0] SDCAS DATA[31:0]
Figure SDRAM Read Timing
SDOCLK SDCSNi ADDR[21:0] SDRASN SDCASN SDWEN SDQM[3:0] DATA[31:0]
Figure SDRAM Write Timing
Symbol
SDTRC SDCAS
Parameter Programmable SDRAM latency Programmable SDRAM latency
Registers 0x4038 0x4038
Table SDRAM Timing Parameters
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Package Information
289-Pin PBGA
MICREL, INC.
2180 FORTUNE DRIVE JOSE, 95131
(408) 944-0800
(408) 474-1000
http://www.micrel.com
information furnished Micrel this data sheet believed accurate reliable. However, responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer. Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2004 Micrel, Incorporated.
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KS8695PX Integrated Multi-Port Gateway Solution Rev. Ge

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