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SM3E ULTRA MINIATURE STRATUM 3E MODULE

Bulletin Page Revision Date Issued By

SM3E ULTRA MINIATURE STRATUM 3E MODULE
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Application
Features
Bulletin Page Revision Date Issued By
TM054 1 of 30 Advance A02 16 JAN 04 MBatts
General Description
Functional Block Diagram
Figure 1
Advance Data Sheet #: TM054
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Rev: A02 Date: 01 / 16 / 04
Specifications for Ultra Miniature Stratum 3E
Table 1 Parameter
Specification
Pin Description
Table 2
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Pin Diagram
Figure 2
(TOP VIEW)
Register Map
Table 3 Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b
Reg Name
Description
Advance Data Sheet #: TM054
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Register Map Continued
Table 3
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Detailed Description
The SM3E utilizes up to 8 external references, each from 8 kHz to 77.76 MHz, may be equipped and monitored for signal presence and frequency offset. Additionally, a cross-couple 8 kHz reference input is provided for master / slave operation. Reference selection may be manual or automatic, according to pre-programmed priorities. All reference switches are performed in a hitless manner, and frequency ramp controls ensure smooth output signal transitions. When references are switched, the device provides a controllable phase build-out to minimize phase transitions in the output clocks. Three output signals are provided, the first up to 77.76 MHz , the second fixed at 8 kHz for use as a frame sync signal as well as a cross-couple reference for master / slave operation. In slave mode, the output phase may be adjusted from -32 to +31.75nS relative to the master, to accommodate downstream system needs, such as different clock distribution path lengths. The third output is a BITS clock, selectable as either 1.544 MHz or 2.048 MHz. Device operation may be in Free Run, locked, or Hold Over modes. In Free Run, the clock outputs are simply determined by the Free Run frequency and accuracy of the calibrated internal clock. In locked mode, the chip phase locks to the selected input reference. While locked, a frequency history is accumulated. In Hold Over mode, the chip outputs are generated according to this history. The Digital Phase Locked Loop provides critical filtering and frequency / phase control functions that meet or exceed all requirements in critical jitter and accuracy performance parameters. Filter bandwidth may be configured to suit applications requirements. Control functions are provided via standard SPI bus register interface. Register access provides visibility into a variety of registered information as well as providing extensive programmable control capability.
Operating Modes: The SM3E Operates in Either Free Run, Locked, or Hold Over Mode:
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Detailed Description continued
Furthermore, under register access control, a backup holdover history register is provided. It may be loaded from the active holdover history or restored to the active holdover history. The active holdover history may also be flushed. Holdover mode may be entered at any time. If there is no holdover history available, the prior output frequency will be maintained. When in holdover, the application may read (via register access) the time since holdover was enterred.
Master / Slave Operation
Pairs of SM3E devices may be operated in a master / slave configuration for redundant timing source applications. A typical configuration is shown below.:
Master / Slave Configuration
Figure 3
REFS1-8 M / S REF
SM3E STC3500 1
REFS1-8
SM3E 2
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Detailed Description continued Serial Bus Timing, Read Access
Figure 4
tRWs tRWh A0
tCH A2 A3
tDRDY D0
Serial Bus Timing, Write Access
Figure 5
tCH A2 A3 tCL A4 A5 A6 1
tRWh A0
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Detailed Description continued Serial Bus Timing
Table 4 Symbol
tCS tCH tCL tRWs tRWh tDRDY tHLD tCSTRI tCSMIN
Parameter
Minimum
Nominal
Maximum
Units
Notes
Minimum delay between successive accesses300
Reference Input Quality Monitoring
Reference Input Selection, Frequencies, and Mode Selection
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Detailed Description continued
The automatic reference selection is shown in the following state diagram:
Automatic Reference Selection
Figure 6
Ref n returns, Ref m marked "revertive"
Ref n returns, Ref m marked "non-revertive"
Locked on Ref n
Loss of Ref n
Select & Lock on Ref m
The operational mode is according to the following state diagram:
No available reference and no Hold Over history Ref loss w / no good Hold Over history and no other available reference
Automatic Operational Mode Selection
Figure 7
Reference Available (Select highest priority) Higher priority Ref return with prior reference marked "revertive" Locked Ref loss w / no good hold over history and no other available reference Ref Return Free Run Ref Return Hold Over Ref Loss w / good hold over history and no alternate reference available Ref Loss w / alternate reference available
No available reference and no hold over history
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Rev: A02 Date: 01 / 16 / 04
Detailed Description continued
Output Signals and Frequency
Interrupts
Interrupts and Reference Change in Autonomous Mode
Interrupts in Manual Mode
Internal Clock Calibration
The internal clock may be calibrated by writing a frequency offset v.s. nominal frequency into the Calibration register. This calibration is used by the synchronization software to create a frequency corrected from the actual internal clock output by the value written to the Calibration register. See register descriptions.
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Register Descriptions and Operation
Low byte of chip ID: 0x11
High byte of chip ID: 0x30
Chip revision number: 0x02
Reserved
Phase Build-out Option: 1: Enable 0: Disable Default: 1
Bandwidth Selection in Hz: 0000: 0.00084 0001: 0.0016 0010: 0.0032 0011: 0.0063 0100: 0.012 0101: 0.025 0110: 0.049 0111: 0.098 (Reset Default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 - 1111: 1.6 BITS 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is 0.098 Hz. Bit 4 enables or disables phase build-out for active reference phase hits. Typically, build-out is not enabled for Stratum 3. Since the default is Stratum 3E, phase build-out operation requires register access operation of the device.
Reserved
Default: 0
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Register Descriptions and Operation continued
Reserved
Master or Slave Mode 1: Master 0: Slave (Read Only)
Free Run, Locked, or Hold Over: 0000: Free Run mode 0001: Locked on Ref1 0010: Locked on Ref2 0011: Locked on Ref3 0100: Locked on Ref4 0101: Locked on Ref5 0110: Locked on Ref6 0111: Locked on Ref7 1000: Locked on Ref8 1001 - 1111: Hold Over
Reserved
Cross reference activity 0000: No signal 0001: 8kHz 0100: 12.96MHz 0101: 19.44MHz 0110: 25.92MHz 0111: 38.88MHz 1000: 51.84MHz 1001: 77.76MHz 1010-1111: Reserved
Indicates signal presence and auto-detected frequency for the M / S REF input.
ref4 activity 1: on 0: off
ref3 activity 1: on 0: off
ref2 activity 1: on 0: off
ref1 activity 1: on 0: off
ref8 activity ref7 activity ref6 activity ref5 activity 1: on 1: on 1: on 1: on 0: off 0: off 0: off 0: off Each bit indicates the presence of a signal for that reference.
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Register Descriptions and Operation continued
ref1 sts 1: in range 0: out range
ref2 avail: 1: avail. 0: not avail.
ref1 avail: 1: avail. 0: not
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Register Descriptions and Operation continued
Calibration, 0x0f (R / W)
Bit 7 ~ Bit4
Reserved
Bit 7 ~Bit 5
Reserved
Hold Over Build Complete 1: Complete 0: Incomplete
Hold Over Available 1: Avail. 0: Not avail.
Locked 1: Locked 0: Not locked
Loss of Lock 1: Loss of Lock 0: No loss of lock
Loss of Signal 1: No activity on active reference 0: Active reference signal present
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Register Descriptions and Operation continued
Loss of Lock
Loss of Signal
Active reference change
DPLL Mode status change
M / S Ref Change from no activity to activity
M / S Ref Change from activity to no activity
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Register Descriptions and Operation continued
Enable / Revertivity Priority Disable 1: Enable 0: Highest Reserved 1: Enable 0: Disable 1: Lowest 0: Disable Default: 0 Default: 0 Default: 0 non-revertive Free Run may be treated like a reference. When it is enabled, Free Run will be entered when all references of higher priority are lost or masked. If or when a higher priority reference returns, it is switched to if Free Run is set as "revertive". When disabled, Free Run will be entered only if manually selected or all references fail without an available Hold Over history. For equal priority value, Free Run will be treated as lower priority.
Reference Switch Hold Over Hisory Policy Reserved 0: Rebuild 1: Continue Bit 0 determines if Hold Over is retained or rebuilt when a reference switch occurs. See Application Notes, Holdover History Accumulation and Management section.
Bit 1-0
Hold Over Histroy Commands 01: Save active history to backup history Reserved 10: Restore active history from backup 11: Flush the active history and accumulation register 00: No command - use to write Bit4 to change policy Bits 0-1 are written to save a holdover history to the backup history, restore the active holdover history from the backup, or flush the active history. The default value of the register is 00. The last command is latched and may be read by the application. A flush does not affect the backup history. See Application Notes, Holdover History Accumulation and Management section.
Indicates the time since entering the Hold Over state. from 0-255, one bit per hour. Zero in non-Hold Over state and stops at 255.
Cfgdata, 0x30 (R / W)
Configuration data write register. Configuration data is written to this register. Internal use only.
Configuration data write counter low byte. Low order byte of configuration data write counter. Internal use only.
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Register Descriptions and Operation continued
Configuration data write counter high byte. High order byte of configuration data write counter. Internal use only.
Chksum, 0x33 (R / W)
Configuration Data Checksum pass / fail indicator 0: Fail 1: Pass
Reserved Checksum verification register for configuration data. Internal use only.
Reserved EEPROM write enable register.
EEPROM Write Enable 0: Disable 1: Enable
Reserved
EEPROM read / write page number, 0x00 to 0x9f (0 - 159) EEPROM read / write page number register. EEPROM consist of 160 pages.
EEPROM read / write FIFO data. EEPROM read / write FIFO port register. EEPROM data is written to / read from this location.
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Performance Specifications
Performance Definitions
SM3E Performance
Input Jitter Tolerance - Input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. The SM3E device provides jitter tolerance that meets the specified requirements. Input Wander Tolerance - Input wander tolerance is the amount of wander at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify input wander TDEV v.s. integration time as shown below.
Integration Time, (seconds)
TDEV (ns)
100 31.6 x
The SM3E device provides wander tolerance that meets these requirements. Phase Transient Tolerance - GR-1244 specifies maximum reference input phase transients that a clock system must tolerate without generating an indication of improper operation. The phase transient tolerance is specified in MTIE(nS) v.s. observation time from .001 to 100 seconds, as shown below.
Observation time S (Seconds)
MTIE (ns)
61, 000 x S 925 + 4600 x S 10, 000
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Performance Specifications continued
Wander Generation Characteristics - MTIE
GR-1244-CORE, R5-5
MTIE (ns)
Observation Time (sec)
Wander Generation Characteristics - TDEV
GR-1244-CORE, R5-4
TDEV (ns)
Integration Time (sec)
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Performance Specifications continued
Wander Transfer - Wander transfer is the degree to which input wander is attenuated (or amplified) from input to output of a clock. The GR-1244 requirements for wander transfer limits are shown below.
Integration time, (seconds)
Stratum 3E TDEV (nanoseconds)
-0.5 1.86 x 1.86 x 32.2 x 0.5
The SM3E, when configured for the appropriate Stratum 3E bandwidth frequency, meets the Stratum 3E requirements, Jitter Generation - Jitter generation is the process whereby jitter appears at the output of a clock in the absence of input jitter. The device jitter generation performance is as shown below:
Jitter
Broadband (10 Hz - 2 MHz) SONET Band
19.44 MHz
8 ps Typical (12 kHz -2MHz) 5 ps Typical
77.76 MHz
8 ps Typical (12 kHz -20MHz) 1.5 ps Typical
Jitter Transfer - Jitter transfer is the degree to which input jitter is attenuated (or amplified) from input to output of a clock. It is a function of the selected bandwidth. The SM3E jitter transfer characteristics are shown below: Phase Transients - A phase transient is an unusual step or change in the phase-time of a signal over a relatively short time period. This may be due to switching between equipment, reference switching, diagnostics, entry or exit to / from Hold Over, or input reference transients. The SM3E performance for reference switches is shown below:
Phase Transients - MITE
GR-1244-CORE, R5-14
MTIE (ns)
Observation Time (sec)
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Performance Specifications continued
Capture range and Lock range - Capture range and lock range are the maximum frequency errors on the reference input within which the phase locked loop is able to achieve lock and hold lock, respectively. The SM3E Stratum 3E performance is shown below:
Characteristic
Capture range Lock in range
Requirement
Characteristic
Master / Slave phase skew Reference switch settling time Phase Build-Out resolution
Requirement
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Application Notes
Master / Slave Configuration
Figure 8
SM3E 1
REF8 STC3500
8 kHz Synchronized clock output BITS clock output
SM3E 2
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Application Notes continued
Hold Over History Accumulation Register
Active Hold Over History
Backup Hold Over History
Once lock has been achieved, holdover history is compiled in the accumulation register. It is transferred to the Active holdover history when it is ready (typically in about 15 minutes). The "Holdover Available" bit and output pin are set to "1". From then on, the Active holdover history is continually updated and kept in sync with the holdover history accumulation register. (See Figure 11).
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Application Notes continued Hold Over History access and Control Registers
Table 5 Register
0x25 0x26 0x27 0x11
Register Name
Description
Sets policy for Hold Over history accumulation: "Rebuild" or "Continue" Save, restore, and flush commands for Hold Over history Indicates the time since entering the Hold Over state Bits 3 and 4: Hold Over Available" and "Hold Over Build Complete"
Hold Over History and Status States
Figure 9
Flush
History Build Complete
Reference Switch History Build Complete, Replace Active Hold Over History
Reference Switch
History Restored from backup, re-start the building procedure.
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Application Notes continued
Control Modes
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Mechanical Specifications Mechanical Dimensions
Figure 10
2.050 52.07mm MAX. .075 1.91mm
1.250 31.75mm MAX.
1.100 27.93mm
.125 3.17mm .750 19.05mm MAX.
.070 1.78mm PIN 1
.018 .46mm
.100 2.54mm
Footprint Dimensions
Figure 11
TOP VIEW
HOLE / PAD SIZE (32 PLACES):
CUSTOMER COMPONENT KEEP OUT AREA
1. UNSOCKETED MODULE: 0.028" DIA. PLATED HOLE WITH 0.060" DIA. PAD. 2. SOCKETED MODULE: 0.038" DIA. PLATED HOLE WITH 0.070" DIA. PAD. NOTE: For compatibllity with both the unsocketed and socketed modules, Connor-Winfield recommends using a 0.038" DIA. plated hole with 0.070" DIA. pad
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Mechanical Specifications continued Required External Components
PCB Layout Recommendations
1. 2. 3. 4. 5. 6. Orient module so airflow is parallel along the header strips (pins). Place de-coupling and / or filter components as close to module pins as possible. Do not place any components directly beneath the module on the topside of the host PCB. Ensure that only clean and well-regulated power is supplied to the module. Isolate power and ground inputs to the module from noisy sources. Provide power and ground connections through a 0.050" wide trace (minimum) using 1-oz. Cu or equivalent copper feature (i.e. internal plane, copper area fill, etc.). 7. Keep module signals away from sensitive or noisy analog and digital circuitry. 8. Avoid split ground planes as high-frequency return currents may be affected. 9. Allow extra spacing between traces of high-frequency inputs and outputs. 10.Keep all traces as short as possible - avoid meandering trace paths. 11.Avoid routing signals directly beneath the module on the topside of the host PCB. 12.If possible, provide a copper area directly beneath the module on the topside of the host PCB. Connect this copper area to ground.
Optional Socket Mounting Recommendations
Mating sockets may be used if permanent installation of the SM3 module is not desired. Two possible sources for these sockets include: 1. Samtec, "Low Profile Socket Strips", SL Series, PN SL-116-G-19. (http://www.samtec.com / ) 2. Mill-Max, "Single-In-Line Sockets", 315 Series, PN 315-xx-114-41-001. (http://www.mill-max.com / ) The SM3E requires two 16-pin sockets. The optional dual footprint configuration shown in Figure 13 requires one 14-pin and two 16-pin sockets.
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Mechanical Specifications continued Optional SM3 / SM3E Dual Footprint
A dual footprint configuration may be used when designing a host circuit board containing the Connor Winfield SM3 or SM3E modules. The smaller SM3 contains a subset of the signal pins found on the larger SM3E in locations which allow for a simple dual footprint arrangement like the one shown in Figure 13.
(TOP VIEW)
Figure 13
Advance Data Sheet #: TM054
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Date: 01 / 16 / 04
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision
A00 A01 A02
Revision Date
Advance Info Data Sheet Updated with new information Updated jitter generation chart