Description ADJD-J823 CMOS mixed-signal with integrated photosensors d
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Agilent ADJD-J823 Color Management Controller with Integrated Photosensor
Description ADJD-J823 CMOS mixed-signal with integrated photosensors designed optical feedback device LED-based backlighting system. typical system consists array red, green blue (RGB) LEDs, drivers ADJD-J823. device samples light output from array, processes color information adjusts light output from LEDs until target color achieved. achieve this, device integrates photosensor array, analog-to-digital converter front-end, color data processing logic core high-resolution 12-bit output generator. employing feedback system ADJD-J823, light output produced array maintains color over time temperature. addition, using serial interface, specifying color array's light output simple picking target color coordinates from color space writing several bytes data device. sensitivity device light adjusted through automated process. output signals control on-time duration red, green blue LEDs. That duration continually adjusted real-time match light output from array target color.
Features Integrated photosensor Integrated color management feedback controller Serial Interface Direct interface standard EEPROM 3-channel 12-bit output Red, Green Blue channels Built-in oscillator Applications Backlighting
Package Dimensions
Seating Plane
0.75
0.65
1.05
Note: Dimensions millimeter (mm)
Bottom View
marker notch
Information
NAME PWMB PWMG PWMR DGND DGND DVDD AGND CLKIO XRST TYPE connect Output Output Output Ground Ground Power Ground Output Input DESCRIPTION connect. Leave floating. PWMB active-high blue pulse width modulation output pin. blue driver channel. PWMG active-high green pulse width modulation output pin. green driver channel. PWMR active-high pulse width modulation output pin. driver channel. digital ground. digital ground. Digital power pin. analog ground. CLKIO outputs reference internal clock signal. Global, asynchronous, active system reset. When asserted low, XRST resets registers. Minimum reset pulse 10us must provided external circuitry. SDASLV SCLSLV serial interface communications pins. SDASLV bidirectional data SCLSLV interface clock. pull-up resistor should tied SDASLV because goes tri-state output logic external serial EEPROM connected device store calibration configuration data. SDAPROM SCLPROM should tied data (SDA) clock (SCL) pins EEPROM. pull-up resistor should tied SDAPROM because goes tri-state output logic When SLEEP=1, device goes into sleep mode. sleep mode, analog circuits powered down clock signal gated away from core logic resulting very current consumption. analog ground. analog ground. analog ground. Analog power pin. connect. Leave floating.
SCLSLV SDASLV SCLPROM SDAPROM SLEEP
Input Input/Output (tri-state high) Output Input/Output (tri-state high) Input
AGND AGND AGND AVDD
Ground Ground Ground Power connect
Powering Device
voltage must applied IO's during power-up power-down ramp time
VDDD VDDA
tVDD_RAMP
Protection Diode Turn-On During Power-Up Power-Down particular power-up power-down sequence must used prevent diode from turning inadvertently. figure above describes sequence. general, AVDD DVDD should power-up powerdown together prevent diodes from turning inadvertently. During this period, voltage should applied IO's same reason. Ground Connection AGND DGND must both preferably star-connected central power source shown application diagram. potential difference between AGND DGND cause diodes turn inadvertently.
Block Diagram
SDASLV SCLSLV PHOTOSENSOR ARRAY
SDAPROM SCLPROM
PWMR PWMG PWMB DEVICE CONTROLLER PHOTOCURRENT VOLTAGE CONVERSION PHOTOCURRENT VOLTAGE CONVERSION GREEN PHOTOCURRENT VOLTAGE CONVERSION BLUE
XRST SLEEP
ANALOG DIGITAL CONVERSION
General Specifications
Feature Interface Input color format Output frequency Output resolution Supply Value 100kHz serial interface 6.35kHz (nominal) bits 2.6V digital (nominal), 2.6V analog (nominal)
High Level Description hardware reset asserting XRST) should performed before starting operation. assumed that factory calibration performed prior deployment ADJD-J823. Calibration discussed this section. user controls configures device programming internal registers through serial interface. start application, following register data must written Frequency registers Setup data Calibration data Bright color input registers. register data usually gathered during calibration process which performed once manufacturing. Factory calibration needed system level integrated tricolor sensor's reading (device dependent) with standard device independent color space. Once register data entered, feedback operation begins; device starts sample sensor using internal ADC. That data compared user-controlled color point target. duty factor each channel adjusted response error signal generated that comparison operation. Thus, actual color produced LEDs maintained close target. There three methods operate device. They differentiated technique which register data stored used. three figures below describe methods. NVPROM stands Non-Volatile Programmable Read-Only Memory such EEPROM.
Independent NVPROM NVPROM independent from device. During factory calibration, host must read register data from device write NVPROM. start
NVPROM
application, host must read register data from NVPROM write back device, after which device will wait further instructions normal mode.
SDASLV SCLSLV DEVICE
HOST CONTROLLER
Dedicated NVPROM Interactive Mode dedicated NVPROM connected device. During factory calibration, host instruct device upload register data NVPROM. start application, host instruct device SDASLV SCLSLV
download register data from NVPROM, after which device will wait further instructions normal mode. serial interface protocol between device NVPROM hard coded. standard NVPROM such serial EEPROM with address 0x50 (7-bit) must used.
HOST CONTROLLER
SDAPROM DEVICE SCLPROM NVPROM
Dedicated NVPROM Standalone Mode dedicated NVPROM connected device. During factory calibration, host instruct device upload register data NVPROM. difference versus Interactive Mode that, application, device itself will download register data immediately after, enter normal mode. Then, will start driving
SDAPROM DEVICE SCLPROM NVPROM
channels achieve default target color point. default color point programmed after factory calibration. host controller necessary during application. serial interface protocol between device NVPROM hard coded. standard NVPROM such serial EEPROM with address 0x50 (7-bit) must used.
Factory Calibration Factory calibration needed system level create `snapshot' initial conditions system. color management algorithm references snapshot data. effect, calibration data trims variation entire signal chain from LEDs sensor ADC. figure below shows calibration procedure brief. First, device into "open loop" mode which color management algorithm turned off. Second, host controller needs determine optimum sensor sensitivity given brightness detection level. sensitivity combination several internal settings. Searching optimum settings performed manually through automatic search routine which built into device. host start routine issuing command device. device will then turn LEDs (usually maximum duty factor) start search routine. Next, host needs turn only LEDs external camera must capture coordinates LEDs. scaled readings then written device. same time, host needs instruct device sample sensor store results. This repeated Green Blue LEDs. Lastly, host needs instruct device start calibration calculator. calculator uses camera sensor readings each color develop mapping matrix that maps sensor standard color space. mapping matrix other configuration data device setup data referred previous section.
Open Loop
Sensor Gain Self-Adjustment
Read Store LEDs Data
Read Store Green LEDs Data
Read Store Blue LEDs Data
Compute Calibration Data
Store Calibration Data Other Configuration Data
Factory Calibration Flow Chart
details, refer application note 5241 ADJD-J823 programming manual
Electrical Specifications Absolute Maximum Ratings (Notes
Parameter Storage temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Input voltage Solder Reflow Peak temperature Human Body Model rating
Symbol TSTG_ABS VDDD_ABS VDDA_ABS VIN_ABS TL_ABS ESDHBM_ABS
Minimum -0.5 -0.5 -0.5
Maximum VDDD+0.5
Units
Notes
pins pins, human body model JESD22-A114-B
Recommended Operating Conditions
Parameter Free operating temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Output current load high Output current load Input voltage high level (Note Input voltage level (Note Power supply ramp period Symbol VDDD VDDA tVDD_RAMP 0.7VDDD Minimum Typical Maximum VDDD 0.3VDDD Units
Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified)
Parameter Output voltage high level (Note Output voltage level (Note Dynamic supply current (Note 7,8) Static supply current (Note Sleep-mode supply current (Note Input leakage current
Symbol IDD_DYN IDD_STATIC IDD_SLP ILEAK
Conditions (Note (Note (Note
Minimum VDDD-0.8
Typical (Note Maximum VDDD-0.4
Units
Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified)
Parameter Internal clock frequency Symbol fCLK Conditions Minimum Typical (Note Maximum Units
Optical Specifications
Parameter Sensor operating detection range Symbol Conditions (Note &10) Minimum Maximum 10000 Units
Notes: "Absolute Maximum Ratings" those values beyond which damage device occur. device should operated these limits. parametric values defined "Electrical Specifications" table guaranteed absolute maximum ratings. "Recommended Operating Conditions" table will define conditions actual device operation. Unless otherwise specified, voltages referenced ground. Specified room temperature (25°C) VDDD VDDA 2.6V. Applies digital input pins. Applies digital output pins CLKIO pin. SDASLV SDAPROM pins tri-state when output logic high. Minimum depends pull-up resistor value. Applies digital output digital input-output pins. Dynamic testing performed with operating mode representative typical operation. Refers total device current consumption. Output bidirectional pins loaded. Using R:G:B light source brightness ratio 7:13:1 achieve white color point (x,y) (0.700, 0.300) Green (x,y) (0.171, 0.715) Blue (x,y) (0.158, 0.019)
Serial Interface Timing Information
Parameter clock frequency (Repeated) START condition hold time Data hold time clock period clock high period Repeated START condition setup time Data setup time STOP condition setup time free time between START STOP conditions Symbol fscl tHD:STA tHD:DAT tLOW tHIGH tSU:STA tSU:DAT tSU:STO tBUF Minimum Maximum 3.45 Units
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tBUF
tLOW tHD:DAT tHD:STA tSU:STO
Figure Serial Interface Timing Waveforms
Sensor Optical Performance integrated sensor spectral respond graph from 700nm. color indicates color channel color sensor.
Spectral response Green Blue Green
Relative sensitivity
Blue
Wavelength (nm)
System Performance Color Accuracy chart. Data obtain from 1078 units 25oC VDDD VDDA 2.6V. Color point x=0.287, y=0.296 (9000K) average du'v' 0.002 with standard deviation 0.0012 maximum value 0.0062.
Color Accuracy 30.0% 25.0% 22.0% 20.0%
Units
24.9%
15.0% 10.0% 5.0% 0.0%
12.9%
4.4% 1.4% du'v' 0.001) 0.1% 0.0%
Color drift over temperature Data obtain from units. Color point 9000K VDDD VDDA 2.6V. System consists ADJD-J823 LEDs with color coordinates, (x,y) (0.691, 0.309), Green (x,y) (0.161, 0.704), Blue (x,y) (0.131, 0.073). R:G:B luminance ratio
Color drift 0.009 0.008 0.007 0.006
du'v'
0.005 0.004 0.003 0.002 0.001 System temperature (°C)
Note: starting point 25oC zero color drift measurements made relative starting point 25oC.
Calculating Sampling Frequency Output Frequency sampling frequency, fSAMP, which frequency which ADJD-J823 samples tricolor photosensor, related system clock frequency, fCLK. output frequency, fPWM, also related fCLK. Calculation example:
fCLK (nominal) fCLK fSAMP 108Hz(nominal) SAMPFREQ fPWM fCLK (PWMFREQ 4096 6.35kHz(nominal)
SAMPFREQ Sampling frequency register setting concatenation registers [0x06][0x07] PWMFREQ frequency register setting register [0x05] internal oscillator frequency varies from part-to-part will vary significantly during operation.
Serial Interface Reference Description programming interface ADJD-J823 2-wire serial bus. consists serial clock (SCL) serial data (SDA) line. line bi-directional ADJD-J823 must connected through pull-up resistor positive power supply. When free, both lines HIGH. 2-wire serial ADJD-J823 requires device master while other devices must slaves. master device that initiates data transfer bus, generates clock signal terminates data transfer while device addressed master called slave. Slaves identified unique device addresses. Both master slave transmitter receiver master controls direction data transfer. transmitter device that sends data receiver device that receives data from bus. ADJD-J823 serial interface always operates slave transceiver with data transfer rate 100kbit/s. START/STOP Condition master initiates terminates serial data transfers. begin serial data transfer, master must send unique signal called START condition. This defined HIGH transition line while HIGH. master terminates serial data transfer sending another unique signal called STOP condition. This defined HIGH transition line while HIGH. considered busy after START condition. will considered free certain time after STOP condition. stays busy repeated START (Sr) sent instead STOP condition. START repeated START conditions functionally identical.
START condition STOP condition
Figure START/STOP Condition
Data Transfer master initiates data transfer after START condition. Data transferred bits with master generating clock pulse each sent. data valid, data line must stable during HIGH period clock line. Only during period clock line data line change state either HIGH LOW.
Data valid Figure Data Transfer Data change
clock line synchronizes serial data transmission data line. always generated master. frequency clock line vary throughout transmission long still meets minimum timing requirements. master default drives data line. slave drives data line only when sending acknowledge after master writes data slave when master requests slave send data. data line driven master implemented negative edge clock line. master sample data driven slave positive edge clock line. Figure shows example master implementation clock line data line synchronized.
data sampled positive edge
data driven negative edge
Figure Data Synchronization
complete data transfer 8-bits long 1-byte. Each byte sent most significant (MSB) first followed acknowledge acknowledge bit. Each data transfer send unlimited number bytes (depending data format).
START repeated START condition
STOP repeated START condition
Figure Data Byte Transfer
Acknowledge/Not acknowledge receiver must always acknowledge each byte sent data transfer. case slavereceiver master-transmitter, slave-receiver does send acknowledge bit, master-transmitter either STOP transfer generate repeated START start transfer.
pulled receiver (SLAVE-RECEIVER) Acknowledge
(MASTER-TRANSMITTER)
left HIGH transmitter
(MASTER)
Acknowledge clock pulse
Figure Slave-Receiver Acknowledge
case master-receiver slave-transmitter, master generates acknowledge signal data transfer slave-transmitter. master then send STOP repeated START condition begin data transfer. cases, master generates acknowledge acknowledge clock pulse.
(SLAVE-TRANSMITTER)
left HIGH transmitter
(MASTER-RECEIVER)
left HIGH receiver
acknowledge Acknowledge clock pulse
(MASTER)
Figure Master-Receiver Acknowledge
STOP repeated START condition
Addressing Each slave device serial needs have unique address. This first byte that sent master-transmitter after START condition. address defined first seven bits first byte. eighth least significant (LSB) determines direction data transfer. `one' first byte indicates that master will read data from addressed slave (master-receiver slave-transmitter). `zero' this position indicates that master will write data addressed slave (master-transmitter slave-receiver). device whose address matches address sent master will respond with acknowledge first byte itself slave-transmitter slave-receiver depending first byte. slave address ADJD-J823 0x58 (7-bits).
Slave address
Figure Slave Addressing
Data format ADJD-J823 uses register-based programming architecture. Each register unique address controls specific function inside chip. write register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then writes register data. Once slave acknowledges, master generates STOP condition data transfer.
Start condition Master will write data Stop condition
Master sends slave address
Master writes register address
Master writes register data
Slave acknowledge
Figure Register Byte Write Protocol
Slave acknowledge
Slave acknowledge
read from register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then generates repeated START condition resends slave address sent previously. least significant (LSB) slave address must indicate that master wants read from slave. addressed device will then acknowledge master. master reads register data sent slave sends acknowledge signal stop reading. master then generates STOP condition data transfer.
Repeated start condition
Start condition
Master will write data
Master will read data
Stop condition
Master sends slave address Master writes register address Slave acknowledge
Figure Register Byte Read Protocol
Master sends slave address Slave acknowledge
Master reads register data Master acknowledge
Slave acknowledge
Application Diagrams
CLKIO Float Float DRIVER PWMR PWMG HOST SYSTEM XRST SLEEP Connect pull-up resistor XRST SERIAL SLEEP SDASLV SCLSLV SDAPROM SCLPROM Connect pull-up resistor EEPROM PWMB ENABLE_RED ENABLE_GREEN ENABLE_BLUE
AVDD
AGND
DGND
DVDD
Voltage Regulator
Voltage Regulator
Star-connected ground
Recommended Reflow Profile recommended that Henkel Pb-free solder paste LF310 used soldering ADJD-J823. Below recommended soldering profile.
°C/sec 218°C/sec Delta -flux 2°C/sec Delta -cooling 2°C/sec
-peak -reflow
-max
160°C
TEMPERATURE
-min
120°C
Delta -ramp 1°C/sec
-pre 40-60 TIME
-peak
Lead Recommended Land Design IPC-SM-782 used standard land design. Recommended finishing OSP.
3.19
3.19
Lead Recommended Stencil Design stencil thickness 2.18mm mils) this package recommended
2.18mm
Recommendations Handling Storage ADJD-J823 Before Opening (Moisture Barrier Bag) sensor component must kept sealed (Moisture Barrier Bag) stored 30°C 70%RH less times. should also seal with moisture absorbent material (Silica Gel) indicator card (Cobalt Chloride) indicate moisture within bag. After Opening (Moisture Barrier Bag) sensor component must kept 30°C 60%RH less sensor component should have (Manufacturing Exposure Time) hours starting from time removal from soldering oven. unused sensor component remain, recommended store them back MBB. indicator card turned from blue pink exceeded recommended (Manufacturing Exposure Time) 24hrs, baking treatment should performed using following conditions before continue reflow soldering. Baking treatment: hours 125°C.
Package Tape Reel Dimensions Carrier Tape Dimensions
Reel Dimensions
www.agilent.com/ semiconductors
product information complete list distributors, please site. technical assistance call: Americas/Canada: (800) 235-0312 (916) 788-6763 Europe: 6441 92460 China: 10800 0017 Hong Kong: (+65) 6756 2394 India, Australia, Zealand: (+65) 6755 1939 Japan: (+81 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject change. Copyright 2005 Agilent Technologies, Inc. December 2005 5989-4059EN
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