8-bit Microcontroller with Bytes In-System Programmable Flash ATmega32
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8-bit Microcontroller with Bytes In-System Programmable Flash ATmega323 ATmega323L Summary
recommended designs. ATmega32.
1457GS-AVR-09/03
Note: This summary document. complete document available site www.atmel.com.
Configurations
PDIP
(XCK/T0) (T1) (INT2/AIN0) (OC0/AIN1) (SS) (MOSI) (MISO) (SCK) RESET XTAL2 XTAL1 (RXD) (TXD) (INT0) (INT1) (OC1B) (OC1A) (ICP) (ADC0) (ADC1) (ADC2) (ADC3) (ADC4) (ADC5) (ADC6) (ADC7) AREF AGND AVCC (TOSC2) (TOSC1) (TDI) (TDO) (TMS) (TCK) (SDA) (SCL) (OC2)
TQFP
(SS) (AIN1/OC0) ((AIN0/INT2) (T1) (XCK/T0) (ADC0) (ADC1) (ADC2) (ADC3)
(MOSI) (MISO) (SCK) RESET XTAL2 XTAL1 (RXD) (TXD) (INT0)
(ADC4) (ADC5) (ADC6) (ADC7) AREF AGND AVCC (TOSC2) (TOSC1) (TDI) (TDO)
ATmega323(L)
1457GS-AVR-09/03
(INT1) (OC1B) (OC1A) (ICP) (OC2) (SCL) (SDA) (TCK) (TMS)
ATmega323(L)
Overview
ATmega323 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega323 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed. Figure Block Diagram
Block Diagram
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC
8-BIT DATA
AVCC JTAG INTERFACE 2-WIRE SERIAL INTERFACE
ANALOG
AGND AREF
OSCILLATOR
XTAL1
INTERNAL REFERENCE
INTERNAL OSCILLATOR
OSCILLATOR
PROGRAM COUNTER
STACK POINTER
WATCHDOG TIMER
TIMING CONTROL
XTAL2 RESET
PROGRAM FLASH
SRAM
CONTROL REGISTER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
INTERNAL CALIBRATED OSCILLATOR
PROGRAMMING LOGIC
USART
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTB DRIVERS
PORTD DRIVERS
1457GS-AVR-09/03
core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega323 provides following features: bytes In-System Programmable Flash, bytes EEPROM, bytes SRAM, general purpose lines, general purpose working registers, JTAG interface Boundary-Scan, On-chip Debugging support programming, three flexible Timer/Counters with compare modes, internal external interrupts, serial programmable USART, byte oriented Two-wire Serial Interface, 8-channel, 10-bit ADC, programmable Watchdog Timer with internal Oscillator, serial port, software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counters, port, interrupt system continue functioning. Power-down mode saves register contents freezes Oscillator, disabling other chip functions until next interrupt Hardware Reset. Power-save mode, asynchronous timer continues run, allowing user maintain timer base while rest device sleeping. Noise Reduction mode stops modules except asynchronous timer ADC, minimize switching noise during conversions. Standby mode, crystal/resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with low-power consumption. Extended Standby mode, both main Oscillator asynchronous timer continue run. device manufactured using Atmel's high-density non-volatile memory technology. On-chip Flash allows Program memory re-programmed In-System through serial interface, conventional non-volatile memory programmer, On-chip Boot Program running core. Boot Program interface download application program Application Flash memory. combining 8-bit RISC with In-System Programmable Flash monolithic chip, Atmel ATmega323 powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATmega323 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, evaluation kits.
Descriptions
Port (PA7.PA0) Digital supply voltage. Digital ground. Port serves analog inputs Converter. Port also serves 8-bit bi-directional port, Converter used. Port pins provide internal pull-up resistors (selected each bit). Port output buffers sink drive displays directly. When pins used inputs externally pulled low, they will source current internal pullup resistors activated. Port pins tri-stated when reset condition becomes active, even clock running.
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega323 listed page 139. Port (PC7.PC0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions JTAG interface other special features ATmega323 listed page 146. JTAG interface enabled, pull-up resistors pins (TDI), (TMS) (TCK) will activated even Reset occurs. Port (PD7.PD0) Port 8-bit bidirectional port with internal pull-up resistors (selected each bit). Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega323 listed page 151. RESET Reset input. level this more than will generate Reset, even clock running. Shorter pulses guaranteed generate Reset. Input inverting Oscillator amplifier input internal clock operating circuit. Output from inverting Oscillator amplifier. AVCC supply voltage Port Converter. should externally connected VCC, even used. used, should connected through low-pass filter. page details operation ADC. AREF analog reference Converter. operations, voltage range 2.56V AVCC applied this pin. Analog ground. board separate analog ground plane, this should connected this ground plane. Otherwise, connect GND.
XTAL1 XTAL2 AVCC
AREF
AGND
1457GS-AVR-09/03
Register Summary
Address
($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($42) ($41) ($40) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($34) ($33) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2B) ($2A) ($29) ($28) ($27) ($26) ($25) ($24) ($23) ($22)
Name
SREG OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCRD SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UCSRA UCSRB UBRRL ACSR ADMUX ADCSR ADCH ADCL TWDR TWAR
INT1 INTF1 OCIE2 OCF2 TWINT FOC0
INT0 INTF0 TOIE2 TOV2 TWEA ISC2 PWM0
INT2 INTF2 TICIE1 ICF1 TWSTA COM01
OCIE1A OCF1A ASRE TWSTO JTRF COM00
SP11 OCIE1B OCF1B BLBSET TWWC ISC11 WDRF CTC0
SP10 TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
IVSEL OCIE0 OCF0 PGERS ISC01 EXTRF CS01
IVCE TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
Page
page page page page page page page page page page page page page page page page
Timer/Counter0 Output Compare Register
Timer/Counter0 Bits) Oscillator Calibration Register On-chip Debug Register COM1A1 ICNC1 COM1A0 ICES1 COM1B1 COM1B0 ACME FOC1A CTC1 FOC1B CS12 PSR2 PWM11 CS11 PSR10 PWM10 CS10
page page page page page page page page page page page
Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 Timer/Counter2 Bits) Timer/Counter2 Output Compare Register URSEL URSEL EEAR7 PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXCIE REFS1 ADEN UMSEL EEAR6 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL TXCIE ACBG REFS0 ADSC UPM1 EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ADLAR ADFR WDTOE UPM0 EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR RXEN MUX4 ADIF USBS EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL TXEN ACIE MUX3 ADIE EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA UCSZ2 ACIC MUX2 ADPS2 TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 EEAR9 EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 MUX1 ADPS1 UCPOL EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 TCR2UB WDP0
page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page page
EEPROM Data Register
Data Register
USART Data Register
USART Baud Rate Register Byte
Data Register High Byte Data Register Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
page
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Address
($21) ($20)
Name
TWSR TWBR
TWS7
TWS6
TWS5
TWS4
TWS3
Page
page page
Two-wire Serial Interface Rate Register
Notes:
When OCDEN Fuse unprogrammed, OSCCAL Register always accessed this address. Refer debugger specific documentation details OCDR Register. Refer USART description details access UBRRH UCSRC. compatibility with future devices, reserved bits should written zero accessed. Reserved Memory addresses should never written. Some Status Flags cleared writing logical them. Note that instructions will operate bits Register, writing back into flag read set, thus clearing flag. instructions work with registers only.
1457GS-AVR-09/03
Instruction Summary
Mnemonics
ADIW SUBI SBCI SBIW ANDI MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL CALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K
Operands
Rdl,K Rdl,K Rd,K Rd,K
Description
Registers with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump Direct Jump Relative Subroutine Call Indirect Call Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared
Operation
Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl ($FF R1:R0 R1:R0 R1:R0
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS
R1:R0 R1:R0
Stack Stack (Rr(b)=0) (Rr(b)=1) (P(b)=0) (P(b)=1) (SREG(s) then PCPC+k (SREG(s) then PCPC+k then then then then then then then then then then then then then then then then
R1:R0
BRANCH INSTRUCTIONS
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Mnemonics
BRIE BRID MOVW PUSH SWAP BSET BCLR
Operands
Rd,Y+q Y+q,Rr Z+q,Rr
Description
Branch Interrupt Enabled Branch Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Load Program Memory Post-Inc Store Program Memory Port Port Push Register Stack Register from Stack Register Clear Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG
Operation
then then Rd+1:Rd Rr+1:Rr (X), (Y), (Z), (Z), R1:R0 Stack Stack I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0.6 Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None
#Clocks
DATA TRANSFER INSTRUCTIONS
BIT-TEST INSTRUCTIONS
1457GS-AVR-09/03
Mnemonics
SLEEP BREAK
Operands
Description
Clear Half Carry Flag SREG Operation Sleep Watchdog Reset Break
Operation
(see specific descr. Sleep function) (see specific descr. WDR/timer) On-chip Debug Only
Flags
None None None None
#Clocks
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Ordering Information
Speed (MHz) Power Supply 5.5V Ordering Code ATmega323L-4AC ATmega323L-4PC ATmega323L-4AI ATmega323L-4PI 5.5V ATmega323-8AC ATmega323-8PC ATmega323-8AI ATmega323-8PI Package 40P6 40P6 40P6 40P6 Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type 40P6 44-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
1457GS-AVR-09/03
Packaging Information
Marked Pin#
SEATING PLANE
VIEW
Corner
SIDE VIEW
COMMON DIMENSIONS (Unit Measure
SYMBOL
0.80
0.90 0.02 0.25
1.00 0.05
NOTE
0.18
0.23 7.00
0.30
BOTTOM VIEW
5.00
5.20 7.00
5.40
5.00
5.20 0.50
5.40
Notes: JEDEC Standard MO-220, Fig. (SAW Singulation) VKKD-1.
0.35
0.55
0.75
01/15/03 TITLE 2325 Orchard Parkway 44M1, 44-pad, Body, Lead Pitch 0.50 Jose, 95131 Micro Lead Frame Package (MLF) DRAWING REV. 44M1
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
40P6
SEATING PLANE
SYMBOL
COMMON DIMENSIONS (Unit Measure 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 2.540 4.826 52.578 Note 15.875 13.970 Note 0.559 1.651 3.556 0.381 17.526 NOTE
Notes:
This package conforms JEDEC reference MS-011, Variation Dimensions include mold Flash Protrusion. Mold Flash Protrusion shall exceed 0.25 (0.010").
09/28/01 2325 Orchard Parkway Jose, 95131 TITLE 40P6, 40-lead (0.600"/15.24 Wide) Plastic Dual Inline Package (PDIP) DRAWING REV. 40P6
1457GS-AVR-09/03
Errata ATmega323 Rev.
Interrupts Abort Power-down Master Does Accept Spikes Lines TWCR Write Operations Ignored when Immediately Repeated Phase Correct Speed Limited Slave Mode Problems with UBRR Settings Missing OverRun Flag Fake Frame Error USART
Interrupts Abort Power-down Power-down operation wake other interrupts. interrupt (e.g., INT0) occurs during Power-down address watch wakes CPU, aborts operation returns idle state. interrupt occurs middle Power-down Address Match (i.e., during reading slave address), received address will lost Slave will return ACN. Problem Fix/Workaround Ensure that Address Match only enabled interrupt when entering Power-down. Master handle this resending request NACH received. Master Does Accept Spikes Lines When part operates Master, idle (SDA generating short spike (SDA short interval), interrupt generated, status code still (idle). when software initiates start condition clears TWINT, nothing happens SCL, TWINT never again. Problem Fix/Workaround Either following: Ensure spikes occur lines. Generate valid START condition followed STOP condition bus. This provokes error reported interrupt with status code $00. Single-master system, user should write TWSTO immediately before writing TWSTA bit. TWCR Write Operation Ignored when Immediately Repeated Repeated write TWCR must delayed. write operation TWCR immediately followed another write operation TWCR, first write operation ignored. Problem Fix/Workaround Ensure least instruction (e.g., NOP) executed between writes TWCR. Phase Correct phase-correct mode, change from OCRx anything less than does change output. This gives phase error following period. Problem Fix/Workaround Make sure this issue harmful application.
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Speed Limited Slave Mode When Two-wire Serial Interface operates Slave mode, frames undetected frequency less than times frequency. Problem Fix/Workaround Ensure that frequency least times frequency. Problems with UBRR Settings baud rate corresponding previous UBRR setting used first transmitted/received when either UBRRH UBRRL written. This will disturb communication UBRR changed from very high very baud rate setting, internal baud rate counter will have count down zero before using setting. addition, writing UBRRL incorrectly clears UBRRH setting. Problem Fix/Workaround UBRRH must written after UBRRL because setting UBRRL clears UBRRH. doing additional dummy write UBRRH, baud rate correctly. following example UBRR. UBRRH updated first upward compatibility with corrected devices.
r17, HIGH(baud) r16, LOW(baud) UBRRH, UBRRL, UBRRH, UBRRH, Added upward compatibility UBRRL, UBRRH incorrectly cleared UBRRH Loads baud rate counter with (correct) value
Missing OverRun Flag Fake Frame Error USART When USART received three characters without them been read, USART FIFO full. USART detects start fourth character, Data OverRun (DOR) Flag will third character. However, read from USART Data Register performed just after start fourth byte received, Frame Error generated character three. USART Data Register read between reception first data fourth character, Data OverRun Flag character three will lost. Problem Fix/Workaround user should design application never completely fill USART FIFO. this possible, user must high-level protocol able detect characters were lost request retransmission this happens. following errata ATmega323, revisions. However, proposal solving problems regarding JTAG instruction IDCODE presented below. IDCODE masks data from input public optional JTAG instruction IDCODE implemented correctly according IEEE1149.1; logic scanned into shift register instead input while shifting Device Register. Hence, captured data from preceding devices boundary scan chain lost replaced all-ones, data succeeding devices replaced all-ones during Update-DR. ATmega323 only device scan chain, problem visible.
1457GS-AVR-09/03
Problem Workaround Select Device Register ATmega323 (Either issuing IDCODE instruction entering Test-Logic-Reset state controller) read contents Device Register possibly data from succeeding devices scan chain. Note that data succeeding devices cannot entered during this scan, data preceding devices can. Issue BYPASS instruction ATmega323 select Bypass Register while reading Device Registers preceding devices boundary scan chain. Never read data from succeeding devices boundary scan chain upload data succeeding devices while Device Register selected ATmega323. Note that IDCODE instruction default instruction selected Test-Logic-Reset state TAP-controller. Alternative Problem Workaround Device devices boundary scan chain must captured simultaneously (for instance blind interrogation used), boundary scan chain connected such that ATmega323 fist device chain. Update-DR will still work succeeding devices boundary scan chain long IDCODE present JTAG Instruction Register, Device registered cannot uploaded case.
ATmega323(L)
1457GS-AVR-09/03
ATmega323(L)
Datasheet Change ATmega323
Changes from Rev. 1457F 09/02 Rev. 1457G 09/03
This document contains changes made datasheet ATmega323.
Removed "Preliminary" from Updated "The Test Access Port TAP" page regarding JTAGEN. Updated description page Added extra information regarding JTAGEN interface "Fuse Bits" page 187. Updated some values "Electrical Characteristics" page 213. Added proposal solving problems regarding JTAG instruction IDCODE "Errata ATmega323 Rev. page
Changes from Rev. 1457E 11/01 Rev. 1457F 09/02
Added watermark: "Not recommended designs. ATmega32". Added "Errata ATmega323 Rev. page
1457GS-AVR-09/03
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1457GS-AVR-09/03
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