8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATm

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8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATm

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8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega128 ATmega128L Summary
Rev. 2467LS-AVR-05/04
Note: This summary document. complete document available site www.atmel.com.
Configurations
Figure Pinout ATmega128
AVCC AREF (ADC0) (ADC1) (ADC2) (ADC3) (ADC4/TCK) (ADC5/TMS) (ADC6/TDO) (ADC7/TDI) (AD0) (AD1) (AD2)
Overview
ATmega128 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega128 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed.
ATmega128
2467LS-AVR-05/04
(OC2/OC1C) TOSC2/PG3 TOSC1/1PG4 RESET XTAL2 XTAL1 (SCL/INT0) (SDA/INT1) (RXD1/INT2) (TXD1/INT3) (ICP1) (XCK1) (T1) (T2)
RXD0/(PDI) (TXD0/PDO) (XCK0/AIN0) (OC3A/AIN1) (OC3B/INT4) (OC3C/INT5) (T3/INT6) (ICP3/INT7) (SS) (SCK) (MOSI) (MISO) (OC0) (OC1A) (OC1B)
(AD3) (AD4) (AD5) (AD6) (AD7) PG2(ALE) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) PG1(RD) PG0(WR)
ATmega128
Block Diagram
Figure Block Diagram
PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS
DATA REGISTER PORTF
DATA DIR. REG. PORTF
DATA REGISTER PORTA
DATA DIR. REG. PORTA
DATA REGISTER PORTC
DATA DIR. REG. PORTC
8-BIT DATA
AVCC AGND AREF PROGRAM COUNTER STACK POINTER WATCHDOG TIMER INTERNAL OSCILLATOR
CALIB.
OSCILLATOR JTAG
OSCILLATOR
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
CONTROL REGISTER
TIMING CONTROL
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
USART0
USART1
TWO-WIRE SERIAL INTERFACE
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. PORTG
DATA DIR. REG. PORTG
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
RESET
XTAL1
XTAL2
2467LS-AVR-05/04
core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega128 provides following features: 128K bytes In-System Programmable Flash with Read-While-Write capabilities, bytes EEPROM, bytes SRAM, general purpose lines, general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes PWM, USARTs, byte oriented Two-wire Serial Interface, 8-channel, 10-bit with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, serial port, IEEE std. 1149.1 compliant JTAG test interface, also used accessing On-chip Debug system programming software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counters, port, interrupt system continue functioning. Powerdown mode saves register contents freezes Oscillator, disabling other chip functions until next interrupt Hardware Reset. Power-save mode, asynchronous timer continues run, allowing user maintain timer base while rest device sleeping. Noise Reduction mode stops modules except Asynchronous Timer ADC, minimize switching noise during conversions. Standby mode, Crystal/Resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with power consumption. Extended Standby mode, both main Oscillator Asynchronous Timer continue run. device manufactured using Atmel's high-density nonvolatile memory technology. On-chip Flash allows program memory reprogrammed in-system through serial interface, conventional nonvolatile memory programmer, On-chip Boot program running core. boot program interface download application program application Flash memory. Software Boot Flash section will continue while Application Flash section updated, providing true Read-While-Write operation. combining 8-bit RISC with In-System Self-Programmable Flash monolithic chip, Atmel ATmega128 powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATmega128 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, in-circuit emulators, evaluation kits.
ATmega103 ATmega128 Compatibility
ATmega128 highly complex microcontroller where number locations supersedes locations reserved instruction set. ensure backward compatibility with ATmega103, locations present ATmega103 have same location ATmega128. Most additional locations added Extended space starting from $FF, (i.e., ATmega103 internal space). These locations reached using LD/LDS/LDD ST/STS/STD instructions only, using instructions. relocation internal space still problem ATmega103 users. Also, increased number interrupt vectors might problem code uses absolute addresses. solve these problems, ATmega103 compatibility mode selected programming fuse M103C. this mode, none functions Extended space use, internal located ATmega103. Also, Extended Interrupt vectors removed.
ATmega128
2467LS-AVR-05/04
ATmega128
ATmega128 100% compatible with ATmega103, replace ATmega103 current Printed Circuit Boards. application note "Replacing ATmega103 ATmega128" describes what user should aware replacing ATmega103 ATmega128. ATmega103 Compatibility Mode programming M103C fuse, ATmega128 will compatible with ATmega103 regards RAM, pins interrupt vectors described above. However, some features ATmega128 available this compatibility mode, these features listed below: USART instead two, Asynchronous mode only. Only eight least significant bits Baud Rate Register available. bits Timer/Counter with compare registers instead 16-bit Timer/Counters with three compare registers. Two-wire serial interface supported. Port output only. Port serves alternate functions only (not general port). Port serves digital input only addition analog input ADC. Boot Loader capabilities supported. possible adjust frequency internal calibrated Oscillator. External Memory Interface release Address pins general I/O, neither configure different wait-states different External Memory Address sections.
addition, there some other minor differences make more compatible ATmega103: Only EXTRF PORF exists MCUCSR. Timed sequence required Watchdog Time-out change. External Interrupt pins serve level interrupt only. USART FIFO buffer, data overrun comes earlier.
Unused bits ATmega103 should written ensure same operation ATmega128.
Descriptions
Port (PA7.PA0) Digital supply voltage. Ground. Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega128 listed page Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source
2467LS-AVR-05/04
current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega128 listed page Port (PC7.PC0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions special features ATmega128 listed page ATmega103 compatibility mode, Port output only, port pins tri-stated when reset condition becomes active. Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega128 listed page Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega128 listed page Port (PF7.PF0) Port serves analog inputs Converter. Port also serves 8-bit bi-directional port, Converter used. Port pins provide internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. JTAG interface enabled, pull-up resistors pins PF7(TDI), PF5(TMS), PF4(TCK) will activated even Reset occurs. tri-stated unless states that shift data entered. Port also serves functions JTAG interface. ATmega103 compatibility mode, Port input Port only. Port (PG4.PG0) Port 5-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features.
ATmega128
2467LS-AVR-05/04
ATmega128
port pins tri-stated when reset condition becomes active, even clock running. ATmega103 compatibility mode, these pins only serves strobes signals external memory well input Oscillator, pins initialized asynchronously when reset condition becomes active, even clock running. oscillator pins. RESET Reset input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given Table page Shorter pulses guaranteed generate reset. Input inverting Oscillator amplifier input internal clock operating circuit. Output from inverting Oscillator amplifier. AVCC supply voltage Port Converter. should externally connected VCC, even used. used, should connected through low-pass filter. AREF analog reference Converter. programming enable Serial Programming mode. holding this during Power-on Reset, device will enter Serial Programming mode. function during normal operation.
XTAL1 XTAL2 AVCC
AREF
2467LS-AVR-05/04
Register Summary
Address
($FF) ($9E) ($9D) ($9C) ($9B) ($9A) ($99) ($98) ($97) ($96) ($95) ($94) ($93) ($92) ($91) ($90) ($8F) ($8E) ($8D) ($8C) ($8B) ($8A) ($89) ($88) ($87) ($86) ($85) ($84) ($83) ($82) ($81) ($80) ($7F) ($7E) ($7D) ($7C) ($7B) ($7A) ($79) ($78) ($77) ($76) ($75) ($74) ($73) ($72) ($71) ($70) ($6F) ($6E) ($6D) ($6C) ($6B) ($6A) ($69) ($68) ($67) ($66) ($65) ($64) ($63) ($62)
Name
Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved Reserved Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING PORTF
RXC1 RXCIE1 FOC3A COM3A1 ICNC3
UMSEL1 TXC1 TXCIE1 UMSEL0 FOC3B COM3A0 ICES3
UPM11 UDRE1 UDRIE1 UPM01 FOC3C COM3B1
UPM10 RXEN1 UPM00 COM3B0 WGM33
USBS1 DOR1 TXEN1
UCSZ11 UPE1 UCSZ12
UCSZ10 U2X1 RXB81
UCPOL1 MPCM1 TXB81
Page
USART1 Data Register
USART1 Baud Rate Register USART1 Baud Rate Register High USBS0 COM3C1 WGM32 UCSZ01 COM3C0 CS32 UCSZ00 WGM31 CS31 UCPOL0
USART0 Baud Rate Register High WGM30 CS30
Timer/Counter3 Counter Register High Byte Timer/Counter3 Counter Register Byte Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Output Compare Register High Byte Timer/Counter3 Output Compare Register Byte Timer/Counter3 Input Capture Register High Byte Timer/Counter3 Input Capture Register Byte FOC1A FOC1B TICIE3 ICF3 FOC1C OCIE3A OCF3A OCIE3B OCF3B TOIE3 TOV3 OCIE3C OCF3C OCIE1C OCF1C
Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte TWINT TWA6 TWS7 TWEA TWA5 TWS6 TWSTA TWA4 TWS5 TWSTO TWA3 TWS4 TWWC TWA2 TWS3 TWEN TWA1 TWA0 TWPS1 TWIE TWGCE TWPS0
Two-wire Serial Interface Data Register
Two-wire Serial Interface Rate Register Oscillator Calibration Register XMBK ISC31 SPMIE PORTF7 SRL2 ISC30 RWWSB PORTF6 SRL1 ISC21 PORTF5 SRL0 ISC20 RWWSRE PORTG4 DDG4 PING4 PORTF4 SRW01 ISC11 BLBSET PORTG3 DDG3 PING3 PORTF3 SRW00 XMM2 ISC10 PGWRT PORTG2 DDG2 PING2 PORTF2 SRW11 XMM1 ISC01 PGERS PORTG1 DDG1 PING1 PORTF1 XMM0 ISC00 SPMEN PORTG0 DDG0 PING0 PORTF0
ATmega128
2467LS-AVR-05/04
ATmega128
Register Summary (Continued)
Address
($61) ($60) ($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($42) ($41) ($40) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($34) ($33) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2B) ($2A) ($29) ($28) ($27) ($26) ($25) ($24) ($23) ($22)
Name
DDRF Reserved SREG XDIV RAMPZ EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE
DDF7 SP15 XDIVEN ISC71 INT7 INTF7 OCIE2 OCF2 FOC0
DDF6 SP14 XDIV6 ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 WGM00
DDF5 SP13 XDIV5 ISC61 INT5 INTF5 TICIE1 ICF1 COM01
DDF4 SP12 XDIV4 ISC60 INT4 INTF4 OCIE1A OCF1A JTRF COM00
DDF3 SP11 XDIV3 ISC51 INT3 INTF3 OCIE1B OCF1B WDRF WGM01
DDF2 SP10 XDIV2 ISC50 INT2 INTF TOIE1 TOV1 BORF CS02
DDF1 XDIV1 ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01
DDF0 XDIV0 RAMPZ0 ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00
Page
106, 138, 106, 139,
Timer/Counter0 Bit) Timer/Counter0 Output Compare Register COM1A1 ICNC1 COM1A0 ICES1 COM1B1 COM1B0 WGM13 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10
Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 Bit) Timer/Counter2 Output Compare Register
IDRD/OCDR7
OCDR6
OCDR5
OCDR4 WDCE
OCDR3 ACME
OCDR2 WDP2
OCDR1 WDP1 PSR0
OCDR0 WDP0 PSR321
107, 143,
EEPROM Address Register High
EEPROM Address Register Byte EEPROM Data Register PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 REFS1 ADEN PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL TXC0 TXCIE0 ACBG REFS0 ADSC PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE0 UDRIE0 ADLAR ADFR PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR RXEN0 MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL DOR0 TXEN0 ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0
Data Register
USART0 Data Register
USART0 Baud Rate Register
Data Register High Byte Data Register byte PORTE7 DDE7 PORTE6 DDE6 PORTE5 DDE5 PORTE4 DDE4 PORTE3 DDE3 PORTE2 DDE2 PORTE1 DDE1 PORTE0 DDE0
2467LS-AVR-05/04
Register Summary (Continued)
Address
($21) ($20)
Name
PINE PINF
PINE7 PINF7
PINE6 PINF6
PINE5 PINF5
PINE4 PINF4
PINE3 PINF3
PINE2 PINF2
PINE1 PINF1
PINE0 PINF0
Page
Notes:
compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Some status flags cleared writing logical them. Note that instructions will operate bits register, writing back into flag read set, thus clearing flag. instructions work with registers only.
ATmega128
2467LS-AVR-05/04
ATmega128
Instruction Summary
Mnemonics
ADIW SUBI SBCI SBIW ANDI MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL CALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K
Operands
Rdl,K Rdl,K Rd,K Rd,K
Description
Registers with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump Direct Jump Relative Subroutine Call Indirect Call Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared
Operation
Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl ($FF R1:R0 R1:R0 R1:R0
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS
R1:R0 R1:R0
STACK STACK (Rr(b)=0) (Rr(b)=1) (P(b)=0) (P(b)=1) (SREG(s) then PCPC+k (SREG(s) then PCPC+k then then then then then then then then then then then then then then then then
R1:R0
BRANCH INSTRUCTIONS
2467LS-AVR-05/04
Instruction Summary (Continued)
Mnemonics
BRIE BRID MOVW ELPM ELPM ELPM PUSH SWAP BSET BCLR
Operands
Rd,Y+q Y+q,Rr Z+q,Rr
Description
Branch Interrupt Enabled Branch Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Load Program Memory Post-Inc Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory Post-Inc Store Program Memory Port Port Push Register Stack Register from Stack Register Clear Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag
Operation
then then Rd+1:Rd Rr+1:Rr (X), (Y), (Z), (Z), (RAMPZ:Z) (RAMPZ:Z) (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 R1:R0 STACK STACK I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0.6 Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None
#Clocks
DATA TRANSFER INSTRUCTIONS
BIT-TEST INSTRUCTIONS
ATmega128
2467LS-AVR-05/04
ATmega128
Instruction Summary (Continued)
Mnemonics
CONTROL INSTRUCTIONS SLEEP BREAK Operation Sleep Watchdog Reset Break (see specific descr. Sleep function) (see specific descr. WDR/timer) On-chip Debug Only None None None None
Operands
Description
Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG Clear Half Carry Flag SREG
Operation
Flags
#Clocks
2467LS-AVR-05/04
Ordering Information
Speed (MHz) Power Supply Ordering Code ATmega128L-8AC ATmega128L-8MC 5.5V ATmega128L-8AI ATmega128L-8AJ(2) ATmega128L-8MI ATmega128L-8MJ(2) ATmega128-16AC ATmega128-16MC 5.5V ATmega128-16AI ATmega128-16AJ(2) ATmega128-16MI ATmega128-16MJ(2) Package(1) 64M1 64M1 64M1 64M1 64M1 64M1 Operation Range Commercial (0oC 70oC) Industrial (-40oC 85oC) Commercial (0oC 70oC) Industrial (-40oC 85oC)
Notes:
device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free alternative.
Package Type 64M1 64-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, body, lead pitch 0.50 Micro Lead Frame Package (MLF)
ATmega128
2467LS-AVR-05/04
ATmega128
Packaging Information
IDENTIFIER
0°~7°
COMMON DIMENSIONS (Unit Measure SYMBOL 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 1.00 16.00 14.00 16.00 14.00 0.80 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note Note NOTE
Notes:
This package conforms JEDEC reference MS-026, Variation AEB. Dimensions include mold protrusion. Allowable protrusion 0.25 side. Dimensions maximum plastic body size dimensions including mold mismatch. Lead coplanarity 0.10 maximum.
10/5/2001 2325 Orchard Parkway Jose, 95131 TITLE 64A, 64-lead, Body Size, Body Thickness, Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING REV.
2467LS-AVR-05/04
64M1
Marked Pin#
VIEW
SEATING PLANE
0.08
Corner
SIDE VIEW
COMMON DIMENSIONS (Unit Measure SYMBOL 5.20 0.80 0.23 0.90 0.02 0.25 9.00 5.40 9.00 5.20 5.40 0.50 0.35 0.40 0.45 5.60 5.60 1.00 0.05 0.28 NOTE
BOTTOM VIEW
Notes: JEDEC Standard MO-220, Fig. VMMD.
01/15/03 2325 Orchard Parkway Jose, 95131 TITLE 64M1, 64-pad, Body, Lead Pitch 0.50 Micro Lead Frame Package (MLF) DRAWING 64M1 REV.
ATmega128
2467LS-AVR-05/04
ATmega128
Errata
ATmega128 Rev.
revision letter this section refers revision ATmega128 device. Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register Stabilizing time needed when changing XDIV Register After increasing source clock frequency more than with settings XDIV register, device execute some subsequent instructions incorrectly. Problem Workaround instruction will always executed correctly also right after frequency change. Thus, next instructions after change should instructions. ensure this, follow this procedure: 1.Clear SREG Register. 2.Set pre-scaling factor XDIV register. 3.Execute instructions 4.Set SREG This will ensure that subsequent instructions will execute correctly. Assembly Code Example:
XDIV, temp clear global interrupt enable prescale value operation operation operation operation operation operation operation operation clear global interrupt enable
Stabilizing time needed when changing OSCCAL Register After increasing source clock frequency more than with settings OSCCAL register, device execute some subsequent instructions incorrectly. Problem Workaround behavior follows errata number same Workaround applicable this errata. proposal solving problems regarding JTAG instruction IDCODE presented below. IDCODE masks data from input public optional JTAG instruction IDCODE implemented correctly according IEEE1149.1; logic scanned into shift register instead input while shifting Device Register. Hence, captured data from preceding devices boundary scan chain lost replaced all-ones, data succeeding devices replaced all-ones during Update-DR. ATmega128 only device scan chain, problem visible.
2467LS-AVR-05/04
Problem Workaround Select Device Register ATmega128 (Either issuing IDCODE instruction entering Test-Logic-Reset state controller) read contents Device Register possibly data from succeeding devices scan chain. Note that data succeeding devices cannot entered during this scan, data preceding devices can. Issue BYPASS instruction ATmega128 select Bypass Register while reading Device Registers preceding devices boundary scan chain. Never read data from succeeding devices boundary scan chain upload data succeeding devices while Device Register selected ATmega128. Note that IDCODE instruction default instruction selected Test-Logic-Reset state TAP-controller. Alternative Problem Workaround Device devices boundary scan chain must captured simultaneously (for instance blind interrogation used), boundary scan chain connected such that ATmega128 fist device chain. Update-DR will still work succeeding devices boundary scan chain long IDCODE present JTAG Instruction Register, Device registered cannot uploaded case.
ATmega128 Rev.
Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register Stabilizing time needed when changing XDIV Register After increasing source clock frequency more than with settings XDIV register, device execute some subsequent instructions incorrectly. Problem Workaround instruction will always executed correctly also right after frequency change. Thus, next instructions after change should instructions. ensure this, follow this procedure: 1.Clear SREG Register. 2.Set pre-scaling factor XDIV register. 3.Execute instructions 4.Set SREG This will ensure that subsequent instructions will execute correctly. Assembly Code Example:
XDIV, temp clear global interrupt enable prescale value operation operation operation operation operation operation operation operation clear global interrupt enable
ATmega128
2467LS-AVR-05/04
ATmega128
Stabilizing time needed when changing OSCCAL Register After increasing source clock frequency more than with settings OSCCAL register, device execute some subsequent instructions incorrectly. Problem Workaround behavior follows errata number same Workaround applicable this errata. proposal solving problems regarding JTAG instruction IDCODE presented below. IDCODE masks data from input public optional JTAG instruction IDCODE implemented correctly according IEEE1149.1; logic scanned into shift register instead input while shifting Device Register. Hence, captured data from preceding devices boundary scan chain lost replaced all-ones, data succeeding devices replaced all-ones during Update-DR. ATmega128 only device scan chain, problem visible. Problem Workaround Select Device Register ATmega128 (Either issuing IDCODE instruction entering Test-Logic-Reset state controller) read contents Device Register possibly data from succeeding devices scan chain. Note that data succeeding devices cannot entered during this scan, data preceding devices can. Issue BYPASS instruction ATmega128 select Bypass Register while reading Device Registers preceding devices boundary scan chain. Never read data from succeeding devices boundary scan chain upload data succeeding devices while Device Register selected ATmega128. Note that IDCODE instruction default instruction selected Test-Logic-Reset state TAP-controller. Alternative Problem Workaround Device devices boundary scan chain must captured simultaneously (for instance blind interrogation used), boundary scan chain connected such that ATmega128 fist device chain. Update-DR will still work succeeding devices boundary scan chain long IDCODE present JTAG Instruction Register, Device registered cannot uploaded case.
ATmega128 Rev.
Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register Stabilizing time needed when changing XDIV Register After increasing source clock frequency more than with settings XDIV register, device execute some subsequent instructions incorrectly. Problem Workaround instruction will always executed correctly also right after frequency change. Thus, next instructions after change should instructions. ensure this, follow this procedure: 1.Clear SREG Register. 2.Set pre-scaling factor XDIV register.
2467LS-AVR-05/04
3.Execute instructions 4.Set SREG This will ensure that subsequent instructions will execute correctly. Assembly Code Example:
XDIV, temp clear global interrupt enable prescale value operation operation operation operation operation operation operation operation clear global interrupt enable
Stabilizing time needed when changing OSCCAL Register After increasing source clock frequency more than with settings OSCCAL register, device execute some subsequent instructions incorrectly. Problem Workaround behavior follows errata number same Workaround applicable this errata. proposal solving problems regarding JTAG instruction IDCODE presented below. IDCODE masks data from input public optional JTAG instruction IDCODE implemented correctly according IEEE1149.1; logic scanned into shift register instead input while shifting Device Register. Hence, captured data from preceding devices boundary scan chain lost replaced all-ones, data succeeding devices replaced all-ones during Update-DR. ATmega128 only device scan chain, problem visible. Problem Workaround Select Device Register ATmega128 (Either issuing IDCODE instruction entering Test-Logic-Reset state controller) read contents Device Register possibly data from succeeding devices scan chain. Note that data succeeding devices cannot entered during this scan, data preceding devices can. Issue BYPASS instruction ATmega128 select Bypass Register while reading Device Registers preceding devices boundary scan chain. Never read data from succeeding devices boundary scan chain upload data succeeding devices while Device Register selected ATmega128. Note that IDCODE instruction default instruction selected Test-Logic-Reset state TAP-controller. Alternative Problem Workaround Device devices boundary scan chain must captured simultaneously (for instance blind interrogation used), boundary scan chain
ATmega128
2467LS-AVR-05/04
ATmega128
connected such that ATmega128 fist device chain. Update-DR will still work succeeding devices boundary scan chain long IDCODE present JTAG Instruction Register, Device registered cannot uploaded case.
ATmega128 Rev.
Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register Stabilizing time needed when changing XDIV Register After increasing source clock frequency more than with settings XDIV register, device execute some subsequent instructions incorrectly. Problem Workaround instruction will always executed correctly also right after frequency change. Thus, next instructions after change should instructions. ensure this, follow this procedure: 1.Clear SREG Register. 2.Set pre-scaling factor XDIV register. 3.Execute instructions 4.Set SREG This will ensure that subsequent instructions will execute correctly. Assembly Code Example:
XDIV, temp clear global interrupt enable prescale value operation operation operation operation operation operation operation operation clear global interrupt enable
Stabilizing time needed when changing OSCCAL Register After increasing source clock frequency more than with settings OSCCAL register, device execute some subsequent instructions incorrectly. Problem Workaround behavior follows errata number same Workaround applicable this errata. proposal solving problems regarding JTAG instruction IDCODE presented below. IDCODE masks data from input public optional JTAG instruction IDCODE implemented correctly according IEEE1149.1; logic scanned into shift register instead input while shifting Device Register. Hence, captured data from pre-
2467LS-AVR-05/04
ceding devices boundary scan chain lost replaced all-ones, data succeeding devices replaced all-ones during Update-DR. ATmega128 only device scan chain, problem visible. Problem Workaround Select Device Register ATmega128 (Either issuing IDCODE instruction entering Test-Logic-Reset state controller) read contents Device Register possibly data from succeeding devices scan chain. Note that data succeeding devices cannot entered during this scan, data preceding devices can. Issue BYPASS instruction ATmega128 select Bypass Register while reading Device Registers preceding devices boundary scan chain. Never read data from succeeding devices boundary scan chain upload data succeeding devices while Device Register selected ATmega128. Note that IDCODE instruction default instruction selected Test-Logic-Reset state TAP-controller. Alternative Problem Workaround Device devices boundary scan chain must captured simultaneously (for instance blind interrogation used), boundary scan chain connected such that ATmega128 fist device chain. Update-DR will still work succeeding devices boundary scan chain long IDCODE present JTAG Instruction Register, Device registered cannot uploaded case.
ATmega128
2467LS-AVR-05/04
ATmega128
Datasheet Change ATmega128
Changes from Rev. 2467K-03/04 Rev. 2467L-05/04
Please note that referring page numbers this section referred this document. referring revision this section referring document revision. Removed "Preliminary" "TBD" from datasheet, replaced occurrences with ICPx. Updated Table page Table page Table page Table page 243, Table page 302, Table page 306, Table page 323, Table page 325. Updated "External Memory Interface" page Updated "Device Identification Register" page 255. Updated "Electrical Characteristics" page 321. Updated "ADC Characteristics" page 327. Updated "ATmega128 Typical Characteristics" page 335. Updated "Ordering Information" page
Changes from Rev. 2467J-12/03 Rev. 2467K-03/04 Changes from Rev. 2467I-09/03 Rev. 2467J-12/03 Changes from Rev. 2467H-02/03 Rev. 2467I-09/03
Updated "Errata" page
Updated "Calibrated Internal Oscillator" page
Updated note "XTAL Divide Control Register XDIV" page Updated "JTAG Interface On-chip Debug System" page Updated values VBOT (BODLEVEL Table page Updated "Test Access Port TAP" page regarding JTAGEN. Updated description page 257. Added note regarding JTAGEN fuse Table page 290. Updated values Characteristics" page 321. Added proposal solving problems regarding JTAG instruction IDCODE "Errata" page
Changes from Rev. 2467G-09/02 Rev. 2467H-02/03
Corrected names Prescaler bits SFIOR Register. Added Chip Erase first step under "Programming Flash" page "Programming EEPROM" page 319.
2467LS-AVR-05/04
Removed reference "Multipurpose Oscillator" application note Crystal Oscillator" application note, which exist. Corrected waveforms Figure page 123. Various minor Timer1 corrections. Added information about symmetry Timer0 Timer2. Various minor corrections. Added reference Table page from both Serial Programming Self Programming inform about Flash Page size. Added note under "Filling Temporary Buffer (Page Loading)" page about writing EEPROM during Page load. Removed ADHSM completely. Added section "EEPROM Write During Power-down Sleep Mode" page Updated drawings "Packaging Information" page
Changes from Rev. 2467F-09/02 Rev. 2467G-09/02 Changes from Rev. 2467E-04/02 Rev. 2467F-09/02
Changed Endurance Flash 10,000 Write/Erase Cycles.
Added 64-pad Package updated "Ordering Information" page Added section "Using Locations External Memory Smaller than page Added section "Default Clock Source" page Renamed SPMCR SPMCSR entire document. When using external clock there some limitations regards change frequency. This descried "External Clock" page Table 131, "External Clock Drive," page 323. Added section regarding OCD-system power consumption section "Minimizing Power Consumption" page Corrected typo (WGM-bit setting) for: "Fast Mode" page (Timer/Counter0). "Phase Correct Mode" page (Timer/Counter0). "Fast Mode" page (Timer/Counter2). "Phase Correct Mode" page (Timer/Counter2). Corrected Table page (USART). Corrected Table page (Boundary-Scan)
ATmega128
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ATmega128
Updated parameter Characteristics" page 321.
Changes from Rev. 2467D-03/02 Rev. 2467E-04/02
Updated Characterization Data Section "ATmega128 Typical Characteristics" page 335. Updated following tables: Table page Table page Table page 157, Table page 261, Table page 328. Updated Description OSCCAL Calibration Byte. data sheet, explained take advantage calibration bytes Oscillator selections. This added following sections: Improved description "Oscillator Calibration Register OSCCAL" page "Calibration Byte" page 291.
Changes from Rev. 2467C-02/02 Rev. 2467D-03/02
Added more information about "ATmega103 Compatibility Mode" page Updated Table "EEPROM Programming Time," page Updated typical Start-up Time Table page Table Table page Table page Table page Table page Updated Table page with typical Time-out. Corrected description ADSC "ADC Control Status Register ADCSRA" page 245. Improved description polarity check differential results "ADC Conversion Result" page 242. Corrected JTAG version numbers "JTAG Version Numbers" page 256. Improved description addressing during (usage RAMPZ) "Addressing Flash During Self-Programming" page 280, "Performing Page Erase SPM" page 282, "Performing Page Write" page 282. Added regarding OCDEN Fuse below Table page 290. Updated Programming Figures: Figure page Figure page updated also reflect that AVCC must connected during Programming mode. Figure page added illustrate program fuses. Added note regarding usage PROG_PAGEREAD instructions page 310. PROG_PAGELOAD
Added Calibrated Oscillator characterization "ATmega128 Typical Characteristics" page 335. Updated "Two-wire Serial Interface" section.
curves
section
2467LS-AVR-05/04
More details regarding Power-down operation using master with TWBRR values added into data sheet. Added note "Bit Rate Generator Unit" page 204. Added description "Address Match Unit" page 205. Added note regarding usage Timer/Counter0 combined with clock. "XTAL Divide Control Register XDIV" page
Changes from Rev. 2467B-09/01 Rev. 2467C-02/02
Corrected Description Alternate Functions Port Corrected description TOSC1 TOSC2 "Alternate Functions Port page Added JTAG Version Numbers rev. rev. Updated Table page 256. Added Some Preliminary Test Limits Characterization Data Removed some TBD's following tables pages: Table page Table page Characteristics" page 321, Table page 323, Table page 325, Table page 328. Corrected "Ordering Information" page Added some Characterization Data Section "ATmega128 Typical Characteristics" page 335. Removed Alternative Algortihm Leaving JTAG Programming Mode. "Leaving Programming Mode" page 318. Added Description Access Extended Fuse Byte Through JTAG Programming Mode. "Programming Fuses" page "Reading Fuses Lock Bits" page 320.
ATmega128
2467LS-AVR-05/04
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2467LS-AVR-05/04

8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATm

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