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2-wire Serial EEPROMs

128K (16, 384 x 8) 256K (32, 768 x 8)

Features
· Low-voltage and Standard-voltage Operation · · · · · · · · · · ·
2-wire Serial EEPROMs
128K (16, 384 x 8) 256K (32, 768 x 8)
Description
AT24C128 AT24C256
Pin Configurations
Pin Name Function
8-lead PDIP
A0 A1 NC GND
8-lead SOIC
A0 - A1 SDA SCL WP NC GND
Address Inputs Serial Data Serial Clock Input Write Protect No Connect Ground
8-ball dBGA2
VCC WP SCL SDA
8-lead TSSOP
A0 A1 NC GND
Bottom View 8-lead MAP
Bottom View
Rev. 0670N-SEEPR-4 / 04
Absolute Maximum Ratings
Operating Temperature................. -55°C to +125°C Storage Temperature ................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ...................-1.0V to +7.0V Maximum Operating Voltage ..................... 6.25V DC Output Current............................ 5.0 mA NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
AT24C128 / 256
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AT24C128 / 256
Pin Description
Memory Organization
AT24C128 / 256, 128K / 256K SERIAL EEPROM: The 128K / 256K is internally organized as 256 / 512 pages of 64-bytes each. Random word addressing requires a 14 / 15-bit data word address.
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Pin Capacitance(1)
DC Characteristics(1)
ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Notes:
1. VIL min and VIH max are reference only and are not tested. 2. The AT24C128 / 256 bearing the process letter "B" on the package (the mark is located in the lower right corner on the topside of the package) are approved for operation in the extended temperature range.
AT24C128 / 256
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AT24C128 / 256
AC Characteristics - Industrial Tempuatures
1.8-volt Symbol fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time(1) Inputs Fall Time
2.5-volt Min Max 400 1.3 0.6 0.4 0.4 0.9 0.05 0.5 0.25 0.25 0 100 0.3 300 0.6 50 0.25 50 10 or 5
5.0-volt Min Max 1000 Units kHz µs µs 0.55 µs µs µs µs µs ns 0.3 100 µs ns µs ns 10
Max 100
4.7 4.0 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 20 or 5
Stop Set-up Time Data Out Hold Time Write Cycle Time 25°C, Page Mode
ms Write Cycles
100k or 1, 000, 000(4)
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AC Characteristics(5) - Extended Tempuatures
2.7-volt Symbol fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time(1) Inputs Fall Time
5.0-volt Min Max 1000 0.4 0.4 Units kHz µs µs 0.55 µs µs µs µs µs ns 0.3 100 0.25 50 µs ns µs ns 10 or 5
Max 400
Stop Set-up Time Data Out Hold Time Write Cycle Time 25°C, Page Mode
ms Write Cycles
100k or 1, 000, 000(4)
AT24C128 / 256
0670N-SEEPR-4 / 04
AT24C128 / 256
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C128 / 256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
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Bus Timing (SCL: Serial Clock, SDA: Serial Data I / O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I / O)
8th BIT WORDn
twr STOP CONDITION
Note:
START CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
AT24C128 / 256
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AT24C128 / 256
Data Validity
Start and Stop Definition
Output Acknowledge
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Device Addressing
The 128K / 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices. The 128K / 256K uses the two device address bits A1, A0 to allow as many as four devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read / write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C128 / 256 has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 128K / 256K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower 6 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read / write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.
AT24C128 / 256
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AT24C128 / 256
Read Operations
Read operations are initiated the same way as write operations with the exception that the read / write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read / write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read / write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). Figure 1. Device Address
Figure 2. Byte Write
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Figure 3. Page Write
Notes:
Figure 4. Current Address Read
Figure 5. Random Read
Notes:
Figure 6. Sequential Read
AT24C128 / 256
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AT24C128 / 256
AT24C128 Ordering Information
Ordering Code AT24C128-10PI-2.7 AT24C128N-10SI-2.7 AT24C128W-10SI-2.7 AT24C128U2-10UI-2.7 AT24C128Y1-10YI-2.7 AT24C128-10TI-2.7 AT24C128-10PI-1.8 AT24C128N-10SI-1.8 AT24C128W-10SI-1.8 AT24C128U2-10UI-1.8 AT24C128Y1-10YI-1.8 AT24C128-10TI-1.8 AT24C128N-10SE-2.7 AT24C128N-10SU-2.7 AT24C128N-10SU-1.8 AT24C128-10TU-2.7 AT24C128-10TU-1.8 Note: Package 8P3 8S1 8S2 8U2-1 8Y1 8A2 8P3 8S1 8S2 8U2-1 8Y1 8A2 8S1 8S1 8S1 8A2 8A2 Operation Range
Industrial Temperature (-40°C to 85°C)
High Grade / Extended Temperature (-40°C to 125°C) Lead-free / Halogen-free / Industrial Temperature (-40°C to 85°C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
Package Type 8P3 8S1 8S2 8U2-1 8Y1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 3.6V)
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AT24C256 Ordering Information
Ordering Code AT24C256-10PI-2.7 AT24C256N-10SI-2.7 AT24C256W-10SI-2.7 AT24C256U2-10UI-2.7 AT24C256-10TI-2.7 AT24C256-10PI-1.8 AT24C256N-10SI-1.8 AT24C256W-10SI-1.8 AT24C256U2-10UI-1.8 AT24C256-10TI-1.8 AT24C256N-10SE-2.7 AT24C256N-10SU-2.7 AT24C256N-10SU-1.8 AT24C256-10TU-2.7 AT24C256-10TU-1.8 Note: Package 8P3 8S1 8S2 8U2-1 8A2 8P3 8S1 8S2 8U2-1 8A2 8S1 8S1 8S1 8A2 8A2 Operation Range
Industrial Temperature (-40°C to 85°C)
High Grade / Extended Temperature (-40°C to 125°C) Lead-free / Halogen-free / Industrial Temperature (-40°C to 85°C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
Package Type 8P3 8S1 8S2 8U2-1 8A2 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 3.6V)
AT24C128 / 256
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AT24C128 / 256
Packaging Information
8P3 - PDIP
Top View
End View
SYMBOL
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
4 PLCS
Side View
Notes:
1. This drawing is for general information only refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01 / 09 / 02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
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8S1 - JEDEC SOIC
Top View End View
Side View
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10 / 7 / 03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
AT24C128 / 256
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AT24C128 / 256
8S2 - EIAJ SOIC
Top View
End View
SYMBOL
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0° 1.27 BSC
Side View
Notes: 1. 2. 3. 4. 5.
This drawing is for general information only refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb / Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010 / -0.005 mm.
10 / 7 / 03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO.
REV. C
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8U2-1 - dBGA2
A1 BALL PAD CORNER
Top View
A1 BALL PAD CORNER
Side View
d (d1)
Bottom View
8 Solder Balls
6 / 24 / 03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2) DRAWING NO. PO8U2-1 REV. A
AT24C128 / 256
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AT24C128 / 256
8Y1 - MAP
PIN 1 INDEX AREA
Top View
End View
Bottom View
SYMBOL
MIN - 0.00 4.70 2.80 0.85 0.85 0.25
NOM - - 4.90 3.00 1.00 1.00 0.30 0.65 TYP
MAX 0.90 0.05 5.10 3.20 1.15 1.15 0.35
Side View
2 / 28 / 03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 DRAWING NO. 8Y1 REV. C
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8A2 - TSSOP
Pin 1 indicator this corner
Top View
End View
Side View
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5 / 30 / 02
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
AT24C128 / 256
0670N-SEEPR-4 / 04
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0670N-SEEPR-4 / 04 xM