September 2006 Application Note DKAN0000B Phase Locked Loop

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September 2006 Application Note DKAN0000B Phase Locked Loop

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LPC2000 Quick Start
September 2006
Application Note DKAN0000B
Phase Locked Loop (System Clock) Memory Accelerator Module (MAM) Vectored Interrupt Controller (VIC)
Introduction
This document will allow user quickly start project utilizing ARM7 LPC2000 Series devices from NXP. project contained this application note contains small, simple program with everything essential setting Phase Locked Loop, Memory Accelerator Module, Vectored Interrupt Controller. This project tailored with GCC, (GNU Compiler Collection). GNUARM 4.1.1 used during testing; however, other compilers used with appropriate changes header files.
Application
Phase Locked Loop (System Clock)
(Phase Locked Loop) must enabled, locked before used clock source. When switching from oscillator clock output vice versa, internal circuitry synchronizes operation order ensure that glitches generated. However hardware capable insuring locked before connected even automatically disconnecting PLL's lock lost during operation. event loss lock, likely that oscillator clock become unstable disconnecting will remedy situation. setup system.h header file; this file contains symbolic names (#defines) appropriate registers control PLL. Including Configuration register (PLLCFG), this contains Multiplier Divider values. Control register (PLLCON), this contains functions enable connect PLL. using function specific enabling PLL, hardware will attempt lock settings defined multiplier divider values. selecting connect function, processor chip functions will from output clock. However, changes Control register take effect until correct feed sequence been given. This process shown Code
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LPC2000 Quick Start
PLLCON PLLE); enable PLLFEED PLL_FEED1; /*Feed sequence PLLFEED PLL_FEED2; while (!(PLLSTAT PLOCK))); Wait lock PLLCON PLLE) PLLC)); Connect enable PLLFEED PLL_FEED1; /*Feed sequence PLLFEED PLL_FEED2;
Code Setup Sequence
determine actual clock speed Device Multiplier Divider values must defined. Multiplier value defined with PLL_MUL, shown Code this value multiplied with external crystal form main clock.
#define PLL_MUL
/*Keil MCB2100, LPC2148 Demo boards*/
Code Multiplier from System.h
Divider value defined with VAL_PSEL, shown Code properly determine this value these equations must solved. First Calculate Value this expression:
ocessorClock Then Calculate Value this expression: ocessorClock
final valued this symbolic constant must between both those calculated values must
#define VAl_PSEL
Code Divider from System.h
Memory Accelerator Module (MAM)
Memory Accelerator Module special 128bit interface accessing flash memory system. 32bit mode, this interface allows accessing instructions time. This allows much faster clock rate with having timing issues with slower flash memory. However this feature does come price, branch instructions will cause flash memory miss. solve this issue there three modes operation. three modes operation defined MAM, trading performance ease predictability. (MAM_MODE) variable used define these three options. Mode off. memory requests result Flash read operation. There instruction prefetches. Mode partially enabled. Sequential instruction accesses fulfilled from holding latches data present. Instruction prefetch enabled. Non-sequential instruction accesses initiate Flash read Digi-Key Corporation Page
LPC2000 Quick Start operations. This means that branches cause memory fetches. data operations cause Flash read because buffered data access timing hard predict very situation dependent. Mode fully enabled. memory request (code data) value that contained corresponding holding latches fulfilled from latch. Instruction prefetch enabled. Flash read operations initiated instruction prefetch code data values available corresponding holding latches. setup first clearing Control Register. Then Timing Control Register should updated with number wait cycles required specific clock speed. 60Mhz clock speed timing clock cycles will work. Finally Control Register updated with Mode required application.
/*SETUP MEMORY ACCELERATOR MODULE*/ MAMCR MAMTIM MAM_FETCH; MAMCR MAM_MODE;
Code Setup
Vectored Interrupt Controller (VIC)
Vectored Interrupt Controller powerful quite complex deal with, however working thru this example shown below Code quite easy deal with. built with vectored slots; each slot Vector Control Register (VICVectCntlX) Vector Address Register (VICVectAddrX). Priority this design determined slot number, therefore slot highest priority slot lowest. setup specific interrupt, first using Vector Control Register, slot enable specific interrupt bits. Next load address function used into Vector Address Register. Finally enable specific interrupt Interrupt Enable Register (VICIntEnable).
VICVectCntl0 (VIC_ENABLE VIC_EINT1); Setup with Vector position VICVectAddr0 (unsigned long) eint1; Setup jump function VICIntEnable VIC_EINT1 Enable Specific
Code Example Enable Specific
actual interrupt encapsulated Code user code added this function. However when exiting interrupt routine, interrupt flag must cleared specific interrupt interrupt must acknowledged.
void _attribute_ ((interrupt("IRQ"))) eint1(void) EXTINT VIC_EINT1_FLAG; Clear interrupt flag VICVectAddr Acknowledge Interrupt
Code Empty Function
Digi-Key Corporation
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LPC2000 Quick Start
Conclusion
this application note small simple program built setup Phase Locked Loop, Memory Accelerator Module, Vectored Interrupt Controller. project utilized Keil MCB2100 development kit, which contains ARM7 LPC2000 Series from NXP. file included with application note; contains small project utilizing features discussed here. This file used template help speed development your applications. Parts List: Keil Development Kit, MCB2100, Digi-Key part number: 568-1755-ND
Disclaimer
Digi-Key offers Technical Assistance Design Support Services convenience Digi-Key customers. Digi-Key Technical Assistance Design Support Services personnel strive provide useful information regarding Digi-Key products. DIGI-KEY DOES GUARANTEE THAT INFORMATION RECOMMENDATION PROVIDED ACCURATE, COMPLETE, CORRECT, DIGI-KEY SHALL HAVE RESPONSIBILITY LIABILITY WHATSOEVER CONNECTION WITH INFORMATION RECOMMENDATION PROVIDED, CUSTOMER'S RELIANCE SUCH INFORMATION RECOMMENDATION. CUSTOMER SOLELY RESPONSIBLE ANALYZING DETERMINING APPROPRIATENESS INFORMATION RECOMMENDATION PROVIDED DIGI-KEY TECHNICAL ASSISTANCE DESIGN SUPPORT SERVICES PERSONNEL, RELIANCE SUCH INFORMATION RECOMMENDATION CUSTOMER'S SOLE RISK DISCRETION. ACCORDINGLY, CUSTOMER SHALL RELEASE HOLD DIGI-KEY HARMLESS FROM AGAINST LOSS, LIABILITY, DAMAGE INCURRED CUSTOMER THIRD PARTY RESULT INFORMATION RECOMMENDATION PROVIDED CUSTOMER CUSTOMER'S RELIANCE SUCH INFORMATION RECOMMENDATION.
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September 2006 Application Note DKAN0000B Phase Locked Loop

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