TigerSHARC® Embedded Processor ADSP-TS201S BENEFITS Provides
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MHz, 1.67 instruction cycle rate bits internal-on-chip-DRAM memory (576-ball) thermally enhanced ball grid array package Dual-computation blocks-each containing ALU, multiplier, shifter, register file, communications logic unit (CLU) Dual-integer ALUs, providing data addressing pointer manipulation Integrated includes 14-channel controller, external port, four link ports, SDRAM controller, programmable flag pins, timers, timer expired system integration 1149.1 IEEE compliant JTAG test access port on-chip emulation On-chip arbitration glueless multiprocessing
TigerSHARC® Embedded Processor ADSP-TS201S
BENEFITS
Provides high-performance Static Superscalar operations, optimized telecommunications infrastructure other large, demanding multiprocessor applications Performs exceptionally well algorithm benchmarks (see benchmarks Table Supports overhead transfers between internal memory, external memory, memory-mapped peripherals, link ports, host processors, other (multiprocessor) DSPs Eases programming through extremely flexible instruction high-level-language friendly architecture Enables scalable multiprocessing systems with communications overhead
DATA ADDRESS GENERATION INTEGER PROGRAM SEQUENCER ADDR FETCH J-BUS ADDR J-BUS DATA K-BUS ADDR K-BUS DATA I-BUS ADDR I-BUS DATA INTEGER
BITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CACHE) 4xCROSSBAR CONNECT
JTAG
JTAG PORT EXTERNAL PORT ADDR HOST MULTIPROC SDRAM CTRL C-BUS DATA CTRL CTRL
S-BUS ADDR S-BUS DATA
LINK PORTS
SHIFT REGISTER FILE
REGISTER FILE
SHIFT
COMPUTATIONAL BLOCKS
Figure Functional Block Diagram
TigerSHARC TigerSHARC logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2004 Analog Devices, Inc. rights reserved.
ADSP-TS201S
TABLE CONTENTS
General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer (IALU) Program Sequencer Interrupt Controller Flexible Instruction Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface Controller Link Ports (LVDS) Timer General-Purpose Reset Booting Clock Domains Power Domains Filtering Reference Voltage Clocks Development Tools Evaluation Designing Emulator-Compatible Board (Target) Additional Information Function Descriptions Strap Function Descriptions ADSP-TS201S-Specifications Recommended Operating Conditions Electrical Characteristics Absolute Maximum Ratings Sensitivity Timing Specifications General Timing Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics Timing Link Port-Data Timing Link Port-Data Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics 576-Ball BGA_ED Configurations Outline Dimensions Ordering Guide
REVISION HISTORY
11/04-Rev. Rev. Initial (Production) Version Applies corrections additional information (including more detail differences between parts) SCLK_VREF Filtering Scheme Definitions-Link Ports Definitions-Impedance Control, Drive Strength Control, Regulator Enable Recommended Operating Conditions Electrical Characteristics Power-Up Timing Signal Specifications Ordering Guide Provides usable jitter specification Reference Clocks-System Clock (SCLK) Cycle Time Provides thermal information wider temperature range Thermal Characteristics Package
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GENERAL DESCRIPTION
ADSP-TS201S TigerSHARC processor ultrahigh performance, static superscalar processor optimized large signal processing tasks communications infrastructure. combines very wide memory widths with dual computation blocks-supporting 40-bit floating-point supporting 16-, 32-, 64-bit fixed-point processing-to standard performance digital signal processors. TigerSHARC static superscalar architecture lets execute four instructions each cycle, performing fixedpoint (16-bit) operations floating-point operations. Four independent 128-bit wide internal data buses, each connecting memory banks, enable quad-word data, instruction, accesses provide 33.6G bytes second internal memory bandwidth. Operating MHz, ADSP-TS201S processor's core 1.67 instruction cycle time. Using single-instruction, multiple-data (SIMD) features, ADSP-TS201S processor perform billion 40-bit MACs billion 80-bit MACs second. Table shows DSP's performance benchmarks. Table General-Purpose Algorithm Benchmarks
Benchmark Speed 32-bit algorithm, billion MACs/s peak performance 15.7 point complex FFT1 (Radix2) point complex (Radix2) 2.33 filter (per real tap) 0.83 8][8 matrix multiply (complex, floating-point) 16-bit algorithm, billion MACs/s peak performance point complex FFT1 (Radix transfer rate External port bytes/s Link ports (each) bytes/s
Four 128-bit internal data buses, each connecting memory banks On-chip DRAM (24M bit) external port that provides interface host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, external SRAM SDRAM 14-channel controller Four full-duplex LVDS link ports 64-bit interval timers timer expired 1149.1 IEEE compliant JTAG test access port on-chip emulation Figure Page shows typical single-processor system with external SRAM SDRAM. Figure Page shows typical multiprocessor system.
ADSP-TS201S
RST_IN RST_OUT POR_IN CLOCK SCLK SCLKRAT2-0 SCLK_VREF VREF IRQ3-0 FLAG3-0 ID2-0 MSSD3-0 LDQM HDQM SDWE SDCKE BOFF
HOST PROCESSOR INTERFACE (OPTIONAL) BOOT EPROM (OPTIONAL)
ADDR
Clock Cycles 9419 1397544 1399
REFERENCE REFERENCE
SDRAM MEMORY (OPTIONAL)
BRST ADDR31-0 DATA63-0 WRH/WRL MS1-0
DATA
MEMORY (OPTIONAL)
ADDR DATA
ADDR DATA
Cache preloaded
LINK DEVICES MAX) (OPTIONAL)
SDA10 BR7-0 IORD IOWR IOEN LxDATO3-0P/N LxCLKOUTP/N DMAR3-0 LxACKI LxBCMPO
CONTROL ADDRESS DATA
ADDR DATA
DEVICE (OPTIONAL)
DATA
ADSP-TS201S processor code-compatible with other TigerSHARC processors. Functional Block Diagram Page shows ADSPTS201S processor's architectural blocks. These blocks include: Dual compute blocks, each consisting ALU, multiplier, 64-bit shifter, 128-bit CLU, 32-word register file associated data alignment buffers (DABs) Dual integer ALUs (IALUs), each with 31-word register file data addressing status register program sequencer with instruction alignment buffer (IAB) branch target buffer (BTB) interrupt controller that supports hardware software interrupts, supports level- edge-triggers, supports prioritized, nested interrupts
LxDATI3-0P/N LxCLKINP/N LxACKO LxBCMPI CONTROLIMP1-0 BUSLOCK TMR0E DS2-0 JTAG
Figure ADSP-TS201S Single-Processor System with External SDRAM
TigerSHARC uses Static Superscalararchitecture. This architecture superscalar that ADSP-TS201S processor's core execute simultaneously from four 32-bit instructions encoded very large instruction word (VLIW) instruction line using DSP's dual compute blocks. Because
Static Superscalar trademark Analog Devices, Inc.
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does perform instruction re-ordering run-time- programmer selects which operations will execute parallel prior run-time-the order instructions static. With exceptions, instruction line, whether contains one, two, three, four 32-bit instructions, executes with throughput cycle ten-deep processor pipeline. optimal program execution, programmers must follow DSP's instruction parallelism rules when encoding instruction line. general, selection instructions that execute parallel each cycle depends instruction line resources each instruction requires source destination registers used instructions. programmer direct control three core components-the IALUs, compute blocks, program sequencer. ADSP-TS201S processor, most cases, two-cycle execution pipeline that fully interlocked, so-whenever computation result unavailable another operation dependent it-the automatically inserts more stall cycles needed. Efficient programming with dependency-free instructions eliminate most computational memory transfer data dependencies. addition, ADSP-TS201S processor supports SIMD operations ways-SIMD compute blocks SIMD computations. programmer load both compute blocks with same data (broadcast distribution) different data (merged distribution). Shifter-the 64-bit shifter performs logical arithmetic shifts, bitstream manipulation, field deposit extraction operations. Communications Logic Unit (CLU)-this 128-bit unit provides Trellis Decoding (for example, Viterbi Turbo decoders) executes complex correlations CDMA communication applications (for example chip-rate symbol-rate functions). Using these features, compute blocks can: Provide MACs cycle peak MACs cycle sustained 16-bit performance provide MACs cycle peak MACs cycle sustained 32-bit performance (based FIR) Execute single-precision floating-point execute fixed-point (16-bit) operations cycle, providing GFLOPS 12.0 GOPS performance Perform complex 16-bit MACs cycle Execute eight Trellis butterflies cycle
DATA ALIGNMENT BUFFER (DAB)
quad-word FIFO that enables loading quadword data from nonaligned addresses. Normally, load instructions must aligned their data size that quad words loaded from quad-aligned address. Using significantly improves efficiency some applications, such filters.
DUAL COMPUTE BLOCKS
ADSP-TS201S processor compute blocks that execute computations either independently together singleinstruction, multiple-data (SIMD) engine. issue compute instructions compute block each cycle, instructing ALU, multiplier, shifter, perform independent, simultaneous operations. Each compute block execute eight 8-bit, four 16-bit, 32-bit, 64-bit SIMD computations parallel with operation other block. compute blocks referred assembly syntax, each block contains four computational units-an ALU, multiplier, 64-bit shifter, 128-bit CLU-and 32word register file. Register File-each compute block multiported 32word, fully orthogonal register file used transferring data between computation units data buses storing intermediate results. Instructions access registers register file individually (word-aligned), sets (dual-aligned), sets four (quad-aligned). ALU-the performs standard arithmetic operations both fixed- floating-point formats. also performs logic operations. Multiplier-the multiplier performs both fixed- floating-point multiplication fixed-point multiply accumulate.
DUAL INTEGER (IALU)
ADSP-TS201S processor IALUs that provide powerful address generation capabilities perform many generalpurpose integer operations. IALUs referred assembly syntax have following features: Provide memory addresses data update pointers Support circular buffering bit-reverse addressing Perform general-purpose integer operations, increasing programming flexibility Include 31-word register file each IALU address generators, IALUs perform immediate indirect (pre- post-modify) addressing. They perform modulus bit-reverse operations with constraints placed memory addresses modulus data buffer placement. Each IALU specify either single-, dual-, quad-word access from memory. IALUs have hardware support circular buffers, reverse, zero-overhead looping. Circular buffers facilitate efficient programming delay lines other data structures required digital signal processing, they commonly used digital filters Fourier transforms. Each IALU provides registers four circular buffers, applications total eight circular buffers. IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, simplifying implementation. Circular buffers start memory location.
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Because IALU's computational pipeline cycle deep, most cases integer results available next cycle. Hardware (register dependency check) causes stall result unavailable given cycle. subtract both computation blocks while also branches another location program. Some features instruction include: instructions communications infrastructure govern Trellis Decoding (for example, Viterbi Turbo decoders) Despreading complex correlations Algebraic assembly language syntax Direct support DSP, imaging, video arithmetic types Eliminates toggling hardware modes because modes supported options (for example, rounding, saturation, others) within instructions Branch prediction encoded instruction; enables zerooverhead loops Parallelism encoded instruction line Conditional execution optional instructions User defined partitioning between program data memory
PROGRAM SEQUENCER
ADSP-TS201S processor's program sequencer supports following: fully interruptible programming model with flexible programming assembly C/C++ languages; handles hardware interrupts with high throughput aborted instruction cycles ten-cycle instruction pipeline-four-cycle fetch pipe six-cycle execution pipe-computation results available cycles after operands available Supply instruction fetch memory addresses; sequencer's instruction alignment buffer (IAB) caches five fetched instruction lines waiting execute; program sequencer extracts instruction line from distributes appropriate core component execution Management program structures program flow determined according JUMP, CALL, RTI, instructions, loop structures, conditions, interrupts, software exceptions Branch prediction 128-entry branch target buffer (BTB) reduce branch delays efficient execution conditional unconditional branch instructions zero-overhead looping; correctly predicted branches that taken occur with zero overhead cycles, overcoming five-to-nine stage branch penalty Compact code without requirement align code memory; handles alignment
MEMORY
DSP's internal external memory organized into unified memory map, which defines location (address) elements system, shown Figure memory divided into four memory areas-host space, external memory, multiprocessor space, internal memory-and each memory space, except host memory, subdivided into smaller memory spaces. ADSP-TS201S processor internal memory bits on-chip DRAM memory, divided into blocks bits (128K words bits). Each block-M0, M10-can store program instructions, data, both, applications configure memory suit specific needs. Placing program instructions data different memory blocks, however, enables access data while performing instruction fetch. Each memory segment contains 128K cache enable single cycle accesses internal DRAM. internal memory blocks connect four 128-bit wide internal buses through crossbar connection, enabling perform four memory transfers same cycle. DSP's internal architecture provides total memory bandwidth 33.6G bytes second, enabling core access eight 32-bit data-words four 32-bit instructions each cycle. DSP's flexible memory structure enables: core accesses different memory blocks same cycle core access three memory blocks parallel-one instruction data accesses Programmable partitioning program data memory Program access memory 32-, 64-, 128-bit words-16-bit words with
Interrupt Controller
supports nested nonnested interrupts. Each interrupt type register interrupt vector table. Also, each both interrupt latch register interrupt mask register. interrupts fixed either level-sensitive edge-sensitive, except IRQ3-0 hardware interrupts, which programmable. distinguishes between hardware interrupts software exceptions, handling them differently. When software exception occurs, aborts other instructions instruction pipe. When hardware interrupt occurs, continues execute instructions already instruction pipe.
Flexible Instruction
128-bit instruction line, which contain four 32-bit instructions, accommodates variety parallel operations concise programming. example, instruction line direct conditionally execute multiply, add,
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GLOBAL SPACE
0xFFFFFFFF
HOST (MSH)
0x80000000 RESERVED 0x74000000 MSSD BANK (MSSD3) 0x70000000 0x03FFFFFF
EXTERNAL MEMORY SPACE
INTERNAL SPACE
RESERVED 0x64000000 MSSD BANK (MSSD2) 0x60000000 RESERVED 0x54000000 MSSD BANK (MSSD1) 0x50000000 RESERVED 0x44000000 MSSD BANK (MSSD0) 0x40000000 BANK (MS1) 0x38000000 BANK (MS0) 0x30000000
MULTIPROCESSOR MEMORY SPACE
RESERVED
0x001F03FF REGISTERS (UREGS) RESERVED 0x001E03FF INTERNAL ISTERS (UREG RESERVED INTERNAL MEMO BLOCK RESERVED 0x0011FFFF INTERNAL MEMO BLOCK RESERVED INTERNAL MEMORY BLOCK RESERVED INTERNAL MEMORY BLOCK RESERVED INTERNAL MEMORY BLOCK 0x00040000 RESERVED 0x0001FFFF INTERNAL MEMORY BLOCK 0x00000000 INTERNAL MEMORY 0x00100000 0x000DFFFF 0x000C0000 0x0009FFFF 0x00080000 0x0005FFFF RESERVED 0X001E0000 0x0015FFFF 0x00140000 CESSO 0X001F0000
0x2C000000 CESSO 0x28000000 CESSO 0x24000000 CESSO 0x20000000 CESSO 0x1C000000 CESSO 0x18000000 CESSO 0x14000000 CESSO 0x10000000 BROADCAST 0X0C000000 EACH COPY INTERNAL SPACE
0x03FFFFFF 0x00000000
Figure ADSP-TS201S Memory
EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
ADSP-TS201S processor's external port provides DSP's interface off-chip memory peripherals. word address space included DSP's unified address space. separate on-chip buses-four 128-bit data buses four 32-bit address buses-are multiplexed interface transferred external port over create external system transaction. external system provides single 64-bit data single 32-bit address bus. external port supports data transfer rates bytes second over external bus. external configured 64-bit, littleendian operations. When system configured 64-bit operations, lower bits external data connect even addresses, upper bits connect addresses. external port supports pipelined, slow, SDRAM protocols. Addressing external memory devices memorymapped peripherals facilitated on-chip decoding high order address lines generate memory bank select signals. ADSP-TS201S processor provides programmable memory, pipeline depth, idle cycle synchronous accesses, external acknowledge controls support interfacing pipelined slow devices, host processors, other memorymapped peripherals with variable access, hold, disable time requirements.
Host Interface
ADSP-TS201S processor provides easy configurable interface between external host processors through external port. accommodate variety host processors,
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host interface supports pipelined slow protocols ADSP-TS201S processor accesses host slave pipelined host accesses ADSP-TS201S processor slave. Each protocol programmable transmission parameters, such idle cycles, pipe depth, internal wait cycles. host interface supports burst transactions initiated host processor. After host issues starting address burst asserts BRST signal, increments address internally while host continues assert BRST. host interface provides deadlock recovery mechanism that enables host recover from deadlock situations involving DSP. BOFF signal provides deadlock recovery mechanism. When host asserts BOFF, backs current transaction asserts relinquishes external bus. host directly read write internal memory ADSP-TS201S processor, access most registers, including control (TCB) registers. Vector interrupts support efficient execution host commands. words bits SDRAM. SDRAM interface mapped external memory each DSP's unified memory map.
EPROM Interface
ADSP-TS201S processor configured boot from external 8-bit EPROM reset through external port. automatic process (which follows reset) loads program from EPROM into internal memory. This process uses wait cycles each read access. During booting, functions EPROM chip select signal. EPROM boot procedure uses Channel which packs bytes into 32-bit instructions. Applications also access EPROM (write flash memories) during normal operation through DMA. EPROM flash memory interface mapped DSP's unified memory map. byte address space limited maximum bytes address bits). EPROM flash memory interface used after boot DMA.
CONTROLLER
ADSP-TS201S processor's on-chip controller, with channels, provides zero-overhead data transfers without processor intervention. controller operates independently invisibly DSP's core, enabling operations occur while DSP's core continues execute program instructions. controller performs transfers between internal memory external memory memory-mapped peripherals, internal memory other DSPs common bus, host processor, link port I/O; between external memory external peripherals link port I/O; between external master internal memory link port I/O. controller performs following operations: External port block transfers. Four dedicated bidirectional channels transfer blocks data between DSP's internal memory external memory memorymapped peripheral external bus. These transfers support master mode handshake mode protocols. Link port transfers. Eight dedicated channels (four transmit four receive) transfer quad-word data only between link ports between link port internal external memory. These transfers only handshake mode protocol. priority rotates between four receive channels. AutoDMA transfers. dedicated unidirectional channels transfer data received from external master internal memory link port I/O. These transfers only slave mode protocol, external master must initiate transfer. controller provides these additional features: Flyby transfers. Flyby operations only occur through external port (DMA channel involve DSP's core. controller acts conduit transfer data from device external SDRAM memory. During transaction, relinquishes external
Multiprocessor Interface
ADSP-TS201S processor offers powerful features tailored multiprocessing systems through external port link ports. This multiprocessing capability provides highest bandwidth interprocessor communication, including: eight DSPs common On-chip arbitration glueless multiprocessing Link ports point-to-point communication external port link ports provide integrated, glueless multiprocessing support. external port supports unified address space (see Figure that enables direct interprocessor accesses each ADSPTS201S processor's internal memory registers. DSP's on-chip distributed arbitration logic provides simple, glueless connection systems containing eight ADSPTS201S processors host processor. arbitration rotating priority. lock supports indivisible read-modifywrite sequences semaphores. fairness feature prevents from holding external long. DSP's four link ports provide second path interprocessor communications with throughput bytes second. cluster provides bytes second throughput-with total 4.8G bytes second interprocessor bandwidth (limited bandwidth).
SDRAM Controller
SDRAM controller controls ADSP-TS201S processor's transfers data from external synchronous DRAM (SDRAM) throughput bits SCLK cycle using external port SDRAM control pins. SDRAM interface provides glueless interface with standard SDRAMs-16M bit, bit, 128M bit, 256M bit. supports directly maximum four banks
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ADSP-TS201S ADSP-TS201S ADSP-TS201S ADSP-TS201S ADSP-TS201S ADSP-TS201S ADSP-TS201S ID2-0 RST_IN CLKS/REFS LINK DEVICES LINK BR7-2,0 ADDR31-0 DATA63-0 CONTROL
CONTROL ADDRESS
CONTROL
ADDRESS
RESET
ID2-0 RST_IN CLKS/REFS RST_OUT POR_IN
BR7-1 ADDR31-0 DATA63-0 WRH/L MS1-0 BUSLOCK BRST DMAR3-0 BOFF IORD IOWR IOEN MSSD3-0 LDQM HDQM SDWE SDCKE SDA10 CONTROL
DATA
ADSP-TS201S
DATA
ADDR DATA ADDR DATA BOOT EPROM (OPTIONAL) CLOCK GLOBAL MEMORY PERIPHERALS (OPTIONAL)
CLOCK
SCLK
REFERENCE REFERENCE
SCLK_VREF VREF SCLKRAT2-0
IRQ3-0 FLAG3-0 LINK LxDATO3-0P/N LxCLKOUTP/N LINK DEVICES MAX) (OPTIONAL) LxACKI LxBCMPO LxDATI3-0P/N LxCLKINP/N LxACKO LxBCMPI TMR0E CONTROLIMP1-0 DS2-0 JTAG
ADDR DATA ADDR DATA
HOST PROCESSOR INTERFACE (OPTIONAL)
SDRAM MEMORY (OPTIONAL)
Figure ADSP-TS201S Shared Memory Multiprocessing System
data bus; outputs addresses memory selects (MSSD3-0); outputs IORD, IOWR, IOEN, RD/WR strobes; responds ACK. chaining. chaining operations enable applications automatically link transfer sequence another continuous transmission. sequences occur over different channels have different transmission attributes. Two-dimensional transfers. controller access transfer two-dimensional memory arrays transmit receive channel. These transfers implemented with index, count, modify registers both dimensions.
LINK PORTS (LVDS)
DSP's four full-duplex link ports each provide additional four-bit receive four-bit transmit capability, using LowVoltage, Differential-Signal (LVDS) technology. With ability operate double data rate-latching data both rising falling edges clock-running MHz, each link port support 500M bytes second direction, combined maximum throughput bytes second. link ports provide optional communications channel that useful multiprocessor systems implementing pointto-point interprocessor communications. Applications also link ports booting.
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Each link port triple-buffered quad-word input double-buffered quad-word output registers. DSP's core write directly link port's transmit register read from receive register, controller perform transfers through eight (four transmit four receive) dedicated link port channels. Each link port direction three signals that control operation. transmitter, LxCLKOUT output transmit clock, LxACKI handshake input control data flow, LxBCMPO output indicates that block transfer complete. receiver, LxCLKIN input receive clock, LxACKO handshake output control data flow, LxBCMPI input indicates that block transfer complete. LxDATO3-0 pins data output transmitter LxDATI3-0 pins input data receiver. Applications program separate error detection mechanisms transmit receive operations (applications checksum mechanism implement consecutive link port transfers), size data packets, speed which bytes transmitted. Using boot" option, ADSP-TS201S processor must start running from memory when interrupts asserted. Table Boot, from Memory Addresses
Interrupt IRQ0 IRQ1 IRQ2 IRQ3 Address 0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory)
ADSP-TS201S processor core always exits from reset idle state waits interrupt. Some interrupts interrupt vector table initialized enabled after reset. more information boot options, EE-200: ADSPTS20x TigerSHARC Processor Boot Loader Kernels Operation Analog Devices website (www.analog.com)
CLOCK DOMAINS
uses calculated ratios SCLK clock operate shown Figure instruction execution rate equal CCLK. from SCLK generates CCLK which phaselocked. SCLKRATx pins define clock multiplication SCLK CCLK (see Table Page 12). link port clock generated from CCLK software programmable divisor, operates CCLK. Memory transfers external link port buffers operate SOCCLK rate. SCLK also provides clock input external interface defines specification reference external signals. external interface runs SCLK frequency. maximum SCLK frequency quarter internal clock (CCLK) frequency.
EXTERNAL INTERFACE SCLK SCLKRATx BITS, LCTLx REGISTER CCLK (INSTRUCTION RATE) SOCCLK (PERIPHERAL RATE) LxCLKOUT (LINK OUTPUT RATE)
TIMER GENERAL-PURPOSE
ADSP-TS201S processor timer (TMR0E) that generates output when programmed timer counter expired four programmable general-purpose pins (FLAG3-0) that function either single-bit input output. outputs, these pins signal peripheral devices; inputs, they provide test conditional branching.
RESET BOOTING
ADSP-TS201S processor three levels reset: Power-up reset-after power-up system (SCLK, static inputs, strap pins stable), RST_IN must asserted (low). Normal reset-for chip reset following power-up reset, RST_IN must asserted (low). DSP-core reset-when setting SWRST EMUCTL, core reset, external port I/O. normal operations, RST_OUT POR_IN pin. After reset, ADSP-TS201S processor four boot options beginning operation: Boot from EPROM. Boot external master (host another ADSP-TS201S processor). Boot link port. boot-start running from memory address selected with IRQ3-0 interrupt signals. Table
Figure Clock Domains
POWER DOMAINS
ADSP-TS201S processor separate power supply connections internal logic (VDD), analog circuits (VDD_A), buffer (VDD_IO), internal DRAM (VDD_DRAM) power supply. Note that analog (VDD_A) supply powers clock generator PLLs. produce stable clock, systems must provide clean power supply power input VDD_A. Designs must critical attention bypassing VDD_A supply.
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FILTERING REFERENCE VOLTAGE CLOCKS
Figure Figure show possible circuits filtering VREF, SCLK_VREF. These circuits provide reference voltages switching voltage reference system clock reference. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information)
SCLK_VREF
VDD_IO
VREF
SERIES RESISTOR (±1%) 2.87 SERIES RESISTOR (±1%) CAPACITOR (SMD) CAPACITOR SMD) PLACED CLOSE DSP'S PINS
Figure VREF Filtering Scheme
CLOCK DRIVER VOLTAGE* DD_IO
Insert breakpoints conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage TigerSHARC processor development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's command line switches VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, preemptive, cooperative time-sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard
SERIES RESISTOR (±1%) 2.87 SERIES RESISTOR (±1%) CAPACITOR (SMD) CAPACITOR SMD) PLACED CLOSE DSP'S PINS CLOCK DRIVER VOLTAGE VDD_IO
Figure SCLK_VREF Filtering Scheme
DEVELOPMENT TOOLS
ADSP-TS201S processor supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other TigerSHARC processors also fully emulates ADSP-TS201S processor. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. point theses tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code assembly. architectural features that improve efficiency compiled C/C++ code.
CROSSCORE registered trademark Analog Devices, Inc. VisualDSP++ registered trademark Analog Devices, Inc.
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command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various VDK-based objects, visualizing system state, when debugging application that uses VDK. VCSE Analog Devices' technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. also used downloading components from Web, dropping them into application, publishing component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. expert linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas external memory with drag mouse, examine run-time stack heap usage. expert linker fully compatible with existing linker definition file (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG test access port ADSP-TS201S processor monitor control target board processor during emulation. emulator provides full speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting TigerSHARC processor family. Hardware tools include TigerSHARC processor plug-in cards. Third party software tools include libraries, realtime operating systems, block diagram design tools. With full version VisualDSP++ installed (sold separately), engineers develop software EZ-KIT Lite custom-defined system. Connecting Analog Devices JTAG emulators EZ-KIT Lite board enables high speed, nonintrusive emulation.
DESIGNING EMULATOR-COMPATIBLE BOARD (TARGET)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG test access port (TAP) each JTAG DSP. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target board must include header that connects DSP's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- string "EE-68" site search. This document updated regularly keep pace with improvements emulator support.
ADDITIONAL INFORMATION
This data sheet provides general overview ADSPTS201S processor's architecture functionality. detailed information ADSP-TS201S processor's core architecture instruction set, ADSP-TS201 TigerSHARC Processor Hardware Reference ADSP-TS201 TigerSHARC Processor Programming Reference. detailed information development tools this processor, VisualDSP++ User's Guide TigerSHARC Processors.
EVALUATION
Analog Devices offers range EZ-KIT Lite® evaluation platforms cost-effective method learn more about developing prototyping applications with Analog Devices processors, platforms, software tools. Each EZ-KIT Lite includes evaluation board along with evaluation suite VisualDSP++ development debugging environment with C/C++ compiler, assembler, linker. Also included sample application programs, power supply, cable. evaluation versions software tools limited only with EZ-KIT Lite product. controller EZ-KIT Lite board connects board port user's enabling VisualDSP++ evaluation suite emulate on-board processor in-circuit. This permits customer download, execute, debug programs EZ-KIT Lite system. also allows in-circuit programming on-board flash device store user-specific boot code, enabling board standalone unit, without being connected
EZ-Kit Lite registered trademark Analog Devices, Inc.
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FUNCTION DESCRIPTIONS
While most ADSP-TS201S processor's input pins normally synchronous-tied specific clock-a asynchronous. these asynchronous signals, on-chip synchronization circuit prevents metastability problems. specification asynchronous signals when system design requires predictable, cycle-by-cycle behavior these signals. Table Definitions-Clocks Reset
Description Core Clock Ratio. DSP's core clock (CCLK) rate SCLK, where userprogrammable using SCLKRATx pins values shown Table These pins change only during reset; connect these pins VDD_IO VSS. reset specifications Table Table Table must satisfied. core clock rate (CCLK) instruction cycle rate. SCLKRAT2-0 (pd) System Clock Input. DSP's system input clock cluster bus.The core clock rate user-programmable using SCLKRATx pins. more information, Clock SCLK Domains Page Reset. Sets known state causes program idle state. RST_IN must asserted specified time according type reset operation. details, RST_IN Reset Booting Page Table Page Figure Page RST_OUT Reset Output. Indicates that reset complete. Connect POR_IN. POR_IN Power-On Reset internal DRAM. Connect RST_OUT. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal Type Term
output pins three-stated during normal operation. three-states outputs during reset, allowing these pins their internal pull-up pull-down state. Some pins have internal pull-up pull-down resistor (±30% tolerance) that maintains known value during transitions between different drivers.
Table SCLK Ratio
SCLKRAT2-0 (default) Ratio Reserved
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Table Definitions-External Port Controls
Description Address Bus. issues addresses accessing memory peripherals these pins. multiprocessor system, master drives addresses accessing internal memory processor registers other ADSP-TS201S processors. I/O/T inputs addresses when host another accesses internal memory ADDR31-0 (pu_ad) processor registers. I/O/T External Data Bus. drives receives data instructions these pins. DATA63-0 (pu_ad) Pull-up pull-down resistors unused DATA pins unnecessary. Memory Read. asserted whenever reads from slave system, excluding SDRAM. When slave, input indicates read transI/O/T actions that access internal memory universal registers. multiprocessor (pu_0) epu1 system, master drives changes concurrently with ADDR pins. Write Low. asserted cases: when ADSP-TS201S processor writes even address word external memory another external agent; when ADSP-TS201S processor writes 32-bit zone (host, memory, programmed 32-bit bus). external master (host DSP) asserts writing DSP's word internal memory. multiprocessor system, master drives WRL. changes concurrently with ADDR pins. When slave, input indicates write transactions that access internal memory I/O/T universal registers. (pu_0) epu1 Write High. asserted when ADSP-TS201S processor writes long word bits) writes address word external memory another external agent 64-bit data bus. external master (host another DSP) must assert writing DSP's high word 64-bit data bus. multiprocessing system, master drives WRH. changes concurrently with ADDR pins. When I/O/T slave, input indicates write transactions that access internal (pu_0) epu1 memory universal registers. Acknowledge. External slave devices deassert wait states external memory accesses. used devices, memory controllers other peripherals data phase. deassert wait states read write I/O/T/OD accesses internal memory. pull-up low-to-high transactions (pu_od_0) epu1 other transactions. Boot Memory Select. chip select boot EPROM flash memory. During reset, uses strap (EBOOT) EPROM boot mode. multiproO/T cessor system, master drives BMS. details, Reset Booting (pu_0) Page EBOOT signal description Table Page Memory Select. asserted whenever accesses memory banks respectively. MS1-0 decoded memory address pins that change concurrently with ADDR pins. When ADDR31:27 0b00110, asserted. When ADDR31:27 MS1-0 (pu_0) 0b00111, asserted. multiprocessor systems, master drives MS1-0. Memory Select Host. asserted whenever accesses host address space (ADDR31 0b1). decoded memory address that changes concurMSH (pu_0) rently with ADDR pins. multiprocessor system, master drives MSH. Burst. current master (DSP host) asserts this indicate that reading writing data associated with consecutive addresses. slave device ignore addresses after first increment internal address counter after each I/O/T transfer. host-to-DSP burst accesses, increments address automatiBRST (pu_0) epu1 cally while BRST asserted. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS.
Signal
Type
Term
This external pull-up omitted TigerSHARC processor. Rev. Page November 2004
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Table Definitions-External Port Arbitration
Description Multiprocessing Request Pins. Used DSPs multiprocessor system arbitrate mastership. Each drives line (corresponding value ID2-0 inputs) monitors others. systems with fewer than eight BR7-0 VDD_IO1 DSPs, unused pins high (VDD_IO). Multiprocessor Indicates DSP's from which determines order multiprocessor system. These pins also indicate which request (BR0-BR7) assert when requesting bus: BR0, BR1, BR2, BR3, BR4, BR5, BR6, BR7. ID2-0 must have constant ID2-0 (pd) value during system operation change during reset only. Master. current master asserts debugging only. reset this strap pin. more information, Table Page Back Off. deadlock situation occur when host read from each other's same time. When deadlock occurs, host assert BOFF BOFF force relinquish before completing outstanding transaction. Lock Indication. Provides indication that current master locked BUSLOCK (pu_0) bus. reset, this strap pin. more information, Table Page Host Request. host must assert request control DSP's external bus. When asserted multiprocessing system, master relinquishes asserts once outstanding transaction finished. Host Grant. Acknowledges indicates that host take control external bus. When relinquishing bus, master three-states ADDR31-0, DATA63-0, MSH, MSSD3-0, MS1-0, WRL, WRH, BMS, BRST, IORD, IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM HDQM pins, puts SDRAM self-refresh mode. asserts until host deasserts HBR. I/O/T multiprocessor systems, current master drives HBG, slave DSPs (pu_0) epu2 monitor Core Priority Access. Asserted while DSP's core accesses external memory. This enables slave interrupt master DSP's background transfers gain control external core-initiated transactions. open drain I/O/OD output, connected DSPs system. required system, leave (pu_od_0) epu2 unconnected (external pull-ups will required through Priority Access. Asserted while high priority channel accesses external memory. This enables high priority channel slave interrupt transfers normal priority channel master gain control external DMA-initiated transactions. open drain output, I/O/OD connected DSPs system. required system, leave uncon(pu_od_0) epu2 nected (external pull-ups will required through input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS.
Signal
Type
Term
matching ID2-0 input selection processor should left unused. example, processor with BR7-1 VDD_IO. This external pull-up resistor omitted TigerSHARC processor.
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Table Definitions-External Port DMA/Flyby
Description Request Pins. Enable external devices request services from DSP. response DMARx, performs transfers according DMAR3-0 channel's initialization. ignores requests from uninitialized channels. Write. When channel initiates flyby mode read transaction, asserts IOWR signal during data cycles. This assertion makes device IOWR (pu_0) sample data instead TigerSHARC. Read. When channel initiates flyby mode write transaction, asserts IORD signal during data cycle. This assertion with IOEN makes IORD (pu_0) device drive data instead TigerSHARC. Device Output Enable. Enables output buffers external device flyO/T transactions between device external memory. Active flyby IOEN (pu_0) transactions. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal Type Term
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Table Definitions-External Port SDRAM Controller
Description Memory Select SDRAM. MSSD0, MSSD1, MSSD2, MSSD3 asserted whenever accesses SDRAM memory space. MSSD3-0 decoded memory address pins that asserted whenever issues SDRAM command cycle (access I/O/T ADDR31:30 0b01-except reserved spaces shown Figure Page multiMSSD3-0 (pu_0) processor system, master drives MSSD3-0. Address Select. When sampled low, indicates that address valid I/O/T read write SDRAM. other SDRAM accesses, defines type operation (pu_0) execute according SDRAM specification. Column Address Select. When sampled low, indicates that column address I/O/T valid read write SDRAM. other SDRAM accesses, defines type (pu_0) operation execute according SDRAM specification. Word SDRAM Data Mask. When sampled high, three-states SDRAM buffers. LDQM valid SDRAM transactions when asserted, inactive read transactions. write transactions, LDQM active when accessing LDQM (pu_0) address word 64-bit memory disable write word. High Word SDRAM Data Mask. When sampled high, three-states SDRAM buffers. HDQM valid SDRAM transactions when asserted, inactive read transactions. write transactions, HDQM active when accessing even address word accesses when memory configured 32-bit disable HDQM (pu_0) write high word. SDRAM Address Separate signals enable SDRAM refresh operation while SDA10 (pu_0) executes non-SDRAM transactions. SDRAM Clock Enable. Activates SDRAM clock SDRAM self-refresh suspend modes. slave multiprocessor system does have pull-up pullI/O/T down. master single processor system) pull-up before (pu_m/ granting host, except when SDRAM self refresh mode. SDCKE pd_m) self refresh mode, master pull-down before granting host. SDRAM Write Enable. When sampled while active, SDWE indicates SDRAM write access. When sampled high while active, SDWE indicates I/O/T SDRAM read access. other SDRAM accesses, SDWE defines type operation (pu_0) execute according SDRAM specification. SDWE input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal Type Term
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Table Definitions-JTAG Port
Description Emulation. Connected DSP's JTAG emulator target board connector only. Test Clock (JTAG). Provides asynchronous clock JTAG scan. Test Data Input (JTAG). serial data input scan path. Test Data Output (JTAG). serial data output scan path. Test Mode Select (JTAG). Used control test state machine. Test Reset (JTAG). Resets test state machine. TRST must asserted pulsed after power proper device operation. more information, Reset TRST (pu_ad) Booting Page input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS.
Signal
Type O/OD (pu_ad) (pu_ad)
Term epu1
reference Page JTAG emulation technical reference EE-68.
Table Definitions-Flags, Interrupts, Timer
Description FLAG pins. Bidirectional input/output pins used program conditions. Each I/O/A configured individually input output. FLAG3-0 inputs after power-up FLAG3-0 (pu) reset. Interrupt Request. When asserted, generates interrupt. Each IRQ3-0 pins independently edge-triggered level-sensitive operation. After reset, these pins disabled unless IRQ3-0 strap option interrupt vectors initialized IRQ3-0 (pu) booting. Timer expires. This output pulses whenever timer expires. reset, this strap pin. TMR0E more information, Table Page input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal Type Term
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Table Definitions-Link Ports
Description Link Ports Data Transmit LVDS Link Ports Data Transmit LVDS Link Ports Transmit Clock LVDS Link Ports Transmit Clock LVDS Link Ports Receive Acknowledge. Using this signal, receiver indicates LxACKI (pd) transmitter that continue transmission. Link Ports Block Completion. When transmission executed using DMA, this signal indicates receiver that transmitted block completed. pull-up resistor present L0BCMPO only. reset, L1BCMPO, L2BCMPO, L3BCMPO LxBCMPO (pu) pins strap pins. more information, Table Page LxDATI3-0P VDD_IO Link Ports Data Receive LVDS LxDATI3-0N VDD_IO Link Ports Data Receive LVDS LxCLKINP VDD_IO Link Ports Receive Clock LVDS LxCLKINN Link Ports Receive Clock LVDS Link Ports Transmit Acknowledge. Using this signal, receiver indicates LxACKO transmitter that continue transmission. Link Ports Block Completion. When reception executed using DMA, this LxBCMPI signal indicates receiver that transmitted block completed. (pd_l) input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up pd_l internal pull-down more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal LxDATO3-0P LxDATO3-0N LxCLKOUTP LxCLKOUTN Type Term
Table Definitions-Impedance Control, Drive Strength Control, Regulator Enable
Description Impedance Control. shown Table CONTROLIMP1-0 pins select between normal driver mode driver mode. When using normal mode (recommended), output drive strength relative maximum drive strength according Table When using mode, resistance control operates analog mode, CONTROLIMP0 (pd) where drive strength continuously controlled match specific line impedance CONTROLIMP1 (pu) shown Table Digital Drive Strength Selection. Selected shown Table drive strength calculation, Output Drive Currents Page drive strength some pins preset, controlled DS2-0 pins. pins that always drive strength (100%) DS2, (pu) include: CPA, DPA, TDO, EMU, RST_OUT. drive strength always (pd) drive strength (100%). Connect ENEDREG VSS. Connect VDD_DRAM pins properly decoupled ENEDREG (pu) DRAM power supply. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal Type Term
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Table Impedance Control Selection
CONTROLIMP1-0 (recommended) (default) Driver Mode Normal Reserved Mode Reserved
Table Drive Strength/Output Impedance Selection
DS2-0 Pins (default)
Drive Strength1 Strength (11.1%) Strength (23.8%) Strength (36.5%) Strength (49.2%) Strength (61.9%) Strength (74.6%) Strength (87.3%) Strength (100%)
Output Impedance
CONTROLIMP1 mode disabled. CONTROLIMP1 mode enabled.
Table Definitions-Power, Ground, Reference
Description pins internal logic. pins analog circuits. critical attention bypassing this supply. pins buffers. pins internal DRAM. Reference voltage defines trip point input buffers, except SCLK, RST_IN, POR_IN, IRQ3-0, FLAG3-0, DMAR3-0, ID2-0, CONTROLIMP1-0, LxDATO3-0P/N, LxCLKOUTP/N, LxDATI3-0P/N, LxCLKINP/N, TCK, TDI, TMS, TRST. VREF connected power supply voltage divider circuit shown Figure VREF more information, Filtering Reference Voltage Clocks Page System Clock Reference. Connect this reference voltage shown Figure more information, Filtering Reference Voltage Clocks Page SCLK_VREF Ground pins. Connect. connect these pins anything (not supply, signal, each other). These pins reserved must left unconnected. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page Term (termination unused pins) column symbols: external pull-down approximately VSS; external pull-up approximately VDD_IO, connected; applicable (always used); VDD_IO connect directly VDD_IO; connect directly VSS. Signal VDD_A VDD_IO VDD_DRAM Type Term
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STRAP FUNCTION DESCRIPTIONS
Some pins have alternate functions reset. Strap options operating modes. During reset, samples strap option pins. Strap pins have internal pull-up pull-down default value. strap connected overdriving external pull-up, pull-down, logic load, samples default value during reset. strap pins conTable Definitions-I/O Strap Pins
Signal Type Reset) Description EPROM Boot. boot from EPROM immediately after reset (default) idle after reset wait external device boot through external port link port Interrupt Enable. disable IRQ3-0 interrupts edge-sensitive after reset (default) enable IRQ3-0 interrupts level-sensitive immediately after reset Link Port Input Default Data Width. 1-bit (default) 4-bit SYSCON SDRCON Write Enable. one-time writable after reset (default) always writable
nected logic inputs, stronger external pull-up pull-down required ensure default value depending leakage and/or level input current logic load. mode other than default mode, connect strap sufficiently stronger external pull-up pull-down. Table lists describes each DSP's strap pins.
EBOOT
(pd_0)
IRQEN
(pd) (pd)
LINK_DWIDTH
TMR0E
(pd_0) BUSLOCK (pu) L1BCMPO Test Mode overdrive default value during reset. (pu) L2BCMPO Test Mode overdrive default value during reset. (pu) L3BCMPO Test Mode overdrive default value during reset. input; asynchronous; output; open drain output; three-state; power supply; ground; internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up pu_od_0 internal pull-up pd_m internal pull-down master; pu_m internal pull-up master; pu_ad internal pull-up more pull-down pull-up information, Electrical Characteristics Page SYS_REG_WE
When default configuration used, external resistor needed strap pins. apply other configurations, resistor connected VDD_IO required. providing external pull-downs, strap these pins directly VSS; strap pins require resistor straps. strap pins sampled rising edge RST_IN (deassertion edge). Each latches strapped state (state strap rising edge RST_IN). Shortly after deassertion RST_IN, these pins reconfigured their normal functionality. These strap pins have internal pull-down resistor, pull-up resistor, no-resistor (three-state) each pin. resistor type, which connected pad, depends whether RST_IN active (low) RST_IN deasserted (high). Table shows resistors that enabled during active reset during normal operation.
Table Strap Internal Resistors-Active Reset (RST_IN Normal Operation (RST_IN
RST_IN RST_IN (pd_0) (pu_0) (pd) Driven TMR0E (pd) Driven BUSLOCK (pd_0) (pu_0) L1BCMPO (pu) Driven L2BCMPO (pu) Driven L3BCMPO (pu) Driven internal pull-down internal pull-up pd_0 internal pull-down pu_0 internal pull-up
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ADSP-TS201S-SPECIFICATIONS
Note that component specifications subject change without notice. information Link port electrical characteristics, Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics Timing Page
RECOMMENDED OPERATING CONDITIONS
Parameter Internal Supply Voltage Test Conditions CCLK CCLK VDD_A VDD_IO Analog Supply Voltage CCLK CCLK Supply Voltage Internal DRAM Supply Voltage VDD_DRAM TCASE TCASE VIH1 VIH2 Case Operating Temperature Case Operating Temperature High Level Input Voltage High Level Input Voltage
Grade1 (all)
1.14 1.00 1.14 1.00 2.38 1.52 1.425
1.20 1.05 1.20 1.05 2.50 1.60 1.500
1.26 1.10 1.26 1.10 2.63 1.68 1.575 +105
Unit
CCLK CCLK
VDD, VDD_IO VDD, VDD_IO VDD, VDD_IO CCLK MHz, 1.20 TCASE CCLK MHz, 1.05 TCASE
(all) (all) (all) (all) (all) (all)
Level Input Voltage4 Supply Current, Typical Activity5
2.61 2.06 0.15 0.28 0.25 0.43 0.40
IDD_A IDD_IO IDD_DRAM VREF
VDD_A Supply Current, Typical Activity VDD_IO Supply Current, Typical Activity
CCLK MHz, 1.20 TCASE CCLK MHz, 1.05 TCASE SCLK 62.5 MHz, VDD_IO TCASE CCLK MHz, VDD_DRAM TCASE CCLK MHz, VDD_DRAM TCASE
VDD_DRAM Supply Current, Typical Activity5 Voltage Reference
(VDD_IO (VCLOCK_DRIVE
SCLK_VREF Voltage Reference
Specifications vary different grades (for example, SABP-060, SABP-050, SWBP-050). more information part grades, Ordering Guide Page VIH1 specification applies input bidirectional pins: SCLKRAT2-0, SCLK, ADDR31-0, DATA63-0, WRL, WRH, ACK, BRST, BR7-0, BOFF, HBR, HBG, MSSD3-0, RAS, CAS, SDCKE, SDWE, TCK, FLAG3-0, DS2-0, ENEDREG. VIH2 specification applies input bidirectional pins: TDI, TMS, TRST, CIMP1-0, ID2-0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3-0, CPA, DPA, DMAR3-0. Applies input bidirectional pins. details internal external power calculation issues, including other operating conditions, EE-170, Estimating Power ADSP-TS201S Analog Devices website.
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ELECTRICAL CHARACTERISTICS
Parameter IIH_PU IIH_PD IIH_PD_I IIL_PU IIL_PU_AD IOZH IOZH_PD IOZL IOZL_PU IOZL_PU_AD IOZL_OD High Level Output Voltage Level Output Voltage High Level Input Current High Level Input Current High Level Input Current High Level Input Current Level Input Current Level Input Current Level Input Current Three-State Leakage Current High Three-State Leakage Current High Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Input Capacitance2,
Test Conditions @VDD_IO min, @VDD_IO min, @VDD_IO max, @VDD_IO max, @VDD_IO max, VDD_IO @VDD_IO max, @VDD_IO max, @VDD_IO max, @VDD_IO max, @VDD_IO max, @VDD_IO max, VDD_IO @VDD_IO max, @VDD_IO max, @VDD_IO max, @VDD_IO max, @fIN MHz, TCASE
2.18
Unit
0.76 0.76 0.76 0.76
Parameter name suffix conventions: suffix applies pins without pull-up pull-down resistors, applies types (pd) (pd_0), applies types (pu) (pu_0), _PU_AD applies types (pu_ad), applies types
Applies output bidirectional pins. Applies signals. Guaranteed tested.
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ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDD)1 Analog (PLL) Supply Voltage (VDD_A)1 External (I/O) Supply Voltage (VDD_IO)1 External (DRAM) Supply Voltage (VDD_DRAM) Input Voltage
-0.3 +1.40 -0.3 +1.40 -0.3 +3.5 -0.3 +2.1 -0.5 +3.63 -0.5 VDD_IO +0.5
Output Voltage Swing
Storage Temperature Range1
Stresses greater than those listed above cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADSP-TS201S features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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TIMING SPECIFICATIONS
With exception DMAR3-0, IRQ3-0, TMR0E, FLAG3-0 (input only) pins, timing ADSP-TS201S processor relative reference clock edge. Because input setup/hold, output valid/hold, output enable/disable times relative clock edge, timing data ADSPTS201S processor calculated (formula-based) values. information timing, General Timing. information Link port transfer timing, Link Port LowVoltage, Differential-Signal (LVDS) Electrical Characteristics Timing Page
General Timing
Timing measured signals when they cross 1.25 level described Figure Page delays nanoseconds) measured between point that first signal reaches 1.25 point that second signal reaches 1.25 asynchronous timing data IRQ3-0, DMAR3-0, FLAG3-0, TMR0E pins appears Table Table Asynchronous Signal Specifications
Name IRQ3-01 DMAR3-01 FLAG3-02 TMR0E3
Description Interrupt Request Request FLAG3-0 Input Timer Expired
Pulse Width (min) tSCLK tSCLK
Pulse Width High (min) tSCLK tSCLK
These input pins have Schmitt triggers therefore need synchronized clock reference. output specifications FLAG3-0 pins, Table This strap option. During reset, internal resistor pulls low.
general timing data appears Table Table specifications measured with load specified Figure Page with output drive strength strength order calculate output valid hold times different load conditions and/or output drive strengths, refer Figure Page through Figure Page (Rise Fall Time Load Capacitance) Figure Page (Output Valid Load Capacitance Drive Strength).
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Table Reference Clocks-Core Clock (CCLK) Cycle Time
Grade (600MHz) 1.67 12.5 Grade (500MHz) 12.5
Parameter tCCLK1
Description Core Clock Cycle Time
Unit
CCLK internal processor clock instruction cycle time. period this clock equal system clock period (tSCLK) divided system clock ratio (SCLKRAT2-0). information available part numbers different internal processor clock rates, Ordering Guide Page
tCCLK
CCLK
Figure Reference Clocks-Core Clock (CCLK) Cycle Time
Table Reference Clocks-System Clock (SCLK) Cycle Time
SCLKRAT 0.40 tSCLK 0.60 tSCLK 0.40 tSCLK 0.60 tSCLK SCLKRAT 0.45 tSCLK 0.55 tSCLK 0.45 tSCLK 0.55 tSCLK
Parameter tSCLK1, tSCLKH tSCLKL tSCLKF tSCLKR tSCLKJ5,
Description System Clock Cycle Time System Clock Cycle High Time System Clock Cycle Time System Clock Transition Time-Falling Edge4 System Clock Transition Time-Rising Edge System Clock Jitter Tolerance
Unit
more information, Table Page more information, Clock Domains Page value (tSCLK SCLKRAT2-0) must violate specification tCCLK. System clock transition times apply minimum SCLK cycle time (tSCLK) only. Actual input jitter should combined with specifications accurate timing analysis. Jitter specification maximum peak-to-peak time interval error (TIE) jitter.
tSCLK tSCLKH tSCLKL tSCLKJ tSCLKF tSCLKR
SCLK
Figure Reference Clocks-System Clock (SCLK) Cycle Time
Table Reference Clocks-JTAG Test Clock (TCK) Cycle Time
Parameter tTCK tTCKH tTCKL Description Test Clock (JTAG) Cycle Time Test Clock (JTAG) Cycle High Time Test Clock (JTAG) Cycle Time
tTCK tTCKH tTCKL
Greater tCCLK
Unit
Figure Reference Clocks-JTAG Test Clock (TCK) Cycle Time
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ADSP-TS201S
Table Power-Up Timing1
Parameter Timing Requirements tVDD_DRAM VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable
Unit
information about power supply sequencing monitoring solutions, please visit
tVDD_DRAM
VDD_A VDD_IO
VDD_DRAM
Figure Power-Up Timing
Table Power-Up Reset Timing
Parameter Timing Requirements tRST_IN_PWR RST_IN Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK, Static/Strap Pins Stable TRST Asserted During Power-Up Reset tTRST_IN_PWR1 Switching Characteristic tRST_OUT_PWR RST_OUT Deasserted After RST_IN Deasserted
tSCLK
Unit
Applies after VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK stable before RST_IN deasserted.
tRST_IN_PWR
RST_IN
tRST_OUT_PWR
RST_OUT
tTRST_PWR
TRST
SCLK, VDD, VDD_A, VDD_IO, VDD_DRAM STATIC/STRAP PINS
Figure Power-Up Reset Timing
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Table Normal Reset Timing
Parameter Timing Requirements tRST_IN RST_IN Asserted RST_IN Deasserted After Strap Pins Stable tSTRAP Switching Characteristic tRST_OUT RST_OUT Deasserted After RST_IN Deasserted
tRST_IN
Unit
RST_IN
tRST_OUT
RST_OUT
tSTRAP
STRAP PINS
Figure Normal Reset Timing
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Table Signal Specifications
(All values this table nanoseconds.) Output Disable (max)1 Output Enable (min)1 Output Valid (max) Output Hold (min) Input Setup (min) Input Hold (min)
Name ADDR31-0 DATA63-0 MSSD3-0 MS1-0 SDCKE SDWE LDQM HDQM SDA10 BOFF BUSLOCK BRST BR7-0 IORD IOWR IOEN FLAG3-02 RST_IN TRST ID2-08 CONTROLIMP1-08
Description External Address External Data Memory Select HOST Line Memory Select SDRAM Lines Memory Select Static Blocks Memory Read Write Word Write High Word Acknowledge Data High Acknowledge Data High SDRAM Clock Enable Address Select Column Address Select SDRAM Write Enable Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Request Host Grant Back Request Lock Burst Multiprocessing Request Pins Master Debug Only Read Write Enable Core Priority Access High Core Priority Access High Priority Access High Priority Access High Boot Memory Select FLAG Pins Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Emulation High Static Pins-Must Constant Static Pins-Must Constant
0.75 0.75 0.75 0.75 0.75 0.75
29.5 29.5
1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 0.75 0.75 0.75 0.75 1.15 1.15 0.75 1.15
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK5 TCK6 SCLK
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Reference Clock
ADSP-TS201S
Table Signal Specifications (Continued)
(All values this table nanoseconds.) Output Disable (max)1 Output Enable (min)1 Output Valid (max) Output Hold (min) Input Setup (min) Input Hold (min)
Name DS2-08 SCLKRAT2-08 ENEDREG STRAP SYS9, JTAG SYS11,
Description Static Pins-Must Constant Static Pins-Must Constant Static Pins-Must Connected Strap Pins JTAG System Pins
10.0
12.0
-1.0
SCLK
external port protocols employ IDLE cycles mastership transitions well slave access boundary crossings avoid potential contention. apparent driver overlap, output disables being larger than output enables, actual. input specifications FLAG3-0 pins, Table These input pins asynchronous therefore need synchronized clock reference. additional requirement details, Reset Booting Page RST_IN clock reference falling edge SCLK. output clock reference falling edge TCK. Reference clock depends function. These pins change only during reset; recommend connecting VDD_IO/VSS. STRAP pins include: BMS, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, L3BCMPO. Specifications applicable during reset only. JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3-0, DMAR3-0, HBR, BOFF, MS1-0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, EMU, SDA10, IOEN, BUSLOCK, TMR0E, DATA63-0, ADDR31-0, WRL, WRH, BRST, MSSD3-0, RAS, CAS, SDWE, HBG, BR7-0, FLAG3-0, L0DATOP3-0, L0DATON3-0, L1DATOP3-0, L1DATON3-0, L2DATOP3-0, L2DATON3-0, L3DATOP3-0, L3DATON3-0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP, L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3-0, L0DATIN3-0, L1DATIP3-0, L1DATIN3-0, L2DATIP3-0, L2DATIN3-0, L3DATIP3-0, L3DATIN3-0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO, L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2-0, CTRL_IMPD1-0, SCLKRAT2-0, DS2-0, ENEDREG. JTAG system output timing clock reference falling edge TCK.
REFERENCE CLOCK 1.25V
tSCLK tTCK
INPUT SIGNAL 1.25V INPUT SETUP INPUT HOLD
OUTPUT SIGNAL OUTPUT VALID 1.25V OUTPUT HOLD
THREESTATE OUTPUT DISABLE OUTPUT ENABLE
Figure General Parameters Timing
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Reference Clock
ADSP-TS201S
Link Port Low-Voltage, Differential-Signal (LVDS) Electrical Characteristics Timing
Table Table with Figure provide electrical characteristics LVDS link ports. LVDS link port signal definitions represent differential signals with level signal naming without (negative) (positive) suffixes (see Figure 16). Table Link Port LVDS Transmit Electrical Characteristics
Parameter |VOD| VOCM Test Conditions VO_P VO_N 0.92 1.85 +5/- +/-10 1.50 Unit
Output Voltage High, VO_P VO_N Output Voltage Low, VO_P VO_N Output Differential Voltage Short-Circuit Output Current Common-Mode Output Voltage
1.20
Table Link Port LVDS Receive Electrical Characteristics
Parameter |VID| VICM Test Conditions Differential Input Voltage Common-Mode Input Voltage 1.57 Unit
VO_P
(VO_P VO_N (VO_P VO_N
VOCM VO_N
Figure Link Ports-Transmit Electrical Characteristics
DIFFERENTIAL PAIR WAVEFORMS Lx<PIN>P
Lx<PIN>N
DIFFERENTIAL LTAG WAVEFORM Lx<PIN>
Figure Link Ports-Signals Definition
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Link Port-Data Timing Table with Figure Figure Figure Figure Figure Figure provide data timing LVDS link ports. Table Link Port-Data Timing
Parameter Outputs tREO tFEO tLCLKOP tLCLKOH tLCLKOL tCOJT tLDOS Rising Edge (Figure Falling Edge (Figure LxCLKOUT Period (Figure LxCLKOUT High (Figure LxCLKOUT (Figure LxCLKOUT Jitter (Figure 17)3 Greater tCCLK1, tLCLKOP1 tLCLKOP1 tCCLK1, tLCLKOP1 tLCLKOP1 Unit tCCLK1, tCCLK1,
tLDOH
tLACKID tBCMPOV tBCMPOH Inputs
Smaller 2.54 LxDATO Output Setup, (Figure 0.25 tCCLK 0.151, Smaller 2.54 LxDATO Output Setup, (Figure 0.25 tCCLK 0.31, Smaller LxDATO Output Hold, (Figure 0.25 tCCLK 0.151, Smaller LxDATO Output Hold, (Figure 0.25 tCCLK 0.31, Delay from LxACKI rising edge first transmission clock edge (Figure LxBCMPO Valid (Figure LxBCMPO Hold (Figure 0.51, LxACKI setup guarantee that transmitter stops transmitting (Figure LxACKI high setup guarantee that transmitter continues transmission without interruption (Figure tCCLK1, LxACKI High Hold Time (Figure 0.51
tLACKIS tLACKIH
Timing relative differential voltage (VOD (link port clock ratio) 1.5, tCCLK core period. Note that LCLK maximum (for example, then CCLK must MHz). -/+100 value applies LCLKOUT MHz. value tLDOS applies LCLKOUT MHz. tLDOS tLDOH values include LCLKOUT jitter. short-word transmission period. 4-bit link, tCCLK. 1-bit link, tCCLK
tLCLKOP
LxCLKOUT
tCOJT
tLCLKOH
tLCLKOL
Figure Link Ports-Output Clock
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ADSP-TS201S
VO_P CL_P 0.1pF CL_P CL_N CL_N
LxCLKOUT
VO_N
tLDOS tLDOH tLDOS tLDOH
tREO
tFEO
LxDATO
-|VOD|
Figure Link Ports-Differential Output Signals Transition Time
Figure Link Ports-Data Output Setup Hold1
These parameters valid both clock edges.
LxCLKOUT
LxDATO
tLACKID
LxACKI
tBCMPOV
LxBCMPO
Figure Link Ports-Transmission Start
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FIRST EDGE SHORT WORD QUAD WORD LAST EDGE QUAD WORD LxCLKOUT
LxDATO
tLACKIS
tLACKIH
LxACKI
tBCMPOH
LxBCMPO
Figure Link Ports-Transmission Stops
LAST EDGE QUAD WORD
LxCLKOUT
LxDATO
tLACKIS
tLACKIH
LxACKI
Figure Link Ports-Back Back Transmission
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ADSP-TS201S
Link Port-Data Timing Table with Figure Figure provide data timing LVDS link ports. Table Link Port-Data Timing
Parameter Inputs tLCLKIP tLDIS tLDIH tBCMPIS tBCMPIH
Greater tCCLK1 0.21 0.21 tLCLKIP1 tLCLKIP1
Unit
LxCLKIN Period (Figure LxDATI Input Setup (Figure LxDATI Input Hold (Figure LxBCMPI Setup (Figure LxBCMPI Hold (Figure
Timing relative differential voltage (VOD
FIRST EDGE FIFTH SHORT WORD QUAD WORD LxCLKIN
LxDATI
tBCMPIS
tBCMPIH
LxBCMPI
Figure Link Ports-Last Received Quad Word
tLCLKIP
LxCLKIN
tLDIS
tLDIH
tLDIS
tLDIH
LxDATI
Figure Link Ports-Data Input Setup Hold1
These parameters valid both clock edges.
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ADSP-TS201S
OUTPUT DRIVE CURRENTS
Figure through Figure show typical characteristics output drivers ADSP-TS201S processor. curves these diagrams represent current drive capability output drivers function output voltage over range drive strengths. Typical drive currents intermediate temperatures (such 85°C) should obtained from curves using linear interpolation. complete output driver characteristics, refer DSP's IBIS models, available Analog Devices website (www.analog.com).
STRENGTH 15.0 12.5 10.0
OUTPUT CURRENT
STRENGTH
OUTPUT CURRENT
VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
VDD_IO 2.63V, -40°C
VDD_IO 2.63V, -40°C
VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
VDD_IO 2.63V, -40°C VDD_IO 2.5V, +25°C VDD_IO 2.63V, -40°C
OUTPUT VOLTAGE
-2.5
Figure Typical Drive Currents Strength
STRENGTH
VDD_IO 2.38V, +105°C
VDD_IO 2.5V, +25°C
-5.0 VDD_IO 2.38V, +105°C -7.5
OUTPUT CURRENT
-10.0 -12.5 -15.0 OUTPUT VOLTAGE
VDD_IO 2.63V, -40°C VDD_IO 2.5V, +25°C VDD_IO 2.63V, -40°C VDD_IO 2.38V, +105°C VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
Figure Typical Drive Currents Strength
STRENGTH
OUTPUT CURRENT
OUTPUT VOLTAGE
VDD_IO 2.38V, +105°C VDD_IO 2.5V, +25°C
VDD_IO 2.63V, -40°C VDD_IO 2.63V, -40°C
Figure Typical Drive Currents Strength
VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
STRENGTH
OUTPUT CURRENT
OUTPUT VOLTAGE
VDD_IO 2.38V, +105°C VDD_IO 2.38V, +105°C VDD_IO 2.5V, +25°C VDD_IO 2.5V, +25°C
VDD_IO 2.63V, -40°C VDD_IO 2.63V, -40°C
Figure Typical Drive Currents Strength
OUTPUT VOLTAGE
Figure Typical Drive Currents Strength
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ADSP-TS201S
STRENGTH
OUTPUT CURRENT
TEST CONDITIONS
signal specifications (timing parameters) appear Table Page These include output disable time, output enable time, capacitive loading. timing specifications apply voltage reference levels Figure
VDD_IO 2.5V, +25°C
VDD_IO 2.63V, -40°C VDD_IO 2.63V, -40°C VDD_IO 2.38V, +105°C VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
INPUT OUTPUT
1.25V
1.25V
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
OUTPUT VOLTAGE
Output Disable Time
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation: DECAY
Figure Typical Drive Currents Strength
STRENGTH -100
OUTPUT CURRENT
VDD_IO 2.63V, -40°C VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C VDD_IO 2.63V, -40°C
VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
output disable time tDIS difference between tMEASURED_DIS tDECAY shown Figure time tMEASURED_DIS interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY calculated with test loads with equal
OUTPUT VOLTAGE
REFERENCE SIGNAL
tMEASURED_DIS
tMEASURED_ENA tENA
Figure Typical Drive Currents Strength
tDIS
(MEASURED)
STRENGTH -100 -110
(MEASURED) (MEASURED) (MEASURED)
1.65V 0.85V
tDECAY
OUTPUT STOPS DRIVING
tRAMP
OUTPUT STARTS DRIVING
OUTPUT CURRENT
VDD_IO 2.63V, -40°C VDD_IO 2.5V, +25°C VDD_IO 2.63V, -40°C VDD_IO 2.38V, +105°C VDD_IO 2.5V, +25°C VDD_IO 2.38V, +105°C
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE APPROXIMATELY 1.25V.
Figure Output Enable/Disable
OUTPUT VOLTAGE
Figure Typical Drive Currents Strength
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ADSP-TS201S
Output Enable Time
Output pins considered enabled when they have made transition from high impedance state when they start driving. time voltage ramp dependent capacitive load, drive current, This ramp time approximated following equation: RAMP output enable time tENA difference between tMEASURED_ENA tRAMP shown Figure time tMEASURED_ENA interval from when reference signal switches when output voltage ramps from measured three-stated output level. tRAMP calculated with test load drive current with equal
RISE FALL TIMES
STRENGTH (VDD_IO 2.5V)
FALL TIME 0.1527X 0.7485
RISE TIME 0.1501X 0.05
LOAD CAPACITANCE
Capacitive Loading
Output valid hold based standard capacitive loads: pins (see Figure 35). delay hold specifications given should derated drive strength related factor loads other than nominal value Figure through Figure show output rise time varies with capacitance. Figure graphically shows output valid varies with load capacitance. (Note that this graph derating does apply output disable delays; Output Disable Time Page 36.) graphs Figure through Figure linear outside ranges shown.
OUTPUT 1.25V 30pF
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH (VDD_IO 2.5V)
RISE FALL TIMES
FALL TIME 0.0949X 0.8112
RISE TIME 0.0861X 0.4712
Figure Equivalent Device Loading Measurements (Includes Fixtures)
STRENGTH (VDD_IO 2.5V)
RISE FALL TIMES
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH
FALL TIME 0.251X 4.2245
(VDD_IO 2.5V)
RISE FALL TIMES
RISE TIME 0.259X 3.0842
FALL TIME 0.0691X 1.1158
RISE TIME 0.06X 1.1362
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
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ADSP-TS201S
STRENGTH (VDD_IO 2.5V)
STRENGTH (VDD_IO 2.5V)
RISE FALL TIMES
RISE FALL TIMES
FALL TIME 0.0592X 1.0629
RISE TIME
RISE TIME
FALL TIME 0.0313X 0.818
0.0321X 0.6512
0.0573X 0.9789 LOAD CAPACITANCE
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH (VDD_IO 2.5V)
RISE FALL TIMES
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH (VDD_IO 2.5V)
OUTPUT VALID
FALL TIME 0.0493X 0.8389
RISE TIME 0.0481X 0.7889
LOAD CAPACITANCE
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
Figure Typical Output Valid (VDD_IO Load Capacitance Case Temperature Strength 0-71
line equations output valid load capacitance are: Strength 0.1255x 2.7873 Strength 0.0764x 1.0492 Strength 0.0474x 1.0806 Strength 0.0345x 1.2329 Strength 0.0296x 1.2064 Strength 0.0246x 1.0944 Strength 0.0187x 1.1005 Strength 0.0156x 1.084
STRENGTH (VDD_IO 2.5V)
RISE FALL TIMES
RISE TIME
FALL TIME 0.0374X 0.851
0.0377X 0.7449
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
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ADSP-TS201S
ENVIRONMENTAL CONDITIONS
ADSP-TS201S processor rated performance under TCASE environmental conditions specified Recommended Operating Conditions Page
Thermal Characteristics
ADSP-TS201S processor packaged thermally enhanced ball grid array (BGA_ED). ADSPTS201S processor specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heat sink and/or flow source required. Table shows thermal characteristics BGA_ED package. parameters based JESD51-9 four-layer 2s2p board. data based power dissipation. Table Thermal Characteristics Package
Parameter Condition Airflow Airflow Airflow Airflow Typical 12.92 10.2 Unit °C/W °C/W °C/W °C/W °C/W °C/W
measured JEDEC standard JESD51-6. 12.9°C/W vertically mounted boards. horizontally mounted boards, 17.0°C/W m/s. measured JEDEC standard JESD51-9. measured cold plate test method approved JEDEC standard).
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ADSP-TS201S
576-BALL BGA_ED CONFIGURATIONS
Figure shows summary configurations 576ball BGA_ED package Table lists signal-to-ball assignments.
VDD_IO VDD_DRAM VDD_A VREF KEY: SIGNAL
VIEW
Figure 576-Ball BGA_ED Configurations1 (Top View, Summary)
more detailed summary diagram, EE-179: ADSP-TS201S System Design Guidelines Analog Devices website (www.analog.com).
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ADSP-TS201S
Table 576-Ball BGA_ED Assignments
Signal Name DATA51 DATA49 DATA43 DATA41 DATA37 DATA33 DATA29 DATA25 DATA23 DATA19 DATA15 DATA11 DATA9 DATA5 DATA1 ADDR30 ADDR28 ADDR22 ADDR21 DATA61 DATA62 DATA57 DATA58 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR15 ADDR14 ADDR11 ADDR10 Signal Name DATA53 DATA50 DATA44 DATA42 DATA38 DATA34 DATA30 DATA26 DATA24 DATA20 DATA16 DATA12 DATA10 DATA6 DATA2 ADDR31 ADDR29 ADDR23 ADDR18 DATA63 DATA59 DATA60 VDD_IO VDD_DRAM VDD_DRAM VDD_DRAM VDD_DRAM VDD_IO ADDR13 ADDR12 ADDR9 ADDR8 Signal Name DATA52 DATA47 DATA45 DATA39 DATA35 DATA31 DATA27 DATA21 DATA17 DATA13 DATA7 DATA3 ADDR26 ADDR24 ADDR20 VDD_IO VDD_IO MSSD1 VDD_DRAM VDD_DRAM VDD_DRAM VDD_DRAM VDD_IO ADDR7 ADDR6 ADDR5 ADDR4 Signal Name DATA55 DATA56 DATA54 DATA48 DATA46 DATA40 DATA36 DATA32 DATA28 DATA22 DATA18 DATA14 DATA8 DATA4 DATA0 BRST ADDR27 ADDR25 ADDR19 ADDR17 ADDR16 MSSD3 SCLKRAT0 VDD_IO VDD_IO ADDR3 ADDR2 ADDR1 ADDR0
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ADSP-TS201S
Table 576-Ball BGA_ED Assignments (Continued)
Signal Name VREF L0ACKO L0BCMPI L0DATI0_N L0DATI0_P VDD_A VDD_A VDD_IO VDD_IO L0DATO2_N L0DATO2_P L0CLKON L0CLKOP Signal Name SDA10 SDCKE LDQM HDQM VDD_IO VDD_DRAM VDD_DRAM VDD_IO L0DATI1_N L0DATI1_P L0CLKINN L0CLKINP SCLK SCLK_VREF VDD_IO VDD_DRAM VDD_DRAM VDD_IO L0DATO1_N L0DATO1_P L0DATO0_N L0DATO0_P Signal Name SDWE VDD_IO VDD_DRAM VDD_DRAM VDD_IO L0DATI3_N L0DATI3_P L0DATI2_N L0DATI2_P (SCLK)1 (SCLK_VREF)1 VDD_IO VDD_DRAM VDD_DRAM VDD_IO L0BCMPO L0ACKI Signal Name SCLKRAT1 VDD_IO VDD_IO L0DATO3_N L0DATO3_P RST_IN SCLKRAT2 L1DATI0_N L1DATI0_P L1ACKO L1BCMPI
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ADSP-TS201S
Table 576-Ball BGA_ED Assignments (Continued)
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
Signal Name MSSD0 RST_OUT VDD_IO VDD_DRAM VDD_IO L1CLKINN L1CLKINP L1DATI1_N L1DATI1_P FLAG2 FLAG1 IRQ3 IRQ0 IOEN DMAR0 L3BCMPO L3DATO1_N L3DATO3_N L3DATI2_N L3DATI1_N L2DATO0_N L2CLKON L2DATO3_N L2CLKINN L2DATI1_N L1BCMPO L1DATO0_N L1DATO0_P
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
Signal Name MSSD2 POR_IN CONTROLIMP1 VDD_DRAM VDD_DRAM VDD_DRAM VDD_DRAM VDD_IO L1DATI3_N L1DATI3_P L1DATI2_N L1DATI2_P IRQ2 IRQ1 DMAR1 L3ACKI L3DATO1_P L3DATO3_P L3DATI2_P L3DATI1_P L2DATO0_P L2CLKOP L2DATO3_P L2CLKINP L2DATI1_P L2ACKO VDD_IO VDD_IO
AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24
Signal Name CONTROLIMP0 ENEDREG VDD_IO VDD_DRAM VDD_DRAM VDD_DRAM VDD_DRAM VDD_IO L1CLKON L1CLKOP L1DATO3_N L1DATO3_P FLAG0 VDD_IO IOWR DMAR2 BOFF L3DATO0_N L3CLKON L3DATO2_N L3DATI3_N L3CLKINN L3DATI0_N L3ACKO L2BCMPO L2DATO1_N L2DATO2_N L2DATI3_N L2DATI2_N L2DATI0_N VDD_IO L1ACKI
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24
Signal Name TMR0E FLAG3 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO L1DATO1_N L1DATO1_P L1DATO2_N L1DATO2_P VDD_IO TRST IORD DMAR3 BUSLOCK L3DATO0_P L3CLKOP L3DATO2_P L3DATI3_P L3CLKINP L3DATI0_P L3BCMPI L2ACKI L2DATO1_P L2DATO2_P L2DATI3_P L2DATI2_P L2DATI0_P VDD_IO L2BCMPI
revision silicon, pins revision silicon, SCLK, SCLK_VREF. more information SCLK SCLK_VREF revision silicon, EE-179: ADSP-TS20x TigerSHARC System Design Guidelines Analog Devices website (www.analog.com).
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ADSP-TS201S
OUTLINE DIMENSIONS
ADSP-TS201S processor available 576-ball metric thermally enhanced ball grid array (BGA_ED) package with rows balls (BP-576).
25.20 25.00 24.80
1.25 1.00 0.75
BALL INDICATOR 23.00
1.00
25.20 25.00 24.80
1.00 BALL PITCH
1.25 1.00 0.75
1.00
25.20 25.00 24.80
VIEW
DETAIL 3.10 0.97
BOTTOM VIEW
1.60 0.60 0.50 0.40
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL WITHIN 0.25 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10 IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS OMINAL. THIS PACKAGE ONFORMS WITH JEDEC MS-034 SPECIFICATION.
SEATING PLANE BALL DIAMETER
0.75 0.65 0.55
0.20
DETAIL
Figure 576-Ball BGA_ED (BP-576)
ORDERING GUIDE
Case Temperature Range -40°C +85°C -40°C +85°C -40°C +105°C Instruction Rate6 On-Chip DRAM Operating Voltage 1.20 VDD, VDD_IO, VDD_DRAM 1.05 VDD, VDD_IO, VDD_DRAM 1.05 VDD, VDD_IO, VDD_DRAM
Part Number1, ADSP-TS201SABP-060 ADSP-TS201SABP-050 ADSP-TS201SWBP-050
Package (BP-576)7 (BP-576) (BP-576)
indicates 1.xx/2.5 supplies. indicates -40°C +85°C temperature. indicates -40°C +105°C temperature. indicates thermally enhanced ball grid array (BGA_ED) package. -060 indicates operation, -050 indicates operation. instruction rate same internal processor core clock (CCLK) rate. BP-576 package measures
2004 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D04324-0-11/04(0)
Rev.
Page
November 2004
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